| commit | 53cec00aa6789382621a53b33b13f45bd27148ca | [log] [tgz] |
|---|---|---|
| author | Udayan Banerji <udayan.banerji@intel.com> | Fri Sep 26 10:41:47 2014 -0700 |
| committer | Udayan Banerji <udayan.banerji@intel.com> | Fri Sep 26 10:41:47 2014 -0700 |
| tree | 54739a2f5db0d11267c0fc108dfd56257efddb51 | |
| parent | 628a74f9365f7d18dbd1fcc6b2f2661780574b4f [diff] |
ART: Fix GenReduceVector and GenSetVector For GenReduceVector: We now correctly load non-wide values for non-wide destination registers, and generate reg-reg and reg-mem forms of pextr correctly. For GenSetVector: We use the correct opcode from loading into an xmm from a 64-bit GPR Change-Id: I0a01d1f0b12b32a0dee8f79a0139ffcf6d6cb4d5 Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>