commit 55bd45f4ea40b9a0af323f813d07f23d7a8ed397
author Ian Rogers <irogers@google.com> Wed Apr 04 17:31:20 2012 -0700
committer Ian Rogers <irogers@google.com> Wed Apr 04 18:23:36 2012 -0700
tree f315fc79924662e612c6825b6d9b20ba2178853e
parent 5e284224e5525ee0a8494a73d84c8ef86e022a0a

More X86 fixes.

Support for long divides and sparse switches.

Change-Id: I07cdf6a9a2e4c6156cc70a429bf58f22e0e45ef1

src/compiler/codegen/GenCommon.cc

diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc
index 444f5f2..aeacab8 100644
--- a/src/compiler/codegen/GenCommon.cc
+++ b/src/compiler/codegen/GenCommon.cc
@@ -1858,7 +1858,7 @@
     } else {
         RegLocation rlResult;
         oatFlushAllRegs(cUnit);   /* Send everything to home location */
-        loadValueDirectFixed(cUnit, rlSrc2, rRET1);
+        loadValueDirectFixed(cUnit, rlSrc2, rARG1);
 #if !defined(TARGET_X86)
         int rTgt = loadHelper(cUnit, funcOffset);
 #endif
@@ -2197,14 +2197,17 @@
             retReg = rRET0;
             funcOffset = ENTRYPOINT_OFFSET(pLdivmod);
             break;
-        /* NOTE - result is in rARG2/rARG3 instead of rRET0/rRET1 */
-        // FIXME: is true, or could be made true, or other targets?
         case Instruction::REM_LONG:
         case Instruction::REM_LONG_2ADDR:
             callOut = true;
             checkZero = true;
-            funcOffset = ENTRYPOINT_OFFSET(pLdivmod);
+            funcOffset = ENTRYPOINT_OFFSET(pLdiv);
+#if defined(TARGET_ARM)
+            /* NOTE - result is in rARG2/rARG3 instead of rRET0/rRET1 */
             retReg = rARG2;
+#else
+            retReg = rRET0;
+#endif
             break;
         case Instruction::AND_LONG_2ADDR:
         case Instruction::AND_LONG: