commit 67bc236a207852d652f6ddeab0a90efc1bd111bb
author buzbee <buzbee@google.com> Tue Oct 11 18:08:40 2011 -0700
committer buzbee <buzbee@google.com> Fri Oct 14 10:54:03 2011 -0700
tree eea13fcb90ad8ce5b2b3819fb8caf0281583cd61
parent 95caa791e560da97363c0c0d22bfda4a7e7377c3

Register promotion fix

Restructured the type inference mechanism, added lots of DCHECKS,
bumped the default memory allocation size to reflect AOT
compilation and tweaked the bit vector manipulation routines
to be better at handling large sparse vectors (something the old
trace JIT didn't encounter enough to care).

With this CL, optimization is back on by default.  Should also see
a significant boost in compilation speed (~2x better for boot.oat).

Change-Id: Ifd134ef337be173a1be756bb9198b24c5b4936b3

src/compiler/codegen/RallocUtil.cc

diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index 7fd062d..1b0fb90 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -186,9 +186,10 @@
             cUnit->coreSpillMask |= (1 << res);
             cUnit->coreVmapTable.push_back(sReg);
             cUnit->numCoreSpills++;
-            cUnit->regLocation[sReg].location = kLocPhysReg;
-            cUnit->regLocation[sReg].lowReg = res;
-            cUnit->regLocation[sReg].home = true;
+            //  Should be promoting based on initial sReg set
+            DCHECK_EQ(sReg, oatS2VReg(cUnit, sReg));
+            cUnit->promotionMap[sReg].coreLocation = kLocPhysReg;
+            cUnit->promotionMap[sReg].coreReg = res;
             break;
         }
     }
@@ -231,10 +232,11 @@
             ((FPRegs[i].reg & 0x1) == 0) == even) {
             res = FPRegs[i].reg;
             FPRegs[i].inUse = true;
+            //  Should be promoting based on initial sReg set
+            DCHECK_EQ(sReg, oatS2VReg(cUnit, sReg));
             markPreservedSingle(cUnit, sReg, res);
-            cUnit->regLocation[sReg].fpLocation = kLocPhysReg;
-            cUnit->regLocation[sReg].fpLowReg = res;
-            cUnit->regLocation[sReg].home = true;
+            cUnit->promotionMap[sReg].fpLocation = kLocPhysReg;
+            cUnit->promotionMap[sReg].fpReg = res;
             break;
         }
     }
@@ -252,9 +254,11 @@
 STATIC int allocPreservedDouble(CompilationUnit* cUnit, int sReg)
 {
     int res = -1; // Assume failure
-    if (cUnit->regLocation[sReg+1].fpLocation == kLocPhysReg) {
+    //  Should be promoting based on initial sReg set
+    DCHECK_EQ(sReg, oatS2VReg(cUnit, sReg));
+    if (cUnit->promotionMap[sReg+1].fpLocation == kLocPhysReg) {
         // Upper reg is already allocated.  Can we fit?
-        int highReg = cUnit->regLocation[sReg+1].fpLowReg;
+        int highReg = cUnit->promotionMap[sReg+1].fpReg;
         if ((highReg & 1) == 0) {
             // High reg is even - fail.
             return res;
@@ -289,12 +293,10 @@
         }
     }
     if (res != -1) {
-        cUnit->regLocation[sReg].fpLocation = kLocPhysReg;
-        cUnit->regLocation[sReg].fpLowReg = res;
-        cUnit->regLocation[sReg].home = true;
-        cUnit->regLocation[sReg+1].fpLocation = kLocPhysReg;
-        cUnit->regLocation[sReg+1].fpLowReg = res + 1;
-        cUnit->regLocation[sReg+1].home = true;
+        cUnit->promotionMap[sReg].fpLocation = kLocPhysReg;
+        cUnit->promotionMap[sReg].fpReg = res;
+        cUnit->promotionMap[sReg+1].fpLocation = kLocPhysReg;
+        cUnit->promotionMap[sReg+1].fpReg = res + 1;
     }
     return res;
 }
@@ -312,7 +314,6 @@
     int res = -1;
     if (doubleStart) {
         res = allocPreservedDouble(cUnit, sReg);
-    } else {
     }
     if (res == -1) {
         res = allocPreservedSingle(cUnit, sReg, false /* try odd # */);