Stop saying "typedef struct" and "typedef enum".
Seeing new instances of this C-ism go in makes me a sad panda.
Change-Id: Ie3dd414b8b5e57a4164e88eb2d8559545569628d
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 32bb1f8..31449e0 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -138,7 +138,7 @@
INVALID_SREG}
#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 4,
kRegLR = -1,
@@ -151,7 +151,7 @@
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -175,7 +175,7 @@
* Annotate special-purpose core registers:
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r0 = 0,
rAX = r0,
r1 = 1,
@@ -216,7 +216,7 @@
fr13 = 13 + FP_REG_OFFSET,
fr14 = 14 + FP_REG_OFFSET,
fr15 = 15 + FP_REG_OFFSET,
-} NativeRegisterPool;
+};
/*
* Target-independent aliases
@@ -235,7 +235,7 @@
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum X86OpCode {
+enum X86OpCode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -285,25 +285,25 @@
BinaryOpCode(kOpMov),
#undef BinaryOpCode
kX86Last
-} X86OpCode;
+};
/* Instruction assembly fieldLoc kind */
-typedef enum X86EncodingKind {
+enum X86EncodingKind {
kData, // Special case for raw data
kRegImm, kMemImm, kArrayImm, // RI, MI, AI instruction kinds
kRegReg, kRegMem, kRegArray, // RR, RM, RA instruction kinds
kMemReg, kArrayReg, // MR and AR instruction kinds
kUnimplemented // Encoding used when an instruction isn't yet implemented.
-} X86EncodingKind;
+};
/* A form of instruction with an opcode byte and a secondary opcode within the modrm byte */
-typedef struct OpcodeModRMOpcode {
+struct OpcodeModRMOpcode {
uint8_t opcode; // 1 byte opcode
uint8_t modrm_opcode; // 3 bit opcode that gets encoded in the register bits of the modrm byte
-} OpcodeModRMOpcode;
+};
/* Struct used to define the EncodingMap positions for each X86 opcode */
-typedef struct X86EncodingMap {
+struct X86EncodingMap {
X86OpCode opcode; // e.g. kOpAddRI
X86EncodingKind kind; // Used to discriminate in the union below
int flags;
@@ -328,7 +328,7 @@
} skeleton;
const char *name;
const char* fmt;
-} X86EncodingMap;
+};
extern X86EncodingMap EncodingMap[kX86Last];
@@ -337,7 +337,7 @@
#define kST 0
/* Bit flags describing the behavior of each native opcode */
-typedef enum X86OpFeatureFlags {
+enum X86OpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -363,7 +363,7 @@
kMemStore,
kPCRelFixup,
// FIXME: add NEEDS_FIXUP to instruction attributes
-} X86OpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -412,9 +412,9 @@
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum X86TargetOptHints {
+enum X86TargetOptHints {
kMaxHoistDistance,
-} X86TargetOptHints;
+};
#define IS_SIMM8(v) ((-128 <= (v)) && ((v) <= 127))