Change assembler to use byte instruction lengths
Change the Arm & Mips instruction templaces to record instruction
size in bytes rather than half-words. Also includes a few Mips
changes to get us in compilable state.
Change-Id: I5a4f6cbd0cb0569805d9dfbd341c244152e59ac7
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 71220c0..2613f2c 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -41,8 +41,6 @@
void genBarrier(CompilationUnit *cUnit);
LIR* genCompareBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
int src2);
-LIR* opCompareBranch(CompilationUnit* cUnit, MipsOpCode opc, int src1,
- int src2);
void storePair(CompilationUnit *cUnit, int base, int lowReg,
int highReg);
void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
@@ -789,68 +787,16 @@
return storeBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
}
+void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
+{
+ storeWordDisp(cUnit, base, LOWORD_OFFSET, lowReg);
+ storeWordDisp(cUnit, base, HIWORD_OFFSET, highReg);
+}
+
void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
{
loadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
loadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
}
-LIR *genRegImmCheck(CompilationUnit *cUnit,
- MipsConditionCode cond, int reg,
- int checkValue, int dOffset,
- LIR *pcrLabel)
-{
- LIR *branch = NULL;
-
- if (checkValue == 0) {
- MipsOpCode opc = kMipsNop;
- if (cond == kMipsCondEq) {
- opc = kMipsBeqz;
- } else if (cond == kMipsCondNe) {
- opc = kMipsBnez;
- } else if (cond == kMipsCondLt || cond == kMipsCondMi) {
- opc = kMipsBltz;
- } else if (cond == kMipsCondLe) {
- opc = kMipsBlez;
- } else if (cond == kMipsCondGt) {
- opc = kMipsBgtz;
- } else if (cond == kMipsCondGe) {
- opc = kMipsBgez;
- } else {
- LOG(FATAL) << "Bad case in genRegImmCheck";
- }
- branch = opCompareBranch(cUnit, opc, reg, -1);
- } else if (IS_SIMM16(checkValue)) {
- if (cond == kMipsCondLt) {
- int tReg = oatAllocTemp(cUnit);
- newLIR3(cUnit, kMipsSlti, tReg, reg, checkValue);
- branch = opCompareBranch(cUnit, kMipsBne, tReg, r_ZERO);
- oatFreeTemp(cUnit, tReg);
- } else {
- LOG(FATAL) << "Bad case in genRegImmCheck";
- }
- } else {
- LOG(FATAL) << "Bad case in genRegImmCheck";
- }
-
- UNIMPLEMENTED(FATAL) << "Needs art conversion";
- return NULL;
-#if 0
- if (cUnit->jitMode == kJitMethod) {
- BasicBlock *bb = cUnit->curBlock;
- if (bb->taken) {
- LIR *exceptionLabel = (LIR *) cUnit->blockLabelList;
- exceptionLabel += bb->taken->id;
- branch->target = (LIR *) exceptionLabel;
- return exceptionLabel;
- } else {
- LOG(FATAL) << "Catch blocks not handled yet";
- return NULL;
- }
- } else {
- return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
- }
-#endif
-}
-
} // namespace art
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 0b2b15a..942dbc5 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -184,6 +184,27 @@
#endif
}
+void genNegFloat(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+{
+ RegLocation rlResult;
+ rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
+ rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ opRegRegImm(cUnit, kOpAdd, rlResult.lowReg,
+ rlSrc.lowReg, 0x80000000);
+ storeValue(cUnit, rlDest, rlResult);
+}
+
+void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
+{
+ RegLocation rlResult;
+ rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
+ rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
+ opRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg,
+ 0x80000000);
+ genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
+ storeValueWide(cUnit, rlDest, rlResult);
+}
+
/*
* TODO: implement fast path to short-circuit thin-lock case
*/