ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.
Also clean up the usage of set_cc flag. Define a SetCc
enumeration that specifies whether to set or keep condition
codes or whether we don't care and a 16-bit instruction
should be selected if one exists.
This reduces the size of Nexus 5 boot.oat by 44KiB (when
compiled with Optimizing which is not the default yet).
Change-Id: I047072dc197ea678bf2019c01bcb28943fa9b604
diff --git a/compiler/utils/assembler_thumb_test_expected.cc.inc b/compiler/utils/assembler_thumb_test_expected.cc.inc
index 280ed77..82ad642 100644
--- a/compiler/utils/assembler_thumb_test_expected.cc.inc
+++ b/compiler/utils/assembler_thumb_test_expected.cc.inc
@@ -1,8 +1,9 @@
const char* SimpleMovResults[] = {
" 0: 0008 movs r0, r1\n",
- " 2: 46c8 mov r8, r9\n",
- " 4: 2001 movs r0, #1\n",
- " 6: f04f 0809 mov.w r8, #9\n",
+ " 2: 4608 mov r0, r1\n",
+ " 4: 46c8 mov r8, r9\n",
+ " 6: 2001 movs r0, #1\n",
+ " 8: f04f 0809 mov.w r8, #9\n",
nullptr
};
const char* SimpleMov32Results[] = {
@@ -11,39 +12,120 @@
nullptr
};
const char* SimpleMovAddResults[] = {
- " 0: 0008 movs r0, r1\n",
+ " 0: 4608 mov r0, r1\n",
" 2: 1888 adds r0, r1, r2\n",
" 4: 1c08 adds r0, r1, #0\n",
nullptr
};
const char* DataProcessingRegisterResults[] = {
- " 0: 0008 movs r0, r1\n",
- " 2: 43c8 mvns r0, r1\n",
- " 4: 1888 adds r0, r1, r2\n",
- " 6: 1a88 subs r0, r1, r2\n",
- " 8: ea01 0002 and.w r0, r1, r2\n",
- " c: ea41 0002 orr.w r0, r1, r2\n",
- " 10: ea81 0002 eor.w r0, r1, r2\n",
- " 14: ea21 0002 bic.w r0, r1, r2\n",
- " 18: eb41 0002 adc.w r0, r1, r2\n",
- " 1c: eb61 0002 sbc.w r0, r1, r2\n",
- " 20: ebc1 0002 rsb r0, r1, r2\n",
- " 24: 1c08 adds r0, r1, #0\n",
- " 26: 1e08 subs r0, r1, #0\n",
- " 28: 4008 ands r0, r1\n",
- " 2a: 4308 orrs r0, r1\n",
- " 2c: 4048 eors r0, r1\n",
- " 2e: 4388 bics r0, r1\n",
- " 30: 4148 adcs r0, r1\n",
- " 32: 4188 sbcs r0, r1\n",
- " 34: 4248 negs r0, r1\n",
- " 36: 4208 tst r0, r1\n",
- " 38: ea90 0f01 teq r0, r1\n",
- " 3c: 4288 cmp r0, r1\n",
- " 3e: 42c8 cmn r0, r1\n",
- " 40: 0008 movs r0, r1\n",
- " 42: 43c8 mvns r0, r1\n",
- " 44: eb01 0c00 add.w ip, r1, r0\n",
+ " 0: ea6f 0001 mvn.w r0, r1\n",
+ " 4: eb01 0002 add.w r0, r1, r2\n",
+ " 8: eba1 0002 sub.w r0, r1, r2\n",
+ " c: ea01 0002 and.w r0, r1, r2\n",
+ " 10: ea41 0002 orr.w r0, r1, r2\n",
+ " 14: ea81 0002 eor.w r0, r1, r2\n",
+ " 18: ea21 0002 bic.w r0, r1, r2\n",
+ " 1c: eb41 0002 adc.w r0, r1, r2\n",
+ " 20: eb61 0002 sbc.w r0, r1, r2\n",
+ " 24: ebc1 0002 rsb r0, r1, r2\n",
+ " 28: ea90 0f01 teq r0, r1\n",
+ " 2c: 0008 movs r0, r1\n",
+ " 2e: 4608 mov r0, r1\n",
+ " 30: 43c8 mvns r0, r1\n",
+ " 32: 4408 add r0, r1\n",
+ " 34: 1888 adds r0, r1, r2\n",
+ " 36: 1a88 subs r0, r1, r2\n",
+ " 38: 4148 adcs r0, r1\n",
+ " 3a: 4188 sbcs r0, r1\n",
+ " 3c: 4008 ands r0, r1\n",
+ " 3e: 4308 orrs r0, r1\n",
+ " 40: 4048 eors r0, r1\n",
+ " 42: 4388 bics r0, r1\n",
+ " 44: 4208 tst r0, r1\n",
+ " 46: 4288 cmp r0, r1\n",
+ " 48: 42c8 cmn r0, r1\n",
+ " 4a: 4641 mov r1, r8\n",
+ " 4c: 4681 mov r9, r0\n",
+ " 4e: 46c8 mov r8, r9\n",
+ " 50: 4441 add r1, r8\n",
+ " 52: 4481 add r9, r0\n",
+ " 54: 44c8 add r8, r9\n",
+ " 56: 4548 cmp r0, r9\n",
+ " 58: 4588 cmp r8, r1\n",
+ " 5a: 45c1 cmp r9, r8\n",
+ " 5c: 4248 negs r0, r1\n",
+ " 5e: 4240 negs r0, r0\n",
+ " 60: ea5f 0008 movs.w r0, r8\n",
+ " 64: ea7f 0008 mvns.w r0, r8\n",
+ " 68: eb01 0008 add.w r0, r1, r8\n",
+ " 6c: eb11 0008 adds.w r0, r1, r8\n",
+ " 70: ebb1 0008 subs.w r0, r1, r8\n",
+ " 74: eb50 0008 adcs.w r0, r0, r8\n",
+ " 78: eb70 0008 sbcs.w r0, r0, r8\n",
+ " 7c: ea10 0008 ands.w r0, r0, r8\n",
+ " 80: ea50 0008 orrs.w r0, r0, r8\n",
+ " 84: ea90 0008 eors.w r0, r0, r8\n",
+ " 88: ea30 0008 bics.w r0, r0, r8\n",
+ " 8c: ea10 0f08 tst.w r0, r8\n",
+ " 90: eb10 0f08 cmn.w r0, r8\n",
+ " 94: f1d8 0000 rsbs r0, r8, #0\n",
+ " 98: f1d8 0800 rsbs r8, r8, #0\n",
+ " 9c: bf08 it eq\n",
+ " 9e: ea7f 0001 mvnseq.w r0, r1\n",
+ " a2: bf08 it eq\n",
+ " a4: eb11 0002 addseq.w r0, r1, r2\n",
+ " a8: bf08 it eq\n",
+ " aa: ebb1 0002 subseq.w r0, r1, r2\n",
+ " ae: bf08 it eq\n",
+ " b0: eb50 0001 adcseq.w r0, r0, r1\n",
+ " b4: bf08 it eq\n",
+ " b6: eb70 0001 sbcseq.w r0, r0, r1\n",
+ " ba: bf08 it eq\n",
+ " bc: ea10 0001 andseq.w r0, r0, r1\n",
+ " c0: bf08 it eq\n",
+ " c2: ea50 0001 orrseq.w r0, r0, r1\n",
+ " c6: bf08 it eq\n",
+ " c8: ea90 0001 eorseq.w r0, r0, r1\n",
+ " cc: bf08 it eq\n",
+ " ce: ea30 0001 bicseq.w r0, r0, r1\n",
+ " d2: bf08 it eq\n",
+ " d4: 43c8 mvneq r0, r1\n",
+ " d6: bf08 it eq\n",
+ " d8: 1888 addeq r0, r1, r2\n",
+ " da: bf08 it eq\n",
+ " dc: 1a88 subeq r0, r1, r2\n",
+ " de: bf08 it eq\n",
+ " e0: 4148 adceq r0, r1\n",
+ " e2: bf08 it eq\n",
+ " e4: 4188 sbceq r0, r1\n",
+ " e6: bf08 it eq\n",
+ " e8: 4008 andeq r0, r1\n",
+ " ea: bf08 it eq\n",
+ " ec: 4308 orreq r0, r1\n",
+ " ee: bf08 it eq\n",
+ " f0: 4048 eoreq r0, r1\n",
+ " f2: bf08 it eq\n",
+ " f4: 4388 biceq r0, r1\n",
+ " f6: 4608 mov r0, r1\n",
+ " f8: 43c8 mvns r0, r1\n",
+ " fa: 4408 add r0, r1\n",
+ " fc: 1888 adds r0, r1, r2\n",
+ " fe: 1a88 subs r0, r1, r2\n",
+ " 100: 4148 adcs r0, r1\n",
+ " 102: 4188 sbcs r0, r1\n",
+ " 104: 4008 ands r0, r1\n",
+ " 106: 4308 orrs r0, r1\n",
+ " 108: 4048 eors r0, r1\n",
+ " 10a: 4388 bics r0, r1\n",
+ " 10c: 4641 mov r1, r8\n",
+ " 10e: 4681 mov r9, r0\n",
+ " 110: 46c8 mov r8, r9\n",
+ " 112: 4441 add r1, r8\n",
+ " 114: 4481 add r9, r0\n",
+ " 116: 44c8 add r8, r9\n",
+ " 118: 4248 negs r0, r1\n",
+ " 11a: 4240 negs r0, r0\n",
+ " 11c: eb01 0c00 add.w ip, r1, r0\n",
nullptr
};
const char* DataProcessingImmediateResults[] = {
@@ -66,6 +148,8 @@
" 3a: 1f48 subs r0, r1, #5\n",
" 3c: 2055 movs r0, #85 ; 0x55\n",
" 3e: f07f 0055 mvns.w r0, #85 ; 0x55\n",
+ " 42: 1d48 adds r0, r1, #5\n",
+ " 44: 1f48 subs r0, r1, #5\n",
nullptr
};
const char* DataProcessingModifiedImmediateResults[] = {
@@ -100,13 +184,18 @@
" 0: 0123 lsls r3, r4, #4\n",
" 2: 0963 lsrs r3, r4, #5\n",
" 4: 11a3 asrs r3, r4, #6\n",
- " 6: ea4f 13f4 mov.w r3, r4, ror #7\n",
- " a: 41e3 rors r3, r4\n",
- " c: ea4f 1804 mov.w r8, r4, lsl #4\n",
- " 10: ea4f 1854 mov.w r8, r4, lsr #5\n",
- " 14: ea4f 18a4 mov.w r8, r4, asr #6\n",
- " 18: ea4f 18f4 mov.w r8, r4, ror #7\n",
- " 1c: ea4f 0834 mov.w r8, r4, rrx\n",
+ " 6: ea5f 13f4 movs.w r3, r4, ror #7\n",
+ " a: ea5f 0334 movs.w r3, r4, rrx\n",
+ " e: ea4f 1304 mov.w r3, r4, lsl #4\n",
+ " 12: ea4f 1354 mov.w r3, r4, lsr #5\n",
+ " 16: ea4f 13a4 mov.w r3, r4, asr #6\n",
+ " 1a: ea4f 13f4 mov.w r3, r4, ror #7\n",
+ " 1e: ea4f 0334 mov.w r3, r4, rrx\n",
+ " 22: ea5f 1804 movs.w r8, r4, lsl #4\n",
+ " 26: ea5f 1854 movs.w r8, r4, lsr #5\n",
+ " 2a: ea5f 18a4 movs.w r8, r4, asr #6\n",
+ " 2e: ea5f 18f4 movs.w r8, r4, ror #7\n",
+ " 32: ea5f 0834 movs.w r8, r4, rrx\n",
nullptr
};
const char* BasicLoadResults[] = {
@@ -1511,7 +1600,7 @@
" 7fc: 23fa movs r3, #250 ; 0xfa\n",
" 7fe: 23fc movs r3, #252 ; 0xfc\n",
" 800: 23fe movs r3, #254 ; 0xfe\n",
- " 802: 0011 movs r1, r2\n",
+ " 802: 4611 mov r1, r2\n",
nullptr
};
const char* Branch32Results[] = {
@@ -2541,7 +2630,7 @@
" 800: 23fc movs r3, #252 ; 0xfc\n",
" 802: 23fe movs r3, #254 ; 0xfe\n",
" 804: 2300 movs r3, #0\n",
- " 806: 0011 movs r1, r2\n",
+ " 806: 4611 mov r1, r2\n",
nullptr
};
const char* CompareAndBranchMaxResults[] = {
@@ -2610,7 +2699,7 @@
" 7c: 237a movs r3, #122 ; 0x7a\n",
" 7e: 237c movs r3, #124 ; 0x7c\n",
" 80: 237e movs r3, #126 ; 0x7e\n",
- " 82: 0011 movs r1, r2\n",
+ " 82: 4611 mov r1, r2\n",
nullptr
};
const char* CompareAndBranchRelocation16Results[] = {
@@ -2681,7 +2770,7 @@
" 80: 237c movs r3, #124 ; 0x7c\n",
" 82: 237e movs r3, #126 ; 0x7e\n",
" 84: 2380 movs r3, #128 ; 0x80\n",
- " 86: 0011 movs r1, r2\n",
+ " 86: 4611 mov r1, r2\n",
nullptr
};
const char* CompareAndBranchRelocation32Results[] = {
@@ -3712,7 +3801,7 @@
" 802: 23fc movs r3, #252 ; 0xfc\n",
" 804: 23fe movs r3, #254 ; 0xfe\n",
" 806: 2300 movs r3, #0\n",
- " 808: 0011 movs r1, r2\n",
+ " 808: 4611 mov r1, r2\n",
nullptr
};
const char* MixedBranch32Results[] = {
@@ -4743,7 +4832,7 @@
" 802: 23fe movs r3, #254 ; 0xfe\n",
" 804: 2300 movs r3, #0\n",
" 806: f7ff bbfd b.w 4 <MixedBranch32+0x4>\n",
- " 80a: 0011 movs r1, r2\n",
+ " 80a: 4611 mov r1, r2\n",
nullptr
};
const char* ShiftsResults[] = {
@@ -4753,28 +4842,46 @@
" 6: 4088 lsls r0, r1\n",
" 8: 40c8 lsrs r0, r1\n",
" a: 4108 asrs r0, r1\n",
- " c: ea4f 1841 mov.w r8, r1, lsl #5\n",
- " 10: ea4f 1058 mov.w r0, r8, lsr #5\n",
- " 14: ea4f 1861 mov.w r8, r1, asr #5\n",
- " 18: ea4f 1078 mov.w r0, r8, ror #5\n",
- " 1c: fa01 f002 lsl.w r0, r1, r2\n",
- " 20: fa21 f002 lsr.w r0, r1, r2\n",
- " 24: fa41 f002 asr.w r0, r1, r2\n",
- " 28: fa61 f002 ror.w r0, r1, r2\n",
- " 2c: fa01 f802 lsl.w r8, r1, r2\n",
- " 30: fa28 f002 lsr.w r0, r8, r2\n",
- " 34: fa41 f008 asr.w r0, r1, r8\n",
- " 38: ea5f 1841 movs.w r8, r1, lsl #5\n",
- " 3c: ea5f 1058 movs.w r0, r8, lsr #5\n",
- " 40: ea5f 1861 movs.w r8, r1, asr #5\n",
- " 44: ea5f 1078 movs.w r0, r8, ror #5\n",
- " 48: fa11 f002 lsls.w r0, r1, r2\n",
- " 4c: fa31 f002 lsrs.w r0, r1, r2\n",
- " 50: fa51 f002 asrs.w r0, r1, r2\n",
- " 54: fa71 f002 rors.w r0, r1, r2\n",
- " 58: fa11 f802 lsls.w r8, r1, r2\n",
- " 5c: fa38 f002 lsrs.w r0, r8, r2\n",
- " 60: fa51 f008 asrs.w r0, r1, r8\n",
+ " c: 41c8 rors r0, r1\n",
+ " e: 0148 lsls r0, r1, #5\n",
+ " 10: 0948 lsrs r0, r1, #5\n",
+ " 12: 1148 asrs r0, r1, #5\n",
+ " 14: 4088 lsls r0, r1\n",
+ " 16: 40c8 lsrs r0, r1\n",
+ " 18: 4108 asrs r0, r1\n",
+ " 1a: 41c8 rors r0, r1\n",
+ " 1c: ea4f 1041 mov.w r0, r1, lsl #5\n",
+ " 20: ea4f 1051 mov.w r0, r1, lsr #5\n",
+ " 24: ea4f 1061 mov.w r0, r1, asr #5\n",
+ " 28: fa00 f001 lsl.w r0, r0, r1\n",
+ " 2c: fa20 f001 lsr.w r0, r0, r1\n",
+ " 30: fa40 f001 asr.w r0, r0, r1\n",
+ " 34: fa60 f001 ror.w r0, r0, r1\n",
+ " 38: ea4f 1071 mov.w r0, r1, ror #5\n",
+ " 3c: ea5f 1071 movs.w r0, r1, ror #5\n",
+ " 40: ea4f 1071 mov.w r0, r1, ror #5\n",
+ " 44: ea4f 1841 mov.w r8, r1, lsl #5\n",
+ " 48: ea4f 1058 mov.w r0, r8, lsr #5\n",
+ " 4c: ea4f 1861 mov.w r8, r1, asr #5\n",
+ " 50: ea4f 1078 mov.w r0, r8, ror #5\n",
+ " 54: fa01 f002 lsl.w r0, r1, r2\n",
+ " 58: fa21 f002 lsr.w r0, r1, r2\n",
+ " 5c: fa41 f002 asr.w r0, r1, r2\n",
+ " 60: fa61 f002 ror.w r0, r1, r2\n",
+ " 64: fa01 f802 lsl.w r8, r1, r2\n",
+ " 68: fa28 f002 lsr.w r0, r8, r2\n",
+ " 6c: fa41 f008 asr.w r0, r1, r8\n",
+ " 70: ea5f 1841 movs.w r8, r1, lsl #5\n",
+ " 74: ea5f 1058 movs.w r0, r8, lsr #5\n",
+ " 78: ea5f 1861 movs.w r8, r1, asr #5\n",
+ " 7c: ea5f 1078 movs.w r0, r8, ror #5\n",
+ " 80: fa11 f002 lsls.w r0, r1, r2\n",
+ " 84: fa31 f002 lsrs.w r0, r1, r2\n",
+ " 88: fa51 f002 asrs.w r0, r1, r2\n",
+ " 8c: fa71 f002 rors.w r0, r1, r2\n",
+ " 90: fa11 f802 lsls.w r8, r1, r2\n",
+ " 94: fa38 f002 lsrs.w r0, r8, r2\n",
+ " 98: fa51 f008 asrs.w r0, r1, r8\n",
nullptr
};
const char* LoadStoreRegOffsetResults[] = {