| // Copyright 2011 Google Inc. All Rights Reserved. |
| |
| #include "assembler.h" |
| #include "casts.h" |
| #include "globals.h" |
| #include "memory_region.h" |
| #include "offsets.h" |
| #include "thread.h" |
| |
| namespace art { |
| |
| class DirectCallRelocation : public AssemblerFixup { |
| public: |
| void Process(const MemoryRegion& region, int position) { |
| // Direct calls are relative to the following instruction on x86. |
| int32_t pointer = region.Load<int32_t>(position); |
| int32_t start = reinterpret_cast<int32_t>(region.start()); |
| int32_t delta = start + position + sizeof(int32_t); |
| region.Store<int32_t>(position, pointer - delta); |
| } |
| }; |
| |
| static const char* kRegisterNames[] = { |
| "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", |
| }; |
| std::ostream& operator<<(std::ostream& os, const Register& rhs) { |
| if (rhs >= EAX && rhs <= EDI) { |
| os << kRegisterNames[rhs]; |
| } else { |
| os << "Register[" << static_cast<int>(rhs) << "]"; |
| } |
| return os; |
| } |
| |
| std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { |
| return os << "XMM" << static_cast<int>(reg); |
| } |
| |
| std::ostream& operator<<(std::ostream& os, const X87Register& reg) { |
| return os << "ST" << static_cast<int>(reg); |
| } |
| |
| void Assembler::InitializeMemoryWithBreakpoints(byte* data, size_t length) { |
| memset(reinterpret_cast<void*>(data), Instr::kBreakPointInstruction, length); |
| } |
| |
| |
| void Assembler::call(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitRegisterOperand(2, reg); |
| } |
| |
| |
| void Assembler::call(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitOperand(2, address); |
| } |
| |
| |
| void Assembler::call(Label* label) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xE8); |
| static const int kSize = 5; |
| EmitLabel(label, kSize); |
| } |
| |
| |
| void Assembler::pushl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x50 + reg); |
| } |
| |
| |
| void Assembler::pushl(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitOperand(6, address); |
| } |
| |
| |
| void Assembler::pushl(const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x68); |
| EmitImmediate(imm); |
| } |
| |
| |
| void Assembler::popl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x58 + reg); |
| } |
| |
| |
| void Assembler::popl(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x8F); |
| EmitOperand(0, address); |
| } |
| |
| |
| void Assembler::movl(Register dst, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xB8 + dst); |
| EmitImmediate(imm); |
| } |
| |
| |
| void Assembler::movl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x89); |
| EmitRegisterOperand(src, dst); |
| } |
| |
| |
| void Assembler::movl(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x8B); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movl(const Address& dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x89); |
| EmitOperand(src, dst); |
| } |
| |
| |
| void Assembler::movl(const Address& dst, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC7); |
| EmitOperand(0, dst); |
| EmitImmediate(imm); |
| } |
| |
| |
| void Assembler::movzxb(Register dst, ByteRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xB6); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::movzxb(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xB6); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movsxb(Register dst, ByteRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xBE); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::movsxb(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xBE); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movb(Register dst, const Address& src) { |
| LOG(FATAL) << "Use movzxb or movsxb instead."; |
| } |
| |
| |
| void Assembler::movb(const Address& dst, ByteRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x88); |
| EmitOperand(src, dst); |
| } |
| |
| |
| void Assembler::movb(const Address& dst, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC6); |
| EmitOperand(EAX, dst); |
| CHECK(imm.is_int8()); |
| EmitUint8(imm.value() & 0xFF); |
| } |
| |
| |
| void Assembler::movzxw(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xB7); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::movzxw(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xB7); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movsxw(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xBF); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::movsxw(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xBF); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movw(Register dst, const Address& src) { |
| LOG(FATAL) << "Use movzxw or movsxw instead."; |
| } |
| |
| |
| void Assembler::movw(const Address& dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitOperandSizeOverride(); |
| EmitUint8(0x89); |
| EmitOperand(src, dst); |
| } |
| |
| |
| void Assembler::leal(Register dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x8D); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::cmovl(Condition condition, Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0x40 + condition); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::setb(Condition condition, Register dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0x90 + condition); |
| EmitOperand(0, Operand(dst)); |
| } |
| |
| |
| void Assembler::movss(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x10); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movss(const Address& dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x11); |
| EmitOperand(src, dst); |
| } |
| |
| |
| void Assembler::movss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x11); |
| EmitXmmRegisterOperand(src, dst); |
| } |
| |
| |
| void Assembler::movd(XmmRegister dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x6E); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::movd(Register dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x7E); |
| EmitOperand(src, Operand(dst)); |
| } |
| |
| |
| void Assembler::addss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x58); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::addss(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x58); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::subss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x5C); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::subss(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x5C); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::mulss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x59); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::mulss(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x59); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::divss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x5E); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::divss(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x5E); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::flds(const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitOperand(0, src); |
| } |
| |
| |
| void Assembler::fstps(const Address& dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitOperand(3, dst); |
| } |
| |
| |
| void Assembler::movsd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x10); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::movsd(const Address& dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x11); |
| EmitOperand(src, dst); |
| } |
| |
| |
| void Assembler::movsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x11); |
| EmitXmmRegisterOperand(src, dst); |
| } |
| |
| |
| void Assembler::addsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x58); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::addsd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x58); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::subsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x5C); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::subsd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x5C); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::mulsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x59); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::mulsd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x59); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::divsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x5E); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::divsd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x5E); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvtsi2ss(XmmRegister dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x2A); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::cvtsi2sd(XmmRegister dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x2A); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::cvtss2si(Register dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x2D); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x5A); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvtsd2si(Register dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x2D); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvttss2si(Register dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x2C); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvttsd2si(Register dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x2C); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x5A); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0xE6); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::comiss(XmmRegister a, XmmRegister b) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0x2F); |
| EmitXmmRegisterOperand(a, b); |
| } |
| |
| |
| void Assembler::comisd(XmmRegister a, XmmRegister b) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x2F); |
| EmitXmmRegisterOperand(a, b); |
| } |
| |
| |
| void Assembler::sqrtsd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF2); |
| EmitUint8(0x0F); |
| EmitUint8(0x51); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::sqrtss(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF3); |
| EmitUint8(0x0F); |
| EmitUint8(0x51); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::xorpd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x57); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::xorpd(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x57); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::xorps(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0x57); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::xorps(XmmRegister dst, XmmRegister src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0x57); |
| EmitXmmRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::andpd(XmmRegister dst, const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x66); |
| EmitUint8(0x0F); |
| EmitUint8(0x54); |
| EmitOperand(dst, src); |
| } |
| |
| |
| void Assembler::fldl(const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDD); |
| EmitOperand(0, src); |
| } |
| |
| |
| void Assembler::fstpl(const Address& dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDD); |
| EmitOperand(3, dst); |
| } |
| |
| |
| void Assembler::fnstcw(const Address& dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitOperand(7, dst); |
| } |
| |
| |
| void Assembler::fldcw(const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitOperand(5, src); |
| } |
| |
| |
| void Assembler::fistpl(const Address& dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDF); |
| EmitOperand(7, dst); |
| } |
| |
| |
| void Assembler::fistps(const Address& dst) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDB); |
| EmitOperand(3, dst); |
| } |
| |
| |
| void Assembler::fildl(const Address& src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDF); |
| EmitOperand(5, src); |
| } |
| |
| |
| void Assembler::fincstp() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitUint8(0xF7); |
| } |
| |
| |
| void Assembler::ffree(const Immediate& index) { |
| CHECK_LT(index.value(), 7); |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xDD); |
| EmitUint8(0xC0 + index.value()); |
| } |
| |
| |
| void Assembler::fsin() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitUint8(0xFE); |
| } |
| |
| |
| void Assembler::fcos() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitUint8(0xFF); |
| } |
| |
| |
| void Assembler::fptan() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xD9); |
| EmitUint8(0xF2); |
| } |
| |
| |
| void Assembler::xchgl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x87); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::cmpl(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(7, Operand(reg), imm); |
| } |
| |
| |
| void Assembler::cmpl(Register reg0, Register reg1) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x3B); |
| EmitOperand(reg0, Operand(reg1)); |
| } |
| |
| |
| void Assembler::cmpl(Register reg, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x3B); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::addl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x03); |
| EmitRegisterOperand(dst, src); |
| } |
| |
| |
| void Assembler::addl(Register reg, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x03); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::cmpl(const Address& address, Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x39); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::cmpl(const Address& address, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(7, address, imm); |
| } |
| |
| |
| void Assembler::testl(Register reg1, Register reg2) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x85); |
| EmitRegisterOperand(reg1, reg2); |
| } |
| |
| |
| void Assembler::testl(Register reg, const Immediate& immediate) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| // For registers that have a byte variant (EAX, EBX, ECX, and EDX) |
| // we only test the byte register to keep the encoding short. |
| if (immediate.is_uint8() && reg < 4) { |
| // Use zero-extended 8-bit immediate. |
| if (reg == EAX) { |
| EmitUint8(0xA8); |
| } else { |
| EmitUint8(0xF6); |
| EmitUint8(0xC0 + reg); |
| } |
| EmitUint8(immediate.value() & 0xFF); |
| } else if (reg == EAX) { |
| // Use short form if the destination is EAX. |
| EmitUint8(0xA9); |
| EmitImmediate(immediate); |
| } else { |
| EmitUint8(0xF7); |
| EmitOperand(0, Operand(reg)); |
| EmitImmediate(immediate); |
| } |
| } |
| |
| |
| void Assembler::andl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x23); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::andl(Register dst, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(4, Operand(dst), imm); |
| } |
| |
| |
| void Assembler::orl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0B); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::orl(Register dst, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(1, Operand(dst), imm); |
| } |
| |
| |
| void Assembler::xorl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x33); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::addl(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(0, Operand(reg), imm); |
| } |
| |
| |
| void Assembler::addl(const Address& address, Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x01); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::addl(const Address& address, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(0, address, imm); |
| } |
| |
| |
| void Assembler::adcl(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(2, Operand(reg), imm); |
| } |
| |
| |
| void Assembler::adcl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x13); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::adcl(Register dst, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x13); |
| EmitOperand(dst, address); |
| } |
| |
| |
| void Assembler::subl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x2B); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::subl(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(5, Operand(reg), imm); |
| } |
| |
| |
| void Assembler::subl(Register reg, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x2B); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::cdq() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x99); |
| } |
| |
| |
| void Assembler::idivl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitUint8(0xF8 | reg); |
| } |
| |
| |
| void Assembler::imull(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xAF); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::imull(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x69); |
| EmitOperand(reg, Operand(reg)); |
| EmitImmediate(imm); |
| } |
| |
| |
| void Assembler::imull(Register reg, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xAF); |
| EmitOperand(reg, address); |
| } |
| |
| |
| void Assembler::imull(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitOperand(5, Operand(reg)); |
| } |
| |
| |
| void Assembler::imull(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitOperand(5, address); |
| } |
| |
| |
| void Assembler::mull(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitOperand(4, Operand(reg)); |
| } |
| |
| |
| void Assembler::mull(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitOperand(4, address); |
| } |
| |
| |
| void Assembler::sbbl(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x1B); |
| EmitOperand(dst, Operand(src)); |
| } |
| |
| |
| void Assembler::sbbl(Register reg, const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitComplex(3, Operand(reg), imm); |
| } |
| |
| |
| void Assembler::sbbl(Register dst, const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x1B); |
| EmitOperand(dst, address); |
| } |
| |
| |
| void Assembler::incl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x40 + reg); |
| } |
| |
| |
| void Assembler::incl(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitOperand(0, address); |
| } |
| |
| |
| void Assembler::decl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x48 + reg); |
| } |
| |
| |
| void Assembler::decl(const Address& address) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitOperand(1, address); |
| } |
| |
| |
| void Assembler::shll(Register reg, const Immediate& imm) { |
| EmitGenericShift(4, reg, imm); |
| } |
| |
| |
| void Assembler::shll(Register operand, Register shifter) { |
| EmitGenericShift(4, operand, shifter); |
| } |
| |
| |
| void Assembler::shrl(Register reg, const Immediate& imm) { |
| EmitGenericShift(5, reg, imm); |
| } |
| |
| |
| void Assembler::shrl(Register operand, Register shifter) { |
| EmitGenericShift(5, operand, shifter); |
| } |
| |
| |
| void Assembler::sarl(Register reg, const Immediate& imm) { |
| EmitGenericShift(7, reg, imm); |
| } |
| |
| |
| void Assembler::sarl(Register operand, Register shifter) { |
| EmitGenericShift(7, operand, shifter); |
| } |
| |
| |
| void Assembler::shld(Register dst, Register src) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xA5); |
| EmitRegisterOperand(src, dst); |
| } |
| |
| |
| void Assembler::negl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitOperand(3, Operand(reg)); |
| } |
| |
| |
| void Assembler::notl(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF7); |
| EmitUint8(0xD0 | reg); |
| } |
| |
| |
| void Assembler::enter(const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC8); |
| CHECK(imm.is_uint16()); |
| EmitUint8(imm.value() & 0xFF); |
| EmitUint8((imm.value() >> 8) & 0xFF); |
| EmitUint8(0x00); |
| } |
| |
| |
| void Assembler::leave() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC9); |
| } |
| |
| |
| void Assembler::ret() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC3); |
| } |
| |
| |
| void Assembler::ret(const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xC2); |
| CHECK(imm.is_uint16()); |
| EmitUint8(imm.value() & 0xFF); |
| EmitUint8((imm.value() >> 8) & 0xFF); |
| } |
| |
| |
| |
| void Assembler::nop() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x90); |
| } |
| |
| |
| void Assembler::int3() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xCC); |
| } |
| |
| |
| void Assembler::hlt() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF4); |
| } |
| |
| |
| void Assembler::j(Condition condition, Label* label) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| if (label->IsBound()) { |
| static const int kShortSize = 2; |
| static const int kLongSize = 6; |
| int offset = label->Position() - buffer_.Size(); |
| CHECK_LE(offset, 0); |
| if (IsInt(8, offset - kShortSize)) { |
| EmitUint8(0x70 + condition); |
| EmitUint8((offset - kShortSize) & 0xFF); |
| } else { |
| EmitUint8(0x0F); |
| EmitUint8(0x80 + condition); |
| EmitInt32(offset - kLongSize); |
| } |
| } else { |
| EmitUint8(0x0F); |
| EmitUint8(0x80 + condition); |
| EmitLabelLink(label); |
| } |
| } |
| |
| |
| void Assembler::jmp(Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xFF); |
| EmitRegisterOperand(4, reg); |
| } |
| |
| |
| void Assembler::jmp(Label* label) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| if (label->IsBound()) { |
| static const int kShortSize = 2; |
| static const int kLongSize = 5; |
| int offset = label->Position() - buffer_.Size(); |
| CHECK_LE(offset, 0); |
| if (IsInt(8, offset - kShortSize)) { |
| EmitUint8(0xEB); |
| EmitUint8((offset - kShortSize) & 0xFF); |
| } else { |
| EmitUint8(0xE9); |
| EmitInt32(offset - kLongSize); |
| } |
| } else { |
| EmitUint8(0xE9); |
| EmitLabelLink(label); |
| } |
| } |
| |
| |
| void Assembler::lock() { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0xF0); |
| } |
| |
| |
| void Assembler::cmpxchgl(const Address& address, Register reg) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x0F); |
| EmitUint8(0xB1); |
| EmitOperand(reg, address); |
| } |
| |
| void Assembler::fs() { |
| // TODO: fs is a prefix and not an instruction |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| EmitUint8(0x64); |
| } |
| |
| void Assembler::AddImmediate(Register reg, const Immediate& imm) { |
| int value = imm.value(); |
| if (value > 0) { |
| if (value == 1) { |
| incl(reg); |
| } else if (value != 0) { |
| addl(reg, imm); |
| } |
| } else if (value < 0) { |
| value = -value; |
| if (value == 1) { |
| decl(reg); |
| } else if (value != 0) { |
| subl(reg, Immediate(value)); |
| } |
| } |
| } |
| |
| |
| void Assembler::LoadDoubleConstant(XmmRegister dst, double value) { |
| // TODO: Need to have a code constants table. |
| int64_t constant = bit_cast<int64_t, double>(value); |
| pushl(Immediate(High32Bits(constant))); |
| pushl(Immediate(Low32Bits(constant))); |
| movsd(dst, Address(ESP, 0)); |
| addl(ESP, Immediate(2 * kWordSize)); |
| } |
| |
| |
| void Assembler::FloatNegate(XmmRegister f) { |
| static const struct { |
| uint32_t a; |
| uint32_t b; |
| uint32_t c; |
| uint32_t d; |
| } float_negate_constant __attribute__((aligned(16))) = |
| { 0x80000000, 0x00000000, 0x80000000, 0x00000000 }; |
| xorps(f, Address::Absolute(reinterpret_cast<uword>(&float_negate_constant))); |
| } |
| |
| |
| void Assembler::DoubleNegate(XmmRegister d) { |
| static const struct { |
| uint64_t a; |
| uint64_t b; |
| } double_negate_constant __attribute__((aligned(16))) = |
| {0x8000000000000000LL, 0x8000000000000000LL}; |
| xorpd(d, Address::Absolute(reinterpret_cast<uword>(&double_negate_constant))); |
| } |
| |
| |
| void Assembler::DoubleAbs(XmmRegister reg) { |
| static const struct { |
| uint64_t a; |
| uint64_t b; |
| } double_abs_constant __attribute__((aligned(16))) = |
| {0x7FFFFFFFFFFFFFFFLL, 0x7FFFFFFFFFFFFFFFLL}; |
| andpd(reg, Address::Absolute(reinterpret_cast<uword>(&double_abs_constant))); |
| } |
| |
| |
| void Assembler::Align(int alignment, int offset) { |
| CHECK(IsPowerOfTwo(alignment)); |
| // Emit nop instruction until the real position is aligned. |
| while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) { |
| nop(); |
| } |
| } |
| |
| |
| void Assembler::Bind(Label* label) { |
| int bound = buffer_.Size(); |
| CHECK(!label->IsBound()); // Labels can only be bound once. |
| while (label->IsLinked()) { |
| int position = label->LinkPosition(); |
| int next = buffer_.Load<int32_t>(position); |
| buffer_.Store<int32_t>(position, bound - (position + 4)); |
| label->position_ = next; |
| } |
| label->BindTo(bound); |
| } |
| |
| |
| void Assembler::Stop(const char* message) { |
| // Emit the message address as immediate operand in the test rax instruction, |
| // followed by the int3 instruction. |
| // Execution can be resumed with the 'cont' command in gdb. |
| testl(EAX, Immediate(reinterpret_cast<int32_t>(message))); |
| int3(); |
| } |
| |
| |
| void Assembler::EmitOperand(int rm, const Operand& operand) { |
| CHECK_GE(rm, 0); |
| CHECK_LT(rm, 8); |
| const int length = operand.length_; |
| CHECK_GT(length, 0); |
| // Emit the ModRM byte updated with the given RM value. |
| CHECK_EQ(operand.encoding_[0] & 0x38, 0); |
| EmitUint8(operand.encoding_[0] + (rm << 3)); |
| // Emit the rest of the encoded operand. |
| for (int i = 1; i < length; i++) { |
| EmitUint8(operand.encoding_[i]); |
| } |
| } |
| |
| |
| void Assembler::EmitImmediate(const Immediate& imm) { |
| EmitInt32(imm.value()); |
| } |
| |
| |
| void Assembler::EmitComplex(int rm, |
| const Operand& operand, |
| const Immediate& immediate) { |
| CHECK_GE(rm, 0); |
| CHECK_LT(rm, 8); |
| if (immediate.is_int8()) { |
| // Use sign-extended 8-bit immediate. |
| EmitUint8(0x83); |
| EmitOperand(rm, operand); |
| EmitUint8(immediate.value() & 0xFF); |
| } else if (operand.IsRegister(EAX)) { |
| // Use short form if the destination is eax. |
| EmitUint8(0x05 + (rm << 3)); |
| EmitImmediate(immediate); |
| } else { |
| EmitUint8(0x81); |
| EmitOperand(rm, operand); |
| EmitImmediate(immediate); |
| } |
| } |
| |
| |
| void Assembler::EmitLabel(Label* label, int instruction_size) { |
| if (label->IsBound()) { |
| int offset = label->Position() - buffer_.Size(); |
| CHECK_LE(offset, 0); |
| EmitInt32(offset - instruction_size); |
| } else { |
| EmitLabelLink(label); |
| } |
| } |
| |
| |
| void Assembler::EmitLabelLink(Label* label) { |
| CHECK(!label->IsBound()); |
| int position = buffer_.Size(); |
| EmitInt32(label->position_); |
| label->LinkTo(position); |
| } |
| |
| |
| void Assembler::EmitGenericShift(int rm, |
| Register reg, |
| const Immediate& imm) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| CHECK(imm.is_int8()); |
| if (imm.value() == 1) { |
| EmitUint8(0xD1); |
| EmitOperand(rm, Operand(reg)); |
| } else { |
| EmitUint8(0xC1); |
| EmitOperand(rm, Operand(reg)); |
| EmitUint8(imm.value() & 0xFF); |
| } |
| } |
| |
| |
| void Assembler::EmitGenericShift(int rm, |
| Register operand, |
| Register shifter) { |
| AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| CHECK_EQ(shifter, ECX); |
| EmitUint8(0xD3); |
| EmitOperand(rm, Operand(operand)); |
| } |
| |
| // Emit code that will create an activation on the stack |
| void Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg) { |
| CHECK(IsAligned(frame_size, 16)); |
| // return address then method on stack |
| addl(ESP, Immediate(-frame_size + 4 /*method*/ + 4 /*return address*/)); |
| pushl(method_reg.AsCpuRegister()); |
| } |
| |
| // Emit code that will remove an activation from the stack |
| void Assembler::RemoveFrame(size_t frame_size) { |
| CHECK(IsAligned(frame_size, 16)); |
| addl(ESP, Immediate(frame_size - 4)); |
| ret(); |
| } |
| |
| void Assembler::IncreaseFrameSize(size_t adjust) { |
| CHECK(IsAligned(adjust, 16)); |
| addl(ESP, Immediate(-adjust)); |
| } |
| |
| void Assembler::DecreaseFrameSize(size_t adjust) { |
| CHECK(IsAligned(adjust, 16)); |
| addl(ESP, Immediate(adjust)); |
| } |
| |
| // Store bytes from the given register onto the stack |
| void Assembler::Store(FrameOffset offs, ManagedRegister src, size_t size) { |
| if (src.IsNoRegister()) { |
| CHECK_EQ(0u, size); |
| } else if (src.IsCpuRegister()) { |
| CHECK_EQ(4u, size); |
| movl(Address(ESP, offs), src.AsCpuRegister()); |
| } else if (src.IsX87Register()) { |
| if (size == 4) { |
| fstps(Address(ESP, offs)); |
| } else { |
| fstpl(Address(ESP, offs)); |
| } |
| } else { |
| CHECK(src.IsXmmRegister()); |
| if (size == 4) { |
| movss(Address(ESP, offs), src.AsXmmRegister()); |
| } else { |
| movsd(Address(ESP, offs), src.AsXmmRegister()); |
| } |
| } |
| } |
| |
| void Assembler::StoreRef(FrameOffset dest, ManagedRegister src) { |
| CHECK(src.IsCpuRegister()); |
| movl(Address(ESP, dest), src.AsCpuRegister()); |
| } |
| |
| void Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister src) { |
| CHECK(src.IsCpuRegister()); |
| movl(Address(ESP, dest), src.AsCpuRegister()); |
| } |
| |
| void Assembler::CopyRef(FrameOffset dest, FrameOffset src, |
| ManagedRegister scratch) { |
| CHECK(scratch.IsCpuRegister()); |
| movl(scratch.AsCpuRegister(), Address(ESP, src)); |
| movl(Address(ESP, dest), scratch.AsCpuRegister()); |
| } |
| |
| void Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, |
| ManagedRegister) { |
| movl(Address(ESP, dest), Immediate(imm)); |
| } |
| |
| void Assembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm, |
| ManagedRegister) { |
| fs(); |
| movl(Address::Absolute(dest), Immediate(imm)); |
| } |
| |
| void Assembler::Load(ManagedRegister dest, FrameOffset src, size_t size) { |
| if (dest.IsNoRegister()) { |
| CHECK_EQ(0u, size); |
| } else if (dest.IsCpuRegister()) { |
| CHECK_EQ(4u, size); |
| movl(dest.AsCpuRegister(), Address(ESP, src)); |
| } else if (dest.IsX87Register()) { |
| if (size == 4) { |
| flds(Address(ESP, src)); |
| } else { |
| fldl(Address(ESP, src)); |
| } |
| } else { |
| CHECK(dest.IsXmmRegister()); |
| if (size == 4) { |
| movss(dest.AsXmmRegister(), Address(ESP, src)); |
| } else { |
| movsd(dest.AsXmmRegister(), Address(ESP, src)); |
| } |
| } |
| } |
| |
| void Assembler::LoadRef(ManagedRegister dest, FrameOffset src) { |
| CHECK(dest.IsCpuRegister()); |
| movl(dest.AsCpuRegister(), Address(ESP, src)); |
| } |
| |
| void Assembler::LoadRef(ManagedRegister dest, ManagedRegister base, |
| MemberOffset offs) { |
| CHECK(dest.IsCpuRegister() && dest.IsCpuRegister()); |
| movl(dest.AsCpuRegister(), Address(base.AsCpuRegister(), offs)); |
| } |
| |
| void Assembler::LoadRawPtrFromThread(ManagedRegister dest, ThreadOffset offs) { |
| CHECK(dest.IsCpuRegister()); |
| fs(); |
| movl(dest.AsCpuRegister(), Address::Absolute(offs)); |
| } |
| |
| void Assembler::CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs, |
| ManagedRegister scratch) { |
| CHECK(scratch.IsCpuRegister()); |
| fs(); |
| movl(scratch.AsCpuRegister(), Address::Absolute(thr_offs)); |
| Store(fr_offs, scratch, 4); |
| } |
| |
| void Assembler::CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs, |
| ManagedRegister scratch) { |
| CHECK(scratch.IsCpuRegister()); |
| Load(scratch, fr_offs, 4); |
| fs(); |
| movl(Address::Absolute(thr_offs), scratch.AsCpuRegister()); |
| } |
| |
| void Assembler::StoreStackOffsetToThread(ThreadOffset thr_offs, |
| FrameOffset fr_offs, |
| ManagedRegister scratch) { |
| CHECK(scratch.IsCpuRegister()); |
| leal(scratch.AsCpuRegister(), Address(ESP, fr_offs)); |
| fs(); |
| movl(Address::Absolute(thr_offs), scratch.AsCpuRegister()); |
| } |
| |
| void Assembler::StoreStackPointerToThread(ThreadOffset thr_offs) { |
| fs(); |
| movl(Address::Absolute(thr_offs), ESP); |
| } |
| |
| void Assembler::Move(ManagedRegister dest, ManagedRegister src) { |
| if (!dest.Equals(src)) { |
| if (dest.IsCpuRegister() && src.IsCpuRegister()) { |
| movl(dest.AsCpuRegister(), src.AsCpuRegister()); |
| } else { |
| // TODO: x87, SSE |
| LOG(FATAL) << "Unimplemented"; |
| } |
| } |
| } |
| |
| void Assembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, |
| size_t size) { |
| if (scratch.IsCpuRegister() && size == 8) { |
| Load(scratch, src, 4); |
| Store(dest, scratch, 4); |
| Load(scratch, FrameOffset(src.Int32Value() + 4), 4); |
| Store(FrameOffset(dest.Int32Value() + 4), scratch, 4); |
| } else { |
| Load(scratch, src, size); |
| Store(dest, scratch, size); |
| } |
| } |
| |
| void Assembler::CreateStackHandle(ManagedRegister out_reg, |
| FrameOffset handle_offset, |
| ManagedRegister in_reg, bool null_allowed) { |
| CHECK(in_reg.IsCpuRegister()); |
| CHECK(out_reg.IsCpuRegister()); |
| ValidateRef(in_reg, null_allowed); |
| if (null_allowed) { |
| Label null_arg; |
| if (!out_reg.Equals(in_reg)) { |
| xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); |
| } |
| testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); |
| j(ZERO, &null_arg); |
| leal(out_reg.AsCpuRegister(), Address(ESP, handle_offset)); |
| Bind(&null_arg); |
| } else { |
| leal(out_reg.AsCpuRegister(), Address(ESP, handle_offset)); |
| } |
| } |
| |
| void Assembler::CreateStackHandle(FrameOffset out_off, |
| FrameOffset handle_offset, |
| ManagedRegister scratch, bool null_allowed) { |
| CHECK(scratch.IsCpuRegister()); |
| if (null_allowed) { |
| Label null_arg; |
| movl(scratch.AsCpuRegister(), Address(ESP, handle_offset)); |
| testl(scratch.AsCpuRegister(), scratch.AsCpuRegister()); |
| j(ZERO, &null_arg); |
| leal(scratch.AsCpuRegister(), Address(ESP, handle_offset)); |
| Bind(&null_arg); |
| } else { |
| leal(scratch.AsCpuRegister(), Address(ESP, handle_offset)); |
| } |
| Store(out_off, scratch, 4); |
| } |
| |
| // Given a stack handle, load the associated reference. |
| void Assembler::LoadReferenceFromStackHandle(ManagedRegister out_reg, |
| ManagedRegister in_reg) { |
| CHECK(out_reg.IsCpuRegister()); |
| CHECK(in_reg.IsCpuRegister()); |
| Label null_arg; |
| if (!out_reg.Equals(in_reg)) { |
| xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); |
| } |
| testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); |
| j(ZERO, &null_arg); |
| movl(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0)); |
| Bind(&null_arg); |
| } |
| |
| void Assembler::ValidateRef(ManagedRegister src, bool could_be_null) { |
| // TODO: not validating references |
| } |
| |
| void Assembler::ValidateRef(FrameOffset src, bool could_be_null) { |
| // TODO: not validating references |
| } |
| |
| void Assembler::Call(ManagedRegister base, Offset offset, |
| ManagedRegister) { |
| CHECK(base.IsCpuRegister()); |
| call(Address(base.AsCpuRegister(), offset.Int32Value())); |
| // TODO: place reference map on call |
| } |
| |
| void Assembler::Call(FrameOffset base, Offset offset, |
| ManagedRegister) { |
| LOG(FATAL) << "Unimplemented"; |
| } |
| |
| // Generate code to check if Thread::Current()->suspend_count_ is non-zero |
| // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue |
| // at the next instruction. |
| void Assembler::SuspendPoll(ManagedRegister scratch, ManagedRegister return_reg, |
| FrameOffset return_save_location, |
| size_t return_size) { |
| SuspendCountSlowPath* slow = |
| new SuspendCountSlowPath(return_reg, return_save_location, return_size); |
| buffer_.EnqueueSlowPath(slow); |
| fs(); |
| cmpl(Address::Absolute(Thread::SuspendCountOffset()), Immediate(0)); |
| j(NOT_EQUAL, slow->Entry()); |
| Bind(slow->Continuation()); |
| } |
| void SuspendCountSlowPath::Emit(Assembler *sp_asm) { |
| sp_asm->Bind(&entry_); |
| // Save return value |
| sp_asm->Store(return_save_location_, return_register_, return_size_); |
| // Pass top of stack as argument |
| sp_asm->pushl(ESP); |
| sp_asm->fs(); |
| sp_asm->call(Address::Absolute(Thread::SuspendCountEntryPointOffset())); |
| // Release argument |
| sp_asm->addl(ESP, Immediate(kPointerSize)); |
| // Reload return value |
| sp_asm->Load(return_register_, return_save_location_, return_size_); |
| sp_asm->jmp(&continuation_); |
| } |
| |
| // Generate code to check if Thread::Current()->exception_ is non-null |
| // and branch to a ExceptionSlowPath if it is. |
| void Assembler::ExceptionPoll(ManagedRegister scratch) { |
| ExceptionSlowPath* slow = new ExceptionSlowPath(); |
| buffer_.EnqueueSlowPath(slow); |
| fs(); |
| cmpl(Address::Absolute(Thread::ExceptionOffset()), Immediate(0)); |
| j(NOT_EQUAL, slow->Entry()); |
| Bind(slow->Continuation()); |
| } |
| void ExceptionSlowPath::Emit(Assembler *sp_asm) { |
| sp_asm->Bind(&entry_); |
| // NB the return value is dead |
| // Pass top of stack as argument |
| sp_asm->pushl(ESP); |
| sp_asm->fs(); |
| sp_asm->call(Address::Absolute(Thread::ExceptionEntryPointOffset())); |
| // TODO: this call should never return as it should make a long jump to |
| // the appropriate catch block |
| // Release argument |
| sp_asm->addl(ESP, Immediate(kPointerSize)); |
| sp_asm->jmp(&continuation_); |
| } |
| |
| } // namespace art |