| commit | 79bb184ec0a661bf1276eef555dd5e20828bc528 | [log] [tgz] |
|---|---|---|
| author | Vladimir Kostyukov <vladimir.kostyukov@intel.com> | Tue Jul 01 18:28:43 2014 +0700 |
| committer | Vladimir Kostyukov <vladimir.kostyukov@intel.com> | Wed Jul 09 10:59:33 2014 +0000 |
| tree | ccac7bc93ddca873940467ce8be7472a8b8915f5 | |
| parent | 62f28f943e2da2873c7a09096c292f01a21c6478 [diff] |
ART: Correct disassembling of regs from opcodes
Registers, which are part of opcode might have 1-byte size
or 2-byte size depending on the instruction and 66h prefix.
This patch makes the decoding of such instruction correct.
Examples:
- '664155' should be decoded as 'push r13w'
(66h + REX.B)
- '41B320' should be decoded as 'mov r11l, 0x20'
(byte-operand + REX.B)
Change-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>