Multi-target Codegen cleanup
Trying to get a bit more consistent in the abstraction layer
naming:
genXXX -> high-level codegen, for ex: genIGet()
opXXX -> instruction-level output, for ex: opRegImm()
Also more fleshing out of the Mips codegen support.
Change-Id: Iafdf397cbb5015bfe3aa2c38680d96c7c05f8bc4
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index 5f75ef8..b47fae1 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -75,7 +75,7 @@
cUnit->frameSize - (spillCount * 4));
genRegRegCheck(cUnit, kCondCc, rLR, r12, NULL,
kThrowStackOverflow);
- genRegCopy(cUnit, rSP, rLR); // Establish stack
+ opRegCopy(cUnit, rSP, rLR); // Establish stack
} else {
opRegImm(cUnit, kOpSub, rSP,
cUnit->frameSize - (spillCount * 4));
diff --git a/src/compiler/codegen/arm/Codegen.h b/src/compiler/codegen/arm/Codegen.h
index 49e39db..b985e1b 100644
--- a/src/compiler/codegen/arm/Codegen.h
+++ b/src/compiler/codegen/arm/Codegen.h
@@ -29,6 +29,8 @@
#if defined(_CODEGEN_C)
LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target);
/* Forward declaraton the portable versions due to circular dependency */
bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
@@ -47,11 +49,9 @@
LIR* callRuntimeHelper(CompilationUnit* cUnit, int reg);
RegLocation getRetLoc(CompilationUnit* cUnit);
LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
-void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
- int srcLo, int srcHi);
-LIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue);
+void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+ int srcLo, int srcHi);
+LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
RegLocation rlFree);
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 094b952..9ef7b7b 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -228,12 +228,12 @@
DCHECK(!FPREG(rlResult.lowReg));
newLIR0(cUnit, kThumb2Fmstat);
- genIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
+ opIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
newLIR2(cUnit, kThumb2MovImmShift, rlResult.lowReg,
modifiedImmediate(-defaultResult)); // Must not alter ccodes
genBarrier(cUnit);
- genIT(cUnit, kArmCondEq, "");
+ opIT(cUnit, kArmCondEq, "");
loadConstant(cUnit, rlResult.lowReg, 0);
genBarrier(cUnit);
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index 77d6066..03a69d5 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -212,10 +212,12 @@
return newLIR0(cUnit, opcode);
}
-LIR* opCondBranch(CompilationUnit* cUnit, ConditionCode cc)
+LIR* opCondBranch(CompilationUnit* cUnit, ConditionCode cc, LIR* target)
{
- return newLIR2(cUnit, kThumb2BCond, 0 /* offset to be patched */,
- oatArmConditionEncoding(cc));
+ LIR* branch = newLIR2(cUnit, kThumb2BCond, 0 /* offset to be patched */,
+ oatArmConditionEncoding(cc));
+ branch->target = target;
+ return branch;
}
LIR* opReg(CompilationUnit* cUnit, OpKind op, int rDestSrc)
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index 1dfb90d..838fcaf 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -37,7 +37,7 @@
* met, and an "E" means the instruction is executed if the condition
* is not met.
*/
-LIR* genIT(CompilationUnit* cUnit, ArmConditionCode code, const char* guide)
+LIR* opIT(CompilationUnit* cUnit, ArmConditionCode code, const char* guide)
{
int mask;
int condBit = code & 1;
@@ -58,7 +58,7 @@
case 0:
break;
default:
- LOG(FATAL) << "OAT: bad case in genIT";
+ LOG(FATAL) << "OAT: bad case in opIT";
}
mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) |
(1 << (3 - strlen(guide)));
@@ -124,13 +124,12 @@
newLIR2(cUnit, kThumb2LdmiaWB, rBase, (1 << rKey) | (1 << rDisp));
opRegReg(cUnit, kOpCmp, rKey, rlSrc.lowReg);
// Go if match. NOTE: No instruction set switch here - must stay Thumb2
- genIT(cUnit, kArmCondEq, "");
+ opIT(cUnit, kArmCondEq, "");
LIR* switchBranch = newLIR1(cUnit, kThumb2AddPCR, rDisp);
tabRec->bxInst = switchBranch;
// Needs to use setflags encoding here
newLIR3(cUnit, kThumb2SubsRRI12, rIdx, rIdx, 1);
- LIR* branch = opCondBranch(cUnit, kCondNe);
- branch->target = (LIR*)target;
+ opCondBranch(cUnit, kCondNe, target);
}
@@ -166,7 +165,7 @@
}
// Bounds check - if < 0 or >= size continue following switch
opRegImm(cUnit, kOpCmp, keyReg, size-1);
- LIR* branchOver = opCondBranch(cUnit, kCondHi);
+ LIR* branchOver = opCondBranch(cUnit, kCondHi, NULL);
// Load the displacement from the switch table
int dispReg = oatAllocTemp(cUnit);
@@ -328,7 +327,7 @@
opRegImm(cUnit, kOpLsl, r2, LW_LOCK_OWNER_SHIFT);
newLIR3(cUnit, kThumb2Bfc, r1, LW_HASH_STATE_SHIFT, LW_LOCK_OWNER_SHIFT - 1);
opRegReg(cUnit, kOpSub, r1, r2);
- hopBranch = opCondBranch(cUnit, kCondNe);
+ hopBranch = opCondBranch(cUnit, kCondNe, NULL);
oatGenMemBarrier(cUnit, kSY);
storeWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r3);
branch = opNone(cUnit, kOpUncondBr);
@@ -373,12 +372,12 @@
int tReg = oatAllocTemp(cUnit);
loadConstant(cUnit, tReg, -1);
opRegReg(cUnit, kOpCmp, rlSrc1.highReg, rlSrc2.highReg);
- LIR* branch1 = opCondBranch(cUnit, kCondLt);
- LIR* branch2 = opCondBranch(cUnit, kCondGt);
+ LIR* branch1 = opCondBranch(cUnit, kCondLt, NULL);
+ LIR* branch2 = opCondBranch(cUnit, kCondGt, NULL);
opRegRegReg(cUnit, kOpSub, tReg, rlSrc1.lowReg, rlSrc2.lowReg);
- LIR* branch3 = opCondBranch(cUnit, kCondEq);
+ LIR* branch3 = opCondBranch(cUnit, kCondEq, NULL);
- genIT(cUnit, kArmCondHi, "E");
+ opIT(cUnit, kArmCondHi, "E");
newLIR2(cUnit, kThumb2MovImmShift, tReg, modifiedImmediate(-1));
loadConstant(cUnit, tReg, 1);
genBarrier(cUnit);
@@ -404,8 +403,8 @@
* Generate a register comparison to an immediate and branch. Caller
* is responsible for setting branch target field.
*/
-LIR* genCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue)
+LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
+ int checkValue, LIR* target)
{
LIR* branch;
int modImm;
@@ -428,9 +427,10 @@
}
branch = newLIR2(cUnit, kThumbBCond, 0, armCond);
}
+ branch->target = target;
return branch;
}
-LIR* genRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
+LIR* opRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
{
LIR* res;
ArmOpcode opcode;
@@ -457,14 +457,14 @@
return res;
}
-LIR* genRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
+LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
- LIR* res = genRegCopyNoInsert(cUnit, rDest, rSrc);
+ LIR* res = opRegCopyNoInsert(cUnit, rDest, rSrc);
oatAppendLIR(cUnit, (LIR*)res);
return res;
}
-void genRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
+void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
bool destFP = FPREG(destLo) && FPREG(destHi);
@@ -473,7 +473,7 @@
DCHECK_EQ(FPREG(destLo), FPREG(destHi));
if (destFP) {
if (srcFP) {
- genRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
} else {
newLIR3(cUnit, kThumb2Fmdrr, S2D(destLo, destHi), srcLo, srcHi);
}
@@ -483,11 +483,11 @@
} else {
// Handle overlap
if (srcHi == destLo) {
- genRegCopy(cUnit, destHi, srcHi);
- genRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
} else {
- genRegCopy(cUnit, destLo, srcLo);
- genRegCopy(cUnit, destHi, srcHi);
+ opRegCopy(cUnit, destLo, srcLo);
+ opRegCopy(cUnit, destHi, srcHi);
}
}
}