commit 8e895008a3e2f2813bb46cb0c6bc76884e46e9ac
author Nicolas Geoffray <ngeoffray@google.com> Tue Nov 26 14:05:40 2019 +0000
committer Nicolas Geoffray <ngeoffray@google.com> Tue Nov 26 14:06:21 2019 +0000
tree c30e54521e1b31eb50e282b54be138f888d9870e
parent 7c9cfe8b3f986e7cbc18350ad7b9b72f58f5846c

Revert "Revert^2 "Implement Dot Product Vectorization for x86""

This reverts commit 7cf5607f472020711e36eedbbfebb25b40d3f90e.

Bug: 144947842

Reason for revert: Seems to have broken android.jvmti.cts.JvmtiHostTest1936#testJvmt

Change-Id: Ied6ff6ddf1cb2e3e76adcaa0fda5e36af254b7c5

compiler/optimizing/code_generator_vector_x86.cc

diff --git a/compiler/optimizing/code_generator_vector_x86.cc b/compiler/optimizing/code_generator_vector_x86.cc
index 1390af2..68aef77 100644
--- a/compiler/optimizing/code_generator_vector_x86.cc
+++ b/compiler/optimizing/code_generator_vector_x86.cc
@@ -1201,38 +1201,11 @@
 }
 
 void LocationsBuilderX86::VisitVecDotProd(HVecDotProd* instruction) {
-  LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction);
-  locations->SetInAt(0, Location::RequiresFpuRegister());
-  locations->SetInAt(1, Location::RequiresFpuRegister());
-  locations->SetInAt(2, Location::RequiresFpuRegister());
-  locations->SetOut(Location::SameAsFirstInput());
-  locations->AddTemp(Location::RequiresFpuRegister());
+  LOG(FATAL) << "No SIMD for " << instruction->GetId();
 }
 
 void InstructionCodeGeneratorX86::VisitVecDotProd(HVecDotProd* instruction) {
-  bool cpu_has_avx = CpuHasAvxFeatureFlag();
-  LocationSummary* locations = instruction->GetLocations();
-  XmmRegister acc = locations->InAt(0).AsFpuRegister<XmmRegister>();
-  XmmRegister left = locations->InAt(1).AsFpuRegister<XmmRegister>();
-  XmmRegister right = locations->InAt(2).AsFpuRegister<XmmRegister>();
-  switch (instruction->GetPackedType()) {
-    case DataType::Type::kInt32: {
-      DCHECK_EQ(4u, instruction->GetVectorLength());
-      XmmRegister tmp = locations->GetTemp(0).AsFpuRegister<XmmRegister>();
-      if (!cpu_has_avx) {
-        __ movaps(tmp, right);
-        __ pmaddwd(tmp, left);
-        __ paddd(acc, tmp);
-      } else {
-        __ vpmaddwd(tmp, left, right);
-        __ vpaddd(acc, acc, tmp);
-      }
-      break;
-    }
-    default:
-      LOG(FATAL) << "Unsupported SIMD Type" << instruction->GetPackedType();
-      UNREACHABLE();
-  }
+  LOG(FATAL) << "No SIMD for " << instruction->GetId();
 }
 
 // Helper to set up locations for vector memory operations.

compiler/optimizing/code_generator_vector_x86_64.cc

diff --git a/compiler/optimizing/code_generator_vector_x86_64.cc b/compiler/optimizing/code_generator_vector_x86_64.cc
index 7fac44d..19dfd1d 100644
--- a/compiler/optimizing/code_generator_vector_x86_64.cc
+++ b/compiler/optimizing/code_generator_vector_x86_64.cc
@@ -1174,38 +1174,11 @@
 }
 
 void LocationsBuilderX86_64::VisitVecDotProd(HVecDotProd* instruction) {
-  LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction);
-  locations->SetInAt(0, Location::RequiresFpuRegister());
-  locations->SetInAt(1, Location::RequiresFpuRegister());
-  locations->SetInAt(2, Location::RequiresFpuRegister());
-  locations->SetOut(Location::SameAsFirstInput());
-  locations->AddTemp(Location::RequiresFpuRegister());
+  LOG(FATAL) << "No SIMD for " << instruction->GetId();
 }
 
 void InstructionCodeGeneratorX86_64::VisitVecDotProd(HVecDotProd* instruction) {
-  bool cpu_has_avx = CpuHasAvxFeatureFlag();
-  LocationSummary* locations = instruction->GetLocations();
-  XmmRegister acc = locations->InAt(0).AsFpuRegister<XmmRegister>();
-  XmmRegister left = locations->InAt(1).AsFpuRegister<XmmRegister>();
-  XmmRegister right = locations->InAt(2).AsFpuRegister<XmmRegister>();
-  switch (instruction->GetPackedType()) {
-    case DataType::Type::kInt32: {
-      DCHECK_EQ(4u, instruction->GetVectorLength());
-      XmmRegister tmp = locations->GetTemp(0).AsFpuRegister<XmmRegister>();
-      if (!cpu_has_avx) {
-        __ movaps(tmp, right);
-        __ pmaddwd(tmp, left);
-        __ paddd(acc, tmp);
-      } else {
-        __ vpmaddwd(tmp, left, right);
-        __ vpaddd(acc, acc, tmp);
-      }
-      break;
-    }
-    default:
-      LOG(FATAL) << "Unsupported SIMD Type" << instruction->GetPackedType();
-      UNREACHABLE();
-  }
+  LOG(FATAL) << "No SIMD for " << instruction->GetId();
 }
 
 // Helper to set up locations for vector memory operations.

compiler/optimizing/loop_optimization.cc

diff --git a/compiler/optimizing/loop_optimization.cc b/compiler/optimizing/loop_optimization.cc
index 567a41e..9c4e9d2 100644
--- a/compiler/optimizing/loop_optimization.cc
+++ b/compiler/optimizing/loop_optimization.cc
@@ -1623,19 +1623,13 @@
                              kNoDotProd;
             return TrySetVectorLength(16);
           case DataType::Type::kUint16:
-            *restrictions |= kNoDiv |
-                             kNoAbs |
-                             kNoSignedHAdd |
-                             kNoUnroundedHAdd |
-                             kNoSAD |
-                             kNoDotProd;
-            return TrySetVectorLength(8);
           case DataType::Type::kInt16:
             *restrictions |= kNoDiv |
                              kNoAbs |
                              kNoSignedHAdd |
                              kNoUnroundedHAdd |
-                             kNoSAD;
+                             kNoSAD|
+                             kNoDotProd;
             return TrySetVectorLength(8);
           case DataType::Type::kInt32:
             *restrictions |= kNoDiv | kNoSAD;
@@ -2172,7 +2166,7 @@
                                               bool generate_code,
                                               DataType::Type reduction_type,
                                               uint64_t restrictions) {
-  if (!instruction->IsAdd() || reduction_type != DataType::Type::kInt32) {
+  if (!instruction->IsAdd() || (reduction_type != DataType::Type::kInt32)) {
     return false;
   }