Implement Intel QuasiAtomics.
Don't use striped locks for 64bit atomics on x86.
Modify QuasiAtomic::Swap to be QuasiAtomic::Write that fits our current use of
Swap and is closer to Intel's implementation.
Return that MIPS doesn't support 64bit compare-and-exchanges in AtomicLong.
Set the SSE2 flag for host and target Intel ART builds as our codegen assumes
it.
Change-Id: Ic1cd5c3b06838e42c6f94e0dd91e77a2d0bb5868
diff --git a/src/native/sun_misc_Unsafe.cc b/src/native/sun_misc_Unsafe.cc
index 5dc32b0..cb06a0b 100644
--- a/src/native/sun_misc_Unsafe.cc
+++ b/src/native/sun_misc_Unsafe.cc
@@ -27,7 +27,7 @@
volatile int32_t* address = reinterpret_cast<volatile int32_t*>(raw_addr);
// Note: android_atomic_release_cas() returns 0 on success, not failure.
int result = android_atomic_release_cas(expectedValue, newValue, address);
- return (result == 0);
+ return (result == 0) ? JNI_TRUE : JNI_FALSE;
}
static jboolean Unsafe_compareAndSwapLong(JNIEnv* env, jobject, jobject javaObj, jlong offset, jlong expectedValue, jlong newValue) {
@@ -36,8 +36,8 @@
byte* raw_addr = reinterpret_cast<byte*>(obj) + offset;
volatile int64_t* address = reinterpret_cast<volatile int64_t*>(raw_addr);
// Note: android_atomic_cmpxchg() returns 0 on success, not failure.
- int result = QuasiAtomic::Cas64(expectedValue, newValue, address);
- return (result == 0);
+ bool success = QuasiAtomic::Cas64(expectedValue, newValue, address);
+ return success ? JNI_TRUE : JNI_FALSE;
}
static jboolean Unsafe_compareAndSwapObject(JNIEnv* env, jobject, jobject javaObj, jlong offset, jobject javaExpectedValue, jobject javaNewValue) {
@@ -53,7 +53,7 @@
if (result == 0) {
Runtime::Current()->GetHeap()->WriteBarrierField(obj, MemberOffset(offset), newValue);
}
- return (result == 0);
+ return (result == 0) ? JNI_TRUE : JNI_FALSE;
}
static jint Unsafe_getInt(JNIEnv* env, jobject, jobject javaObj, jlong offset) {