Merge "MIPS64: Implement intrinsic java.lang.Thread.currentThread()"
diff --git a/compiler/optimizing/code_generator_mips64.cc b/compiler/optimizing/code_generator_mips64.cc
index c9f8493..ad0a39c 100644
--- a/compiler/optimizing/code_generator_mips64.cc
+++ b/compiler/optimizing/code_generator_mips64.cc
@@ -40,9 +40,6 @@
// We need extra temporary/scratch registers (in addition to AT) in some cases.
static constexpr FpuRegister FTMP = F8;
-// ART Thread Register.
-static constexpr GpuRegister TR = S1;
-
Location Mips64ReturnLocation(Primitive::Type return_type) {
switch (return_type) {
case Primitive::kPrimBoolean:
diff --git a/compiler/optimizing/intrinsics_mips64.cc b/compiler/optimizing/intrinsics_mips64.cc
index 52e2cbe..1b4d161 100644
--- a/compiler/optimizing/intrinsics_mips64.cc
+++ b/compiler/optimizing/intrinsics_mips64.cc
@@ -725,6 +725,24 @@
__ Sd(val, adr, 0);
}
+// Thread java.lang.Thread.currentThread()
+void IntrinsicLocationsBuilderMIPS64::VisitThreadCurrentThread(HInvoke* invoke) {
+ LocationSummary* locations = new (arena_) LocationSummary(invoke,
+ LocationSummary::kNoCall,
+ kIntrinsified);
+ locations->SetOut(Location::RequiresRegister());
+}
+
+void IntrinsicCodeGeneratorMIPS64::VisitThreadCurrentThread(HInvoke* invoke) {
+ Mips64Assembler* assembler = GetAssembler();
+ GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
+
+ __ LoadFromOffset(kLoadUnsignedWord,
+ out,
+ TR,
+ Thread::PeerOffset<kMips64PointerSize>().Int32Value());
+}
+
// Unimplemented intrinsics.
#define UNIMPLEMENTED_INTRINSIC(Name) \
@@ -736,7 +754,6 @@
UNIMPLEMENTED_INTRINSIC(MathRoundDouble)
UNIMPLEMENTED_INTRINSIC(MathRoundFloat)
-UNIMPLEMENTED_INTRINSIC(ThreadCurrentThread)
UNIMPLEMENTED_INTRINSIC(UnsafeGet)
UNIMPLEMENTED_INTRINSIC(UnsafeGetVolatile)
UNIMPLEMENTED_INTRINSIC(UnsafeGetLong)
diff --git a/runtime/arch/mips64/registers_mips64.h b/runtime/arch/mips64/registers_mips64.h
index cd94d5e..1d07d47 100644
--- a/runtime/arch/mips64/registers_mips64.h
+++ b/runtime/arch/mips64/registers_mips64.h
@@ -52,7 +52,6 @@
S6 = 22,
S7 = 23,
T8 = 24, // More temporaries.
- TMP = T8, // scratch register (in addition to AT)
T9 = 25,
K0 = 26, // Reserved for trap handler.
K1 = 27,
@@ -60,6 +59,8 @@
SP = 29, // Stack pointer.
S8 = 30, // Saved value/frame pointer.
RA = 31, // Return address.
+ TR = S1, // ART Thread Register
+ TMP = T8, // scratch register (in addition to AT)
kNumberOfGpuRegisters = 32,
kNoGpuRegister = -1 // Signals an illegal register.
};