Quick compiler: refactored listing & const fix
This CL started off as a simple fix to Issue 4959751, which
identified a case in which compiler debugging listings could read
uninitialized data. The fix ended up pulling a few strings - we
had two distinct dex printing routines (one was focused on SSA names
and was used by the .dot graph dumper), while the other was used with
verbose codegen listing.
Ended up combining the two routines and significantly enhancing the
value of the verbose debug output. We now always use ssa register
names, and also show the constant values of ssa names which are known
to be const following constant propagation.
Along the way, deleted a bit of useless code that remapped all
registers in a phi set to have the same name, and also got rid of
some duplicate listing helper LIR pseudo ops.
Somee examples of the new listing:
-------- dalvik offset: 0x2 @ const/4 v0_1#0x1, #1
the format of the vreg is:
v<orignal Dalvik vnum>_<ssa instance>[#hex value of immediate]
In this example, we don't add any new info (the listing already had #1),
but we also show this form in uses:
invoke-virtual v0_2, v1_3#0x40
Also improved is the listing output of potentially throwing instructions
which are broken into two parts: the check portion and the work portion.
Both halves now show the full disassembly. For example:
-------- dalvik offset: 0x13 @ Check1: invoke-virtual v0_2, v1_3#0x40
....code here
....code here
-------- dalvik offset: 0x13 @ Check2: invoke-virtual v0_2, v1_3#0x40
Dalvik instructions which are optimized away prior to code generation
are displayed in sqare brackets. For example:
-------- dalvik offset: 0x16 @ [move-result-object v0_3]--optimized away
Finally, Phi nodes show which incoming block an operand came through.
In the following example:
-------- dalvik offset: 0x5 @ Phi v1_2 = (v1_1#0x0:4, v1_2:12, v1_3#0x1:14)
Sreg v1_2 is a merge of a constant 0x0 from incoming block 4, a non-const
value from block 12 and a const 0x1 from block 14.
Change-Id: Ib6c19c19ab8a48509d43d8b0e5ed3e8e7ce9fc82
diff --git a/src/compiler/codegen/arm/call_arm.cc b/src/compiler/codegen/arm/call_arm.cc
index 950105c..9696bca 100644
--- a/src/compiler/codegen/arm/call_arm.cc
+++ b/src/compiler/codegen/arm/call_arm.cc
@@ -129,13 +129,8 @@
{
/* Mark the beginning of a Dalvik instruction for line tracking */
char* inst_str = cu->verbose ?
- GetDalvikDisassembly(cu, mir->dalvikInsn, "") : NULL;
+ GetDalvikDisassembly(cu, mir) : NULL;
MarkBoundary(cu, mir->offset, inst_str);
- /* Don't generate the SSA annotation unless verbose mode is on */
- if (cu->verbose && mir->ssa_rep) {
- char* ssa_string = GetSSAString(cu, mir->ssa_rep);
- NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
- }
}
static MIR* SpecialIGet(CompilationUnit* cu, BasicBlock** bb, MIR* mir,
diff --git a/src/compiler/codegen/arm/target_arm.cc b/src/compiler/codegen/arm/target_arm.cc
index 272dc46..493b4a9 100644
--- a/src/compiler/codegen/arm/target_arm.cc
+++ b/src/compiler/codegen/arm/target_arm.cc
@@ -584,23 +584,6 @@
// Start allocation at r2 in an attempt to avoid clobbering return values
pool->next_core_reg = r2;
-
- // Construct the alias map.
- cu->phi_alias_map = static_cast<int*>
- (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
- for (int i = 0; i < cu->num_ssa_regs; i++) {
- cu->phi_alias_map[i] = i;
- }
- for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
- int def_reg = phi->ssa_rep->defs[0];
- for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
- for (int j = 0; j < cu->num_ssa_regs; j++) {
- if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
- cu->phi_alias_map[j] = def_reg;
- }
- }
- }
- }
}
void ArmCodegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,
diff --git a/src/compiler/codegen/codegen_util.cc b/src/compiler/codegen/codegen_util.cc
index 11ab9c0..bab5cd9 100644
--- a/src/compiler/codegen/codegen_util.cc
+++ b/src/compiler/codegen/codegen_util.cc
@@ -177,7 +177,6 @@
* Debugging macros
*/
#define DUMP_RESOURCE_MASK(X)
-#define DUMP_SSA_REP(X)
/* Pretty-print a LIR instruction */
void DumpLIRInsn(CompilationUnit* cu, LIR* lir, unsigned char* base_addr)
@@ -199,12 +198,6 @@
case kPseudoBarrier:
LOG(INFO) << "-------- BARRIER";
break;
- case kPseudoExtended:
- LOG(INFO) << "-------- " << reinterpret_cast<char*>(dest);
- break;
- case kPseudoSSARep:
- DUMP_SSA_REP(LOG(INFO) << "-------- kMirOpPhi: " << reinterpret_cast<char*>(dest));
- break;
case kPseudoEntryBlock:
LOG(INFO) << "-------- entry offset: 0x" << std::hex << dest;
break;
diff --git a/src/compiler/codegen/gen_invoke.cc b/src/compiler/codegen/gen_invoke.cc
index afaa053..ebc1a98 100644
--- a/src/compiler/codegen/gen_invoke.cc
+++ b/src/compiler/codegen/gen_invoke.cc
@@ -1337,7 +1337,8 @@
info->result.location = kLocInvalid;
} else {
info->result = GetRawDest(cu, move_result_mir);
- move_result_mir->dalvikInsn.opcode = Instruction::NOP;
+ move_result_mir->meta.original_opcode = move_result_mir->dalvikInsn.opcode;
+ move_result_mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
}
info->num_arg_words = mir->ssa_rep->num_uses;
info->args = (info->num_arg_words == 0) ? NULL : static_cast<RegLocation*>
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index ed884b2..3bb4689 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -516,22 +516,6 @@
for (int i = 0; i < num_fp_temps; i++) {
MarkTemp(cu, fp_temps[i]);
}
- // Construct the alias map.
- cu->phi_alias_map = static_cast<int*>
- (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
- for (int i = 0; i < cu->num_ssa_regs; i++) {
- cu->phi_alias_map[i] = i;
- }
- for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
- int def_reg = phi->ssa_rep->defs[0];
- for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
- for (int j = 0; j < cu->num_ssa_regs; j++) {
- if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
- cu->phi_alias_map[j] = def_reg;
- }
- }
- }
- }
}
void MipsCodegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free)
diff --git a/src/compiler/codegen/mir_to_gbc.cc b/src/compiler/codegen/mir_to_gbc.cc
index 2c27bb0..6758bb9 100644
--- a/src/compiler/codegen/mir_to_gbc.cc
+++ b/src/compiler/codegen/mir_to_gbc.cc
@@ -1824,6 +1824,7 @@
SSARepresentation* ssa_rep = work_half->ssa_rep;
work_half->ssa_rep = mir->ssa_rep;
mir->ssa_rep = ssa_rep;
+ work_half->meta.original_opcode = work_half->dalvikInsn.opcode;
work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
if (bb->successor_block_list.block_list_type == kCatch) {
llvm::Function* intr = cu->intrinsic_helper->GetIntrinsicFunction(
diff --git a/src/compiler/codegen/mir_to_lir.cc b/src/compiler/codegen/mir_to_lir.cc
index fc3df6e..6ec7edb 100644
--- a/src/compiler/codegen/mir_to_lir.cc
+++ b/src/compiler/codegen/mir_to_lir.cc
@@ -611,29 +611,11 @@
return res;
}
-// Process extended MIR instructions (such as PHI).
+// Process extended MIR instructions
static void HandleExtendedMethodMIR(CompilationUnit* cu, BasicBlock* bb, MIR* mir)
{
Codegen* cg = cu->cg.get();
- int op_offset = mir->dalvikInsn.opcode - kMirOpFirst;
- char* msg = NULL;
- if (cu->verbose) {
- msg = static_cast<char*>(NewMem(cu, strlen(extended_mir_op_names[op_offset]) + 1,
- false, kAllocDebugInfo));
- strcpy(msg, extended_mir_op_names[op_offset]);
- }
- LIR* op = NewLIR1(cu, kPseudoExtended, reinterpret_cast<uintptr_t>(msg));
-
switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
- case kMirOpPhi: {
- char* ssa_string = NULL;
- if (cu->verbose) {
- ssa_string = GetSSAString(cu, mir->ssa_rep);
- }
- op->flags.is_nop = true;
- NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
- break;
- }
case kMirOpCopy: {
RegLocation rl_src = GetSrc(cu, mir, 0);
RegLocation rl_dest = GetDest(cu, mir);
@@ -719,7 +701,7 @@
// Mark the beginning of a Dalvik instruction for line tracking.
char* inst_str = cu->verbose ?
- GetDalvikDisassembly(cu, mir->dalvikInsn, "") : NULL;
+ GetDalvikDisassembly(cu, mir) : NULL;
boundary_lir = MarkBoundary(cu, mir->offset, inst_str);
// Remember the first LIR for this block.
if (head_lir == NULL) {
@@ -728,12 +710,6 @@
head_lir->def_mask = ENCODE_ALL;
}
- // Don't generate the SSA annotation unless verbose mode is on.
- if (cu->verbose && mir->ssa_rep) {
- char* ssa_string = GetSSAString(cu, mir->ssa_rep);
- NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
- }
-
if (opcode == kMirOpCheck) {
// Combine check and work halves of throwing instruction.
MIR* work_half = mir->meta.throw_insn;
@@ -742,7 +718,7 @@
SSARepresentation* ssa_rep = work_half->ssa_rep;
work_half->ssa_rep = mir->ssa_rep;
mir->ssa_rep = ssa_rep;
- work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
+ work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpCheckPart2);
}
if (opcode >= kMirOpFirst) {
diff --git a/src/compiler/codegen/x86/target_x86.cc b/src/compiler/codegen/x86/target_x86.cc
index c3c79f1..e396e54 100644
--- a/src/compiler/codegen/x86/target_x86.cc
+++ b/src/compiler/codegen/x86/target_x86.cc
@@ -484,22 +484,6 @@
for (int i = 0; i < num_fp_temps; i++) {
MarkTemp(cu, fp_temps[i]);
}
- // Construct the alias map.
- cu->phi_alias_map = static_cast<int*>
- (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
- for (int i = 0; i < cu->num_ssa_regs; i++) {
- cu->phi_alias_map[i] = i;
- }
- for (MIR* phi = cu->phi_list; phi != NULL; phi = phi->meta.phi_next) {
- int def_reg = phi->ssa_rep->defs[0];
- for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
- for (int j = 0; j < cu->num_ssa_regs; j++) {
- if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
- cu->phi_alias_map[j] = def_reg;
- }
- }
- }
- }
}
void X86Codegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,
diff --git a/src/compiler/compiler_enums.h b/src/compiler/compiler_enums.h
index 6d8b27e..bdf7a8b 100644
--- a/src/compiler/compiler_enums.h
+++ b/src/compiler/compiler_enums.h
@@ -80,17 +80,15 @@
// Shared pseudo opcodes - must be < 0.
enum LIRPseudoOpcode {
- kPseudoExportedPC = -18,
- kPseudoSafepointPC = -17,
- kPseudoIntrinsicRetry = -16,
- kPseudoSuspendTarget = -15,
- kPseudoThrowTarget = -14,
- kPseudoCaseLabel = -13,
- kPseudoMethodEntry = -12,
- kPseudoMethodExit = -11,
- kPseudoBarrier = -10,
- kPseudoExtended = -9,
- kPseudoSSARep = -8,
+ kPseudoExportedPC = -16,
+ kPseudoSafepointPC = -15,
+ kPseudoIntrinsicRetry = -14,
+ kPseudoSuspendTarget = -13,
+ kPseudoThrowTarget = -12,
+ kPseudoCaseLabel = -11,
+ kPseudoMethodEntry = -10,
+ kPseudoMethodExit = -9,
+ kPseudoBarrier = -8,
kPseudoEntryBlock = -7,
kPseudoExitBlock = -6,
kPseudoTargetLabel = -5,
@@ -114,6 +112,7 @@
kMirOpRangeCheck,
kMirOpDivZeroCheck,
kMirOpCheck,
+ kMirOpCheckPart2,
kMirOpLast,
};
diff --git a/src/compiler/compiler_ir.h b/src/compiler/compiler_ir.h
index 2923587..9c67cd5 100644
--- a/src/compiler/compiler_ir.h
+++ b/src/compiler/compiler_ir.h
@@ -214,10 +214,10 @@
SSARepresentation* ssa_rep;
int optimization_flags;
union {
- // Used to quickly locate all Phi opcodes.
- MIR* phi_next;
// Establish link between two halves of throwing instructions.
MIR* throw_insn;
+ // Saved opcode for NOP'd MIRs
+ Instruction::Code original_opcode;
} meta;
};
@@ -307,8 +307,6 @@
ssa_last_defs(NULL),
is_constant_v(NULL),
constant_values(NULL),
- phi_alias_map(NULL),
- phi_list(NULL),
reg_location(NULL),
promotion_map(NULL),
method_sreg(0),
@@ -420,8 +418,6 @@
int* ssa_last_defs; // length == method->registers_size
ArenaBitVector* is_constant_v; // length == num_ssa_reg
int* constant_values; // length == num_ssa_reg
- int* phi_alias_map; // length == num_ssa_reg
- MIR* phi_list;
// Use counts of ssa names.
GrowableList use_counts; // Weighted by nesting depth
diff --git a/src/compiler/compiler_utility.cc b/src/compiler/compiler_utility.cc
index d8a5956..2e67902 100644
--- a/src/compiler/compiler_utility.cc
+++ b/src/compiler/compiler_utility.cc
@@ -19,18 +19,19 @@
namespace art {
const char* extended_mir_op_names[kMirOpLast - kMirOpFirst] = {
- "kMirOpPhi",
- "kMirOpCopy",
- "kMirFusedCmplFloat",
- "kMirFusedCmpgFloat",
- "kMirFusedCmplDouble",
- "kMirFusedCmpgDouble",
- "kMirFusedCmpLong",
- "kMirNop",
- "kMirOpNullCheck",
- "kMirOpRangeCheck",
- "kMirOpDivZeroCheck",
- "kMirOpCheck",
+ "Phi",
+ "Copy",
+ "FusedCmplFloat",
+ "FusedCmpgFloat",
+ "FusedCmplDouble",
+ "FusedCmpgDouble",
+ "FusedCmpLong",
+ "Nop",
+ "OpNullCheck",
+ "OpRangeCheck",
+ "OpDivZeroCheck",
+ "Check1",
+ "Check2",
};
#ifdef WITH_MEMSTATS
diff --git a/src/compiler/dataflow.cc b/src/compiler/dataflow.cc
index 810e6c6..22135b1 100644
--- a/src/compiler/dataflow.cc
+++ b/src/compiler/dataflow.cc
@@ -854,45 +854,94 @@
return cu->raw_use_counts.elem_list[s_reg];
}
-
-char* GetDalvikDisassembly(CompilationUnit* cu,
- const DecodedInstruction& insn, const char* note)
+static std::string GetSSAName(const CompilationUnit* cu, int ssa_reg)
{
+ return StringPrintf("v%d_%d", SRegToVReg(cu, ssa_reg), SRegToSubscript(cu, ssa_reg));
+}
+
+// Similar to GetSSAName, but if ssa name represents an immediate show that as well.
+static std::string GetSSANameWithConst(const CompilationUnit* cu, int ssa_reg, bool singles_only)
+{
+ if (cu->reg_location[ssa_reg].is_const) {
+ if (!singles_only && cu->reg_location[ssa_reg].wide) {
+ int64_t immval = cu->constant_values[ssa_reg + 1];
+ immval = (immval << 32) | cu->constant_values[ssa_reg];
+ return StringPrintf("v%d_%d#0x%llx", SRegToVReg(cu, ssa_reg),
+ SRegToSubscript(cu, ssa_reg), immval);
+ } else {
+ int32_t immval = cu->constant_values[ssa_reg];
+ return StringPrintf("v%d_%d#0x%x", SRegToVReg(cu, ssa_reg),
+ SRegToSubscript(cu, ssa_reg), immval);
+ }
+ } else {
+ return StringPrintf("v%d_%d", SRegToVReg(cu, ssa_reg), SRegToSubscript(cu, ssa_reg));
+ }
+}
+
+
+char* GetDalvikDisassembly(CompilationUnit* cu, const MIR* mir)
+{
+ DecodedInstruction insn = mir->dalvikInsn;
std::string str;
+ int flags = 0;
int opcode = insn.opcode;
- int df_attributes = oat_data_flow_attributes[opcode];
- int flags;
char* ret;
+ bool nop = false;
+ SSARepresentation* ssa_rep = mir->ssa_rep;
+ Instruction::Format dalvik_format = Instruction::k10x; // Default to no-operand format
+ int defs = (ssa_rep != NULL) ? ssa_rep->num_defs : 0;
+ int uses = (ssa_rep != NULL) ? ssa_rep->num_uses : 0;
+
+ // Handle special cases.
+ if ((opcode == kMirOpCheck) || (opcode == kMirOpCheckPart2)) {
+ str.append(extended_mir_op_names[opcode - kMirOpFirst]);
+ str.append(": ");
+ // Recover the original Dex instruction
+ insn = mir->meta.throw_insn->dalvikInsn;
+ ssa_rep = mir->meta.throw_insn->ssa_rep;
+ defs = ssa_rep->num_defs;
+ uses = ssa_rep->num_uses;
+ opcode = insn.opcode;
+ } else if (opcode == kMirOpNop) {
+ str.append("[");
+ insn.opcode = mir->meta.original_opcode;
+ opcode = mir->meta.original_opcode;
+ nop = true;
+ }
if (opcode >= kMirOpFirst) {
- if (opcode == kMirOpPhi) {
- str.append("PHI");
- } else if (opcode == kMirOpCheck) {
- str.append("Check");
- } else {
- str.append(StringPrintf("Opcode %#x", opcode));
- }
- flags = 0;
+ str.append(extended_mir_op_names[opcode - kMirOpFirst]);
} else {
- str.append(Instruction::Name(insn.opcode));
+ dalvik_format = Instruction::FormatOf(insn.opcode);
flags = Instruction::FlagsOf(insn.opcode);
+ str.append(Instruction::Name(insn.opcode));
}
- if (note) {
- str.append(note);
- }
-
- /* For branches, decode the instructions to print out the branch targets */
- if (flags & Instruction::kBranch) {
- Instruction::Format dalvik_format = Instruction::FormatOf(insn.opcode);
+ if (opcode == kMirOpPhi) {
+ int* incoming = reinterpret_cast<int*>(insn.vB);
+ str.append(StringPrintf(" %s = (%s",
+ GetSSANameWithConst(cu, ssa_rep->defs[0], true).c_str(),
+ GetSSANameWithConst(cu, ssa_rep->uses[0], true).c_str()));
+ str.append(StringPrintf(":%d",incoming[0]));
+ int i;
+ for (i = 1; i < uses; i++) {
+ str.append(StringPrintf(", %s:%d",
+ GetSSANameWithConst(cu, ssa_rep->uses[i], true).c_str(),
+ incoming[i]));
+ }
+ str.append(")");
+ } else if (flags & Instruction::kBranch) {
+ // For branches, decode the instructions to print out the branch targets.
int offset = 0;
switch (dalvik_format) {
case Instruction::k21t:
- str.append(StringPrintf(" v%d,", insn.vA));
+ str.append(StringPrintf(" %s,", GetSSANameWithConst(cu, ssa_rep->uses[0], false).c_str()));
offset = insn.vB;
break;
case Instruction::k22t:
- str.append(StringPrintf(" v%d, v%d,", insn.vA, insn.vB));
+ str.append(StringPrintf(" %s, %s,", GetSSANameWithConst(cu, ssa_rep->uses[0], false).c_str(),
+ GetSSANameWithConst(cu, ssa_rep->uses[cu->reg_location[ssa_rep->uses[0]].wide
+ ? 2 : 1], false).c_str()));
offset = insn.vC;
break;
case Instruction::k10t:
@@ -903,193 +952,57 @@
default:
LOG(FATAL) << "Unexpected branch format " << dalvik_format << " from " << insn.opcode;
}
- str.append(StringPrintf(" (%c%x)",
- offset > 0 ? '+' : '-',
- offset > 0 ? offset : -offset));
- } else if (df_attributes & DF_FORMAT_35C) {
- unsigned int i;
- for (i = 0; i < insn.vA; i++) {
- if (i != 0) str.append(",");
- str.append(StringPrintf(" v%d", insn.arg[i]));
- }
- }
- else if (df_attributes & DF_FORMAT_3RC) {
- str.append(StringPrintf(" v%d..v%d", insn.vC, insn.vC + insn.vA - 1));
+ str.append(StringPrintf(" 0x%x (%c%x)", mir->offset + offset,
+ offset > 0 ? '+' : '-', offset > 0 ? offset : -offset));
} else {
- if (df_attributes & DF_A_IS_REG) {
- str.append(StringPrintf(" v%d", insn.vA));
- }
- if (df_attributes & DF_B_IS_REG) {
- str.append(StringPrintf(", v%d", insn.vB));
- } else if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
- str.append(StringPrintf(", (#%d)", insn.vB));
- }
- if (df_attributes & DF_C_IS_REG) {
- str.append(StringPrintf(", v%d", insn.vC));
- } else if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
- str.append(StringPrintf(", (#%d)", insn.vC));
- }
- }
- int length = str.length() + 1;
- ret = static_cast<char*>(NewMem(cu, length, false, kAllocDFInfo));
- strncpy(ret, str.c_str(), length);
- return ret;
-}
-
-static std::string GetSSAName(const CompilationUnit* cu, int ssa_reg)
-{
- return StringPrintf("v%d_%d", SRegToVReg(cu, ssa_reg),
- SRegToSubscript(cu, ssa_reg));
-}
-
-/*
- * Dalvik instruction disassembler with optional SSA printing.
- */
-char* FullDisassembler(CompilationUnit* cu, const MIR* mir)
-{
- std::string str;
- const DecodedInstruction* insn = &mir->dalvikInsn;
- int opcode = insn->opcode;
- int df_attributes = oat_data_flow_attributes[opcode];
- char* ret;
- int length;
-
- if (opcode >= kMirOpFirst) {
- if (opcode == kMirOpPhi) {
- int* incoming = reinterpret_cast<int*>(mir->dalvikInsn.vB);
- str.append(StringPrintf("PHI %s = (%s",
- GetSSAName(cu, mir->ssa_rep->defs[0]).c_str(),
- GetSSAName(cu, mir->ssa_rep->uses[0]).c_str()));
- str.append(StringPrintf(":%d",incoming[0]));
- int i;
- for (i = 1; i < mir->ssa_rep->num_uses; i++) {
- str.append(StringPrintf(", %s:%d",
- GetSSAName(cu, mir->ssa_rep->uses[i]).c_str(),
- incoming[i]));
+ // For invokes-style formats, treat wide regs as a pair of singles
+ bool show_singles = ((dalvik_format == Instruction::k35c) ||
+ (dalvik_format == Instruction::k3rc));
+ if (defs != 0) {
+ str.append(StringPrintf(" %s", GetSSANameWithConst(cu, ssa_rep->defs[0], false).c_str()));
+ if (uses != 0) {
+ str.append(", ");
}
- str.append(")");
- } else if (opcode == kMirOpCheck) {
- str.append("Check ");
- str.append(Instruction::Name(mir->meta.throw_insn->dalvikInsn.opcode));
- } else if (opcode == kMirOpNop) {
- str.append("MirNop");
- } else {
- str.append(StringPrintf("Opcode %#x", opcode));
}
- goto done;
- } else {
- str.append(Instruction::Name(insn->opcode));
- }
-
- /* For branches, decode the instructions to print out the branch targets */
- if (Instruction::FlagsOf(insn->opcode) & Instruction::kBranch) {
- Instruction::Format dalvik_format = Instruction::FormatOf(insn->opcode);
- int delta = 0;
+ for (int i = 0; i < uses; i++) {
+ str.append(
+ StringPrintf(" %s", GetSSANameWithConst(cu, ssa_rep->uses[i], show_singles).c_str()));
+ if (!show_singles && cu->reg_location[i].wide) {
+ // For the listing, skip the high sreg.
+ i++;
+ }
+ if (i != (uses -1)) {
+ str.append(",");
+ }
+ }
switch (dalvik_format) {
- case Instruction::k21t:
- str.append(StringPrintf(" %s, ",
- GetSSAName(cu, mir->ssa_rep->uses[0]).c_str()));
- delta = insn->vB;
+ case Instruction::k11n: // Add one immediate from vB
+ case Instruction::k21s:
+ case Instruction::k31i:
+ case Instruction::k21h:
+ str.append(StringPrintf(", #%d", insn.vB));
break;
- case Instruction::k22t:
- str.append(StringPrintf(" %s, %s, ",
- GetSSAName(cu, mir->ssa_rep->uses[0]).c_str(),
- GetSSAName(cu, mir->ssa_rep->uses[1]).c_str()));
- delta = insn->vC;
+ case Instruction::k51l: // Add one wide immediate
+ str.append(StringPrintf(", #%lld", insn.vB_wide));
break;
- case Instruction::k10t:
- case Instruction::k20t:
- case Instruction::k30t:
- delta = insn->vA;
+ case Instruction::k21c: // One register, one string/type/method index
+ case Instruction::k31c:
+ str.append(StringPrintf(", index #%d", insn.vB));
+ break;
+ case Instruction::k22c: // Two registers, one string/type/method index
+ str.append(StringPrintf(", index #%d", insn.vC));
+ break;
+ case Instruction::k22s: // Add one immediate from vC
+ case Instruction::k22b:
+ str.append(StringPrintf(", #%d", insn.vC));
break;
default:
- LOG(FATAL) << "Unexpected branch format: " << dalvik_format;
+ ; // Nothing left to print
}
- str.append(StringPrintf(" %04x", mir->offset + delta));
- } else if (df_attributes & (DF_FORMAT_35C | DF_FORMAT_3RC)) {
- unsigned int i;
- for (i = 0; i < insn->vA; i++) {
- if (i != 0) str.append(",");
- str.append(" ");
- str.append(GetSSAName(cu, mir->ssa_rep->uses[i]));
- }
- } else {
- int ud_idx;
- if (mir->ssa_rep->num_defs) {
-
- for (ud_idx = 0; ud_idx < mir->ssa_rep->num_defs; ud_idx++) {
- str.append(" ");
- str.append(GetSSAName(cu, mir->ssa_rep->defs[ud_idx]));
- }
- str.append(",");
- }
- if (mir->ssa_rep->num_uses) {
- /* No leading ',' for the first use */
- str.append(" ");
- str.append(GetSSAName(cu, mir->ssa_rep->uses[0]));
- for (ud_idx = 1; ud_idx < mir->ssa_rep->num_uses; ud_idx++) {
- str.append(", ");
- str.append(GetSSAName(cu, mir->ssa_rep->uses[ud_idx]));
- }
- }
- if (static_cast<int>(opcode) < static_cast<int>(kMirOpFirst)) {
- Instruction::Format dalvik_format = Instruction::FormatOf(insn->opcode);
- switch (dalvik_format) {
- case Instruction::k11n: // op vA, #+B
- case Instruction::k21s: // op vAA, #+BBBB
- case Instruction::k21h: // op vAA, #+BBBB00000[00000000]
- case Instruction::k31i: // op vAA, #+BBBBBBBB
- case Instruction::k51l: // op vAA, #+BBBBBBBBBBBBBBBB
- str.append(StringPrintf(" #%#x", insn->vB));
- break;
- case Instruction::k21c: // op vAA, thing@BBBB
- case Instruction::k31c: // op vAA, thing@BBBBBBBB
- str.append(StringPrintf(" @%#x", insn->vB));
- break;
- case Instruction::k22b: // op vAA, vBB, #+CC
- case Instruction::k22s: // op vA, vB, #+CCCC
- str.append(StringPrintf(" #%#x", insn->vC));
- break;
- case Instruction::k22c: // op vA, vB, thing@CCCC
- str.append(StringPrintf(" @%#x", insn->vC));
- break;
- /* No need for special printing */
- default:
- break;
- }
- }
}
-
-done:
- length = str.length() + 1;
- ret = static_cast<char*>(NewMem(cu, length, false, kAllocDFInfo));
- strncpy(ret, str.c_str(), length);
- return ret;
-}
-
-char* GetSSAString(CompilationUnit* cu, SSARepresentation* ssa_rep)
-{
- std::string str;
- char* ret;
- int i;
-
- for (i = 0; i < ssa_rep->num_defs; i++) {
- int ssa_reg = ssa_rep->defs[i];
- str.append(StringPrintf("s%d(v%d_%d) ", ssa_reg,
- SRegToVReg(cu, ssa_reg),
- SRegToSubscript(cu, ssa_reg)));
+ if (nop) {
+ str.append("]--optimized away");
}
-
- if (ssa_rep->num_defs) {
- str.append("<- ");
- }
-
- for (i = 0; i < ssa_rep->num_uses; i++) {
- int ssa_reg = ssa_rep->uses[i];
- str.append(StringPrintf("s%d(v%d_%d) ", ssa_reg, SRegToVReg(cu, ssa_reg),
- SRegToSubscript(cu, ssa_reg)));
- }
-
int length = str.length() + 1;
ret = static_cast<char*>(NewMem(cu, length, false, kAllocDFInfo));
strncpy(ret, str.c_str(), length);
diff --git a/src/compiler/dataflow.h b/src/compiler/dataflow.h
index 28b9a32..38edd36 100644
--- a/src/compiler/dataflow.h
+++ b/src/compiler/dataflow.h
@@ -158,9 +158,7 @@
};
int SRegToVReg(const CompilationUnit* cu, int ssa_reg);
-char* GetDalvikDisassembly(CompilationUnit* cu, const DecodedInstruction& insn, const char* note);
-char* FullDisassembler(CompilationUnit* cu, const MIR* mir);
-char* GetSSAString(CompilationUnit* cu, SSARepresentation* ssa_rep);
+char* GetDalvikDisassembly(CompilationUnit* cu, const MIR* mir);
bool FindLocalLiveIn(CompilationUnit* cu, BasicBlock* bb);
bool DoSSAConversion(CompilationUnit* cu, BasicBlock* bb);
bool DoConstantPropogation(CompilationUnit* cu, BasicBlock* bb);
diff --git a/src/compiler/frontend.cc b/src/compiler/frontend.cc
index cd07dde..d896e5b 100644
--- a/src/compiler/frontend.cc
+++ b/src/compiler/frontend.cc
@@ -113,7 +113,7 @@
* Parse an instruction, return the length of the instruction
*/
static int ParseInsn(CompilationUnit* cu, const uint16_t* code_ptr,
- DecodedInstruction* decoded_instruction, bool verbose)
+ DecodedInstruction* decoded_instruction)
{
// Don't parse instruction data
if (!ContentIsInsn(code_ptr)) {
@@ -123,12 +123,6 @@
const Instruction* instruction = Instruction::At(code_ptr);
*decoded_instruction = DecodedInstruction(instruction);
- if (verbose) {
- char* decoded_string = GetDalvikDisassembly(cu, *decoded_instruction,
- NULL);
- LOG(INFO) << code_ptr << ": 0x" << std::hex << static_cast<int>(decoded_instruction->opcode)
- << " " << decoded_string;
- }
return instruction->SizeInCodeUnits();
}
@@ -311,7 +305,7 @@
bb->first_mir_insn ? " | " : " ");
for (mir = bb->first_mir_insn; mir; mir = mir->next) {
fprintf(file, " {%04x %s\\l}%s\\\n", mir->offset,
- mir->ssa_rep ? FullDisassembler(cu, mir) :
+ mir->ssa_rep ? GetDalvikDisassembly(cu, mir) :
Instruction::Name(mir->dalvikInsn.opcode),
mir->next ? " | " : " ");
}
@@ -932,7 +926,7 @@
while (code_ptr < code_end) {
MIR *insn = static_cast<MIR *>(NewMem(cu.get(), sizeof(MIR), true, kAllocMIR));
insn->offset = cur_offset;
- int width = ParseInsn(cu.get(), code_ptr, &insn->dalvikInsn, false);
+ int width = ParseInsn(cu.get(), code_ptr, &insn->dalvikInsn);
insn->width = width;
Instruction::Code opcode = insn->dalvikInsn.opcode;
if (cu->opcode_count != NULL) {
diff --git a/src/compiler/ralloc.cc b/src/compiler/ralloc.cc
index 8813193..2038e19 100644
--- a/src/compiler/ralloc.cc
+++ b/src/compiler/ralloc.cc
@@ -68,26 +68,6 @@
return change;
}
-static bool RemapNames(CompilationUnit* cu, BasicBlock* bb)
-{
- if (bb->block_type != kDalvikByteCode && bb->block_type != kEntryBlock &&
- bb->block_type != kExitBlock)
- return false;
-
- for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
- SSARepresentation *ssa_rep = mir->ssa_rep;
- if (ssa_rep) {
- for (int i = 0; i < ssa_rep->num_uses; i++) {
- ssa_rep->uses[i] = cu->phi_alias_map[ssa_rep->uses[i]];
- }
- for (int i = 0; i < ssa_rep->num_defs; i++) {
- ssa_rep->defs[i] = cu->phi_alias_map[ssa_rep->defs[i]];
- }
- }
- }
- return false;
-}
-
/*
* Infer types and sizes. We don't need to track change on sizes,
* as it doesn't propagate. We're guaranteed at least one pass through
@@ -368,10 +348,11 @@
{
Codegen* cg = cu->cg.get();
for (int i = 0; i < count; i++) {
- LOG(INFO) << StringPrintf("Loc[%02d] : %s, %c %c %c %c %c %c%d %c%d S%d",
+ LOG(INFO) << StringPrintf("Loc[%02d] : %s, %c %c %c %c %c %c %c%d %c%d S%d",
table[i].orig_sreg, storage_name[table[i].location],
table[i].wide ? 'W' : 'N', table[i].defined ? 'D' : 'U',
table[i].fp ? 'F' : table[i].ref ? 'R' :'C',
+ table[i].is_const ? 'c' : 'n',
table[i].high_word ? 'H' : 'L', table[i].home ? 'h' : 't',
cg->IsFpReg(table[i].low_reg) ? 's' : 'r',
table[i].low_reg & cg->FpRegMask(),
@@ -480,13 +461,6 @@
}
}
- if (!cu->gen_bitcode) {
- /* Remap names */
- DataFlowAnalysisDispatcher(cu, RemapNames,
- kPreOrderDFSTraversal,
- false /* is_iterative */);
- }
-
/* Do type & size inference pass */
DataFlowAnalysisDispatcher(cu, InferTypeAndSize,
kPreOrderDFSTraversal,
diff --git a/src/compiler/ssa_transformation.cc b/src/compiler/ssa_transformation.cc
index 2a3ceca..5d787c4 100644
--- a/src/compiler/ssa_transformation.cc
+++ b/src/compiler/ssa_transformation.cc
@@ -783,8 +783,6 @@
phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpPhi);
phi->dalvikInsn.vA = dalvik_reg;
phi->offset = phi_bb->start_offset;
- phi->meta.phi_next = cu->phi_list;
- cu->phi_list = phi;
PrependMIR(phi_bb, phi);
}
}