Rework arm64 register codes and fix Arm64ManagedRegister tests.
Change-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec
diff --git a/compiler/utils/arm64/assembler_arm64.h b/compiler/utils/arm64/assembler_arm64.h
index ef83334..cf831f8 100644
--- a/compiler/utils/arm64/assembler_arm64.h
+++ b/compiler/utils/arm64/assembler_arm64.h
@@ -183,6 +183,11 @@
}
static vixl::Register reg_w(int code) {
+ if (code == WSP) {
+ return vixl::wsp;
+ } else if (code == WZR) {
+ return vixl::wzr;
+ }
return vixl::Register::WRegFromCode(code);
}
diff --git a/compiler/utils/arm64/managed_register_arm64.cc b/compiler/utils/arm64/managed_register_arm64.cc
index 8977313..db040e3 100644
--- a/compiler/utils/arm64/managed_register_arm64.cc
+++ b/compiler/utils/arm64/managed_register_arm64.cc
@@ -42,22 +42,14 @@
// 63__________0 D[n]
bool Arm64ManagedRegister::Overlaps(const Arm64ManagedRegister& other) const {
if (IsNoRegister() || other.IsNoRegister()) return false;
- if ((IsGPRegister() && other.IsGPRegister()) ||
- (IsFPRegister() && other.IsFPRegister())) {
- return (RegNo() == other.RegNo());
- }
- return false;
+ return (IsGPRegister() == other.IsGPRegister()) && (RegNo() == other.RegNo());
}
int Arm64ManagedRegister::RegNo() const {
CHECK(!IsNoRegister());
int no;
if (IsCoreRegister()) {
- if (IsZeroRegister()) {
- no = static_cast<int>(X31);
- } else {
- no = static_cast<int>(AsCoreRegister());
- }
+ no = static_cast<int>(AsCoreRegister());
} else if (IsWRegister()) {
no = static_cast<int>(AsWRegister());
} else if (IsDRegister()) {
diff --git a/compiler/utils/arm64/managed_register_arm64.h b/compiler/utils/arm64/managed_register_arm64.h
index a0f520f..2c52504 100644
--- a/compiler/utils/arm64/managed_register_arm64.h
+++ b/compiler/utils/arm64/managed_register_arm64.h
@@ -78,7 +78,7 @@
WRegister AsOverlappingCoreRegisterLow() const {
CHECK(IsValidManagedRegister());
- if (IsZeroRegister()) return W31;
+ if (IsZeroRegister()) return WZR;
return static_cast<WRegister>(AsCoreRegister());
}
diff --git a/compiler/utils/arm64/managed_register_arm64_test.cc b/compiler/utils/arm64/managed_register_arm64_test.cc
index f149f1b..f1a5494 100644
--- a/compiler/utils/arm64/managed_register_arm64_test.cc
+++ b/compiler/utils/arm64/managed_register_arm64_test.cc
@@ -97,7 +97,7 @@
EXPECT_TRUE(!reg.IsWRegister());
EXPECT_TRUE(!reg.IsDRegister());
EXPECT_TRUE(!reg.IsSRegister());
- EXPECT_TRUE(reg.Overlaps(wreg));
+ EXPECT_TRUE(!reg.Overlaps(wreg));
EXPECT_EQ(SP, reg.AsCoreRegister());
}
@@ -160,8 +160,7 @@
EXPECT_TRUE(reg.IsWRegister());
EXPECT_TRUE(!reg.IsDRegister());
EXPECT_TRUE(!reg.IsSRegister());
- EXPECT_TRUE(reg.Overlaps(xreg));
- EXPECT_EQ(W31, reg.AsWRegister());
+ EXPECT_TRUE(!reg.Overlaps(xreg));
}
// D Register test.
@@ -294,20 +293,9 @@
EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D1)));
EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1)));
- Arm64ManagedRegister reg_X31 = Arm64ManagedRegister::FromCoreRegister(X31);
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::NoRegister()));
- EXPECT_TRUE(reg_X31.Equals(Arm64ManagedRegister::FromCoreRegister(SP)));
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromWRegister(W31)));
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromWRegister(WZR)));
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromSRegister(S0)));
- EXPECT_TRUE(!reg_X31.Equals(Arm64ManagedRegister::FromDRegister(D0)));
-
Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromCoreRegister(SP);
EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::NoRegister()));
- EXPECT_TRUE(reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(X31)));
EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(XZR)));
- EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromWRegister(W31)));
EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0)));
EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromDRegister(D0)));
@@ -452,17 +440,13 @@
reg = Arm64ManagedRegister::FromCoreRegister(XZR);
reg_o = Arm64ManagedRegister::FromWRegister(WZR);
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W19)));
- EXPECT_EQ(X31, reg_o.AsOverlappingWRegisterCore());
- EXPECT_EQ(SP, reg_o.AsOverlappingWRegisterCore());
- EXPECT_NE(XZR, reg_o.AsOverlappingWRegisterCore());
- EXPECT_EQ(W31, reg.AsOverlappingCoreRegisterLow());
+ EXPECT_NE(SP, reg_o.AsOverlappingWRegisterCore());
+ EXPECT_EQ(XZR, reg_o.AsOverlappingWRegisterCore());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
@@ -476,15 +460,11 @@
reg = Arm64ManagedRegister::FromCoreRegister(SP);
reg_o = Arm64ManagedRegister::FromWRegister(WZR);
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
- EXPECT_EQ(X31, reg_o.AsOverlappingWRegisterCore());
- EXPECT_EQ(W31, reg.AsOverlappingCoreRegisterLow());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2)));
@@ -503,7 +483,7 @@
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30)));
EXPECT_EQ(W1, reg_o.AsOverlappingCoreRegisterLow());
EXPECT_EQ(X1, reg.AsOverlappingWRegisterCore());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
@@ -524,7 +504,7 @@
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30)));
EXPECT_EQ(W21, reg_o.AsOverlappingCoreRegisterLow());
EXPECT_EQ(X21, reg.AsOverlappingWRegisterCore());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
@@ -541,13 +521,13 @@
reg = Arm64ManagedRegister::FromSRegister(S1);
reg_o = Arm64ManagedRegister::FromDRegister(D1);
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30)));
EXPECT_EQ(S1, reg_o.AsOverlappingDRegisterLow());
EXPECT_EQ(D1, reg.AsOverlappingSRegisterD());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
@@ -564,13 +544,13 @@
reg = Arm64ManagedRegister::FromSRegister(S15);
reg_o = Arm64ManagedRegister::FromDRegister(D15);
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30)));
EXPECT_EQ(S15, reg_o.AsOverlappingDRegisterLow());
EXPECT_EQ(D15, reg.AsOverlappingSRegisterD());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
@@ -587,13 +567,13 @@
reg = Arm64ManagedRegister::FromDRegister(D15);
reg_o = Arm64ManagedRegister::FromSRegister(S15);
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1)));
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12)));
- EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W31)));
+ EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30)));
EXPECT_EQ(S15, reg.AsOverlappingDRegisterLow());
EXPECT_EQ(D15, reg_o.AsOverlappingSRegisterD());
EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0)));
@@ -642,9 +622,6 @@
EXPECT_TRUE(vixl::x28.Is(Arm64Assembler::reg_x(X28)));
EXPECT_TRUE(vixl::x29.Is(Arm64Assembler::reg_x(X29)));
EXPECT_TRUE(vixl::x30.Is(Arm64Assembler::reg_x(X30)));
- // FIXME: Take a look here.
- EXPECT_TRUE(vixl::sp.Is(Arm64Assembler::reg_x(X31)));
- EXPECT_TRUE(!vixl::x31.Is(Arm64Assembler::reg_x(X31)));
EXPECT_TRUE(vixl::x18.Is(Arm64Assembler::reg_x(TR)));
EXPECT_TRUE(vixl::ip0.Is(Arm64Assembler::reg_x(IP0)));
@@ -686,8 +663,9 @@
EXPECT_TRUE(vixl::w28.Is(Arm64Assembler::reg_w(W28)));
EXPECT_TRUE(vixl::w29.Is(Arm64Assembler::reg_w(W29)));
EXPECT_TRUE(vixl::w30.Is(Arm64Assembler::reg_w(W30)));
- EXPECT_TRUE(vixl::w31.Is(Arm64Assembler::reg_w(W31)));
+ EXPECT_TRUE(vixl::w31.Is(Arm64Assembler::reg_w(WZR)));
EXPECT_TRUE(vixl::wzr.Is(Arm64Assembler::reg_w(WZR)));
+ EXPECT_TRUE(vixl::wsp.Is(Arm64Assembler::reg_w(WSP)));
// D Registers.
EXPECT_TRUE(vixl::d0.Is(Arm64Assembler::reg_d(D0)));
diff --git a/runtime/arch/arm64/context_arm64.cc b/runtime/arch/arm64/context_arm64.cc
index 3eb92c8..0614f1a 100644
--- a/runtime/arch/arm64/context_arm64.cc
+++ b/runtime/arch/arm64/context_arm64.cc
@@ -75,6 +75,7 @@
bool Arm64Context::SetGPR(uint32_t reg, uintptr_t value) {
DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
+ DCHECK_NE(reg, static_cast<uint32_t>(XZR));
DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
if (gprs_[reg] != nullptr) {
*gprs_[reg] = value;
@@ -146,11 +147,13 @@
extern "C" void art_quick_do_long_jump(uint64_t*, uint64_t*);
void Arm64Context::DoLongJump() {
- uint64_t gprs[32];
+ uint64_t gprs[kNumberOfCoreRegisters];
uint64_t fprs[kNumberOfDRegisters];
- // Do not use kNumberOfCoreRegisters, as this is with the distinction of SP and XZR
- for (size_t i = 0; i < 32; ++i) {
+ // The long jump routine called below expects to find the value for SP at index 31.
+ DCHECK_EQ(SP, 31);
+
+ for (size_t i = 0; i < kNumberOfCoreRegisters; ++i) {
gprs[i] = gprs_[i] != nullptr ? *gprs_[i] : Arm64Context::kBadGprBase + i;
}
for (size_t i = 0; i < kNumberOfDRegisters; ++i) {
diff --git a/runtime/arch/arm64/registers_arm64.cc b/runtime/arch/arm64/registers_arm64.cc
index 87901e3..3ed6eff 100644
--- a/runtime/arch/arm64/registers_arm64.cc
+++ b/runtime/arch/arm64/registers_arm64.cc
@@ -32,11 +32,11 @@
"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9",
"w10", "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19",
"w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29",
- "w30", "wsp", "wxr"
+ "w30", "wsp", "wzr"
};
std::ostream& operator<<(std::ostream& os, const Register& rhs) {
- if (rhs >= X0 && rhs <= XZR) {
+ if (rhs >= X0 && rhs < kNumberOfCoreRegisters) {
os << kRegisterNames[rhs];
} else {
os << "XRegister[" << static_cast<int>(rhs) << "]";
@@ -45,7 +45,7 @@
}
std::ostream& operator<<(std::ostream& os, const WRegister& rhs) {
- if (rhs >= W0 && rhs <= WZR) {
+ if (rhs >= W0 && rhs < kNumberOfWRegisters) {
os << kWRegisterNames[rhs];
} else {
os << "WRegister[" << static_cast<int>(rhs) << "]";
diff --git a/runtime/arch/arm64/registers_arm64.h b/runtime/arch/arm64/registers_arm64.h
index 9ccab70..5bf8242 100644
--- a/runtime/arch/arm64/registers_arm64.h
+++ b/runtime/arch/arm64/registers_arm64.h
@@ -55,17 +55,17 @@
X28 = 28,
X29 = 29,
X30 = 30,
- X31 = 31,
- TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg)
- ETR = 21, // ART Thread Register - External Calls (Callee Saved Reg)
- IP0 = 16, // Used as scratch by VIXL.
- IP1 = 17, // Used as scratch by ART JNI Assembler.
- FP = 29,
- LR = 30,
- SP = 31, // SP is X31 and overlaps with XRZ but we encode it as a
- // special register, due to the different instruction semantics.
- XZR = 32,
+ SP = 31, // SP and XZR are encoded in instructions using the register
+ XZR = 32, // code `31`, the context deciding which is used. We use a
+ // different enum value to distinguish between the two.
kNumberOfCoreRegisters = 33,
+ // Aliases.
+ TR = X18, // ART Thread Register - Managed Runtime (Caller Saved Reg)
+ ETR = X21, // ART Thread Register - External Calls (Callee Saved Reg)
+ IP0 = X16, // Used as scratch by VIXL.
+ IP1 = X17, // Used as scratch by ART JNI Assembler.
+ FP = X29,
+ LR = X30,
kNoRegister = -1,
};
std::ostream& operator<<(std::ostream& os, const Register& rhs);
@@ -103,9 +103,9 @@
W28 = 28,
W29 = 29,
W30 = 30,
- W31 = 31,
- WZR = 31,
- kNumberOfWRegisters = 32,
+ WSP = 31,
+ WZR = 32,
+ kNumberOfWRegisters = 33,
kNoWRegister = -1,
};
std::ostream& operator<<(std::ostream& os, const WRegister& rhs);