tree 8cafd7692046b4f8c95fb8e6a713755f9eeddeec
parent d3236731ca6145e0723ce8aab8c6ff634ab021c2
author buzbee <buzbee@google.com> 1400021947 -0700
committer buzbee <buzbee@google.com> 1400674644 -0700

64-bit temp register support.

Add a 64-bit temp register allocation path.  The recent physical
register handling rework supports multiple views of the same
physical register (or, such as for Arm's float/double regs,
different parts of the same physical register).

This CL adds a 64-bit core register view for 64-bit targets. In
short, each core register will have a 64-bit name, and a 32-bit
name.  The different views will be kept in separate register pools,
but aliasing will be tracked.  The core temp register allocation
routines will be largely identical - except for 32-bit targets,
which will continue to use pairs of 32-bit core registers for holding
long values.

Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053