ART: Vectorization opcode implementation fixes
This patch fixes the implementation of the x86 vectorization opcodes.
Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Signed-off-by: Philbert Lin <philbert.lin@intel.com>
diff --git a/compiler/dex/backend.h b/compiler/dex/backend.h
index 1f24849..cab3427 100644
--- a/compiler/dex/backend.h
+++ b/compiler/dex/backend.h
@@ -38,14 +38,15 @@
/*
* Return the number of reservable vector registers supported
- * @param fp_used ‘true’ if floating point computations will be
- * executed while vector registers are reserved.
+ * @param long_or_fp ‘true’ if floating point computations will be
+ * executed or the operations will be long type while vector
+ * registers are reserved.
* @return the number of vector registers that are available
* @note The backend should ensure that sufficient vector registers
* are held back to generate scalar code without exhausting vector
* registers, if scalar code also uses the vector registers.
*/
- virtual int NumReservableVectorRegisters(bool fp_used) { return 0; }
+ virtual int NumReservableVectorRegisters(bool long_or_fp) { return 0; }
protected:
explicit Backend(ArenaAllocator* arena) : arena_(arena) {}