ART: Implement support for instruction inlining
Optimizing HIR contains 'non-materialized' instructions which are
emitted at their use sites rather than their defining sites. This
was not properly handled by the liveness analysis which did not
adjust the use positions of the inputs of such instructions.
Despite the analysis being incorrect, the current use cases never
produce incorrect code.
This patch generalizes the concept of inlined instructions and
updates liveness analysis to set the compute use positions correctly.
Change-Id: Id703c154b20ab861241ae5c715a150385d3ff621
diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index c0e3959..788c3a6 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -2510,13 +2510,13 @@
locations->SetInAt(1, ARM64EncodableConstantOrRegister(instruction->InputAt(1), instruction));
}
- if (instruction->NeedsMaterialization()) {
+ if (!instruction->IsEmittedAtUseSite()) {
locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
}
}
void InstructionCodeGeneratorARM64::HandleCondition(HCondition* instruction) {
- if (!instruction->NeedsMaterialization()) {
+ if (instruction->IsEmittedAtUseSite()) {
return;
}