commit bff2465abb4b0c097623c82f18a1307ea890bff1
author buzbee <buzbee@google.com> Sun May 06 16:22:05 2012 -0700
committer buzbee <buzbee@google.com> Sun May 06 16:30:57 2012 -0700
tree aee1448eec34b9e5bf8c41fc9f83559ca5f49fd7
parent d0379748bd05b949a8e2193b44ddf4950f9569a8

[Compiler] Add object ref discovery

Previously, the compiler ran a type inference pass to identify floating
point uses for register allocation.  The grand plan involves moving
all type inference into the Art compiler driver (using the results from
verification).  As a short-term workaround, this CL adds object reference
discovery to the type inference pass.  This is needed for LLVM-IR generation.

Change-Id: I655806264181bfd26ab9340582a02c657cd3f678

src/compiler/codegen/x86/ArchFactory.cc

diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc
index dc13238..1d3893a 100644
--- a/src/compiler/codegen/x86/ArchFactory.cc
+++ b/src/compiler/codegen/x86/ArchFactory.cc
@@ -34,7 +34,7 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAdd, r0, r2);  // r0 = r0 + r2
   opRegReg(cUnit, kOpAdc, r1, r3);  // r1 = r1 + r3 + CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -49,7 +49,7 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpSub, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpSbc, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -64,7 +64,7 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpAnd, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpAnd, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -79,7 +79,7 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpOr, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpOr, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -94,7 +94,7 @@
   // Compute (r1:r0) = (r1:r0) + (r2:r3)
   opRegReg(cUnit, kOpXor, r0, r2);  // r0 = r0 - r2
   opRegReg(cUnit, kOpXor, r1, r3);  // r1 = r1 - r3 - CF
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }
@@ -109,7 +109,7 @@
   opRegReg(cUnit, kOpNeg, r0, r0);  // r0 = -r0
   opRegImm(cUnit, kOpAdc, r1, 0);   // r1 = r1 + CF
   opRegReg(cUnit, kOpNeg, r1, r1);  // r1 = -r1
-  RegLocation rlResult = {kLocPhysReg, 1, 0, 0,  0, 0, 1, r0, r1, INVALID_SREG};
+  RegLocation rlResult = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG};
   storeValueWide(cUnit, rlDest, rlResult);
   return false;
 }