Various optimization fixes
Multiple problems surfaced when register promotion was enabled. This
CL takes care of a few, but more remain. The main problems dealt with
here are related to not having data types handy on invokes. Solved by
intepreting the shorty of the target and updating the operand names
appropriately.
The other problem was a little nastier. The codgen infrastructure wasn't
expecting wide results to overlap source operands (for example:
add-long (v0,v1) = (v1,v2) + (v3,v4)
In the old world, the result pair would start with a fresh name
and temps. In the new world, though, the register promotion mechanism
retains the mappings. Not a difficult problem to solve, but I'll
need to very carefully examine the existing long op generators to
make sure they can handle overlaps.
Change-Id: I019607620f7a78cadc9e7c57f247806d0a68243d
diff --git a/src/compiler/CompilerIR.h b/src/compiler/CompilerIR.h
index 5a38c47..934139b 100644
--- a/src/compiler/CompilerIR.h
+++ b/src/compiler/CompilerIR.h
@@ -120,6 +120,8 @@
const Method* calleeMethod;
// Used by the inlined invoke to find the class and method pointers
CallsiteInfo* callsiteInfo;
+ // Used to quickly locate all Phi opcodes
+ struct MIR* phiNext;
} meta;
} MIR;
@@ -223,6 +225,8 @@
int* SSALastDefs; // length == method->registersSize
ArenaBitVector* isConstantV; // length == numSSAReg
int* constantValues; // length == numSSAReg
+ int* phiAliasMap; // length == numSSAReg
+ MIR* phiList;
/* Map SSA names to location */
RegLocation* regLocation;