C++'ification of Quick compiler's casts
o Eliminate old useless LIR casts.
o Replace remaining C-style casts with new C++ versions.
o Unified instruction encoding enum
o Expand usage of the auto-generated ostream helpers for enum LOG messages.
o Replaced all usages of intptr_t with uintptr_t.
o Fixed bug in removeRedundantBranches, and moved to common code
Change-Id: I53211c0de1be913f958c8fde915296ac08345b7e
diff --git a/src/compiler/codegen/mips/assemble_mips.cc b/src/compiler/codegen/mips/assemble_mips.cc
index 1fa3a6b..79259fb 100644
--- a/src/compiler/codegen/mips/assemble_mips.cc
+++ b/src/compiler/codegen/mips/assemble_mips.cc
@@ -479,7 +479,7 @@
case kMipsBltz: opcode = kMipsBgez; break;
case kMipsBnez: opcode = kMipsBeqz; break;
default:
- LOG(FATAL) << "Unexpected branch kind " << (int)opcode;
+ LOG(FATAL) << "Unexpected branch kind " << opcode;
}
LIR* hopTarget = NULL;
if (!unconditional) {
@@ -492,11 +492,11 @@
oatInsertLIRBefore(lir, currPC);
LIR* anchor = rawLIR(cUnit, dalvikOffset, kPseudoTargetLabel);
LIR* deltaHi = rawLIR(cUnit, dalvikOffset, kMipsDeltaHi, r_AT, 0,
- (uintptr_t)anchor, 0, 0, lir->target);
+ reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
oatInsertLIRBefore(lir, deltaHi);
oatInsertLIRBefore(lir, anchor);
LIR* deltaLo = rawLIR(cUnit, dalvikOffset, kMipsDeltaLo, r_AT, 0,
- (uintptr_t)anchor, 0, 0, lir->target);
+ reinterpret_cast<uintptr_t>(anchor), 0, 0, lir->target);
oatInsertLIRBefore(lir, deltaLo);
LIR* addu = rawLIR(cUnit, dalvikOffset, kMipsAddu, r_AT, r_AT, r_RA);
oatInsertLIRBefore(lir, addu);
@@ -515,12 +515,12 @@
* sequence or request that the trace be shortened and retried.
*/
AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
- intptr_t startAddr)
+ uintptr_t startAddr)
{
LIR *lir;
AssemblerStatus res = kSuccess; // Assume success
- for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
+ for (lir = cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
if (lir->opcode < 0) {
continue;
}
@@ -542,8 +542,8 @@
* and is found in lir->target. If operands[3] is non-NULL,
* then it is a Switch/Data table.
*/
- int offset1 = ((LIR*)lir->operands[2])->offset;
- SwitchTable *tabRec = (SwitchTable*)lir->operands[3];
+ int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
+ SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
int offset2 = tabRec ? tabRec->offset : lir->target->offset;
int delta = offset2 - offset1;
if ((delta & 0xffff) == delta && ((delta & 0x8000) == 0)) {
@@ -555,35 +555,35 @@
rawLIR(cUnit, lir->dalvikOffset, kMipsDeltaHi,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- oatInsertLIRBefore((LIR*)lir, (LIR*)newDeltaHi);
+ oatInsertLIRBefore(lir, newDeltaHi);
LIR *newDeltaLo =
rawLIR(cUnit, lir->dalvikOffset, kMipsDeltaLo,
lir->operands[0], 0, lir->operands[2],
lir->operands[3], 0, lir->target);
- oatInsertLIRBefore((LIR*)lir, (LIR*)newDeltaLo);
+ oatInsertLIRBefore(lir, newDeltaLo);
LIR *newAddu =
rawLIR(cUnit, lir->dalvikOffset, kMipsAddu,
lir->operands[0], lir->operands[0], r_RA);
- oatInsertLIRBefore((LIR*)lir, (LIR*)newAddu);
+ oatInsertLIRBefore(lir, newAddu);
lir->flags.isNop = true;
res = kRetryAll;
}
} else if (lir->opcode == kMipsDeltaLo) {
- int offset1 = ((LIR*)lir->operands[2])->offset;
- SwitchTable *tabRec = (SwitchTable*)lir->operands[3];
+ int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
+ SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
int offset2 = tabRec ? tabRec->offset : lir->target->offset;
int delta = offset2 - offset1;
lir->operands[1] = delta & 0xffff;
} else if (lir->opcode == kMipsDeltaHi) {
- int offset1 = ((LIR*)lir->operands[2])->offset;
- SwitchTable *tabRec = (SwitchTable*)lir->operands[3];
+ int offset1 = (reinterpret_cast<LIR*>(lir->operands[2]))->offset;
+ SwitchTable *tabRec = reinterpret_cast<SwitchTable*>(lir->operands[3]);
int offset2 = tabRec ? tabRec->offset : lir->target->offset;
int delta = offset2 - offset1;
lir->operands[1] = (delta >> 16) & 0xffff;
} else if (lir->opcode == kMipsB || lir->opcode == kMipsBal) {
- LIR *targetLIR = (LIR *) lir->target;
- intptr_t pc = lir->offset + 4;
- intptr_t target = targetLIR->offset;
+ LIR *targetLIR = lir->target;
+ uintptr_t pc = lir->offset + 4;
+ uintptr_t target = targetLIR->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
@@ -595,9 +595,9 @@
lir->operands[0] = delta >> 2;
}
} else if (lir->opcode >= kMipsBeqz && lir->opcode <= kMipsBnez) {
- LIR *targetLIR = (LIR *) lir->target;
- intptr_t pc = lir->offset + 4;
- intptr_t target = targetLIR->offset;
+ LIR *targetLIR = lir->target;
+ uintptr_t pc = lir->offset + 4;
+ uintptr_t target = targetLIR->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
@@ -609,9 +609,9 @@
lir->operands[1] = delta >> 2;
}
} else if (lir->opcode == kMipsBeq || lir->opcode == kMipsBne) {
- LIR *targetLIR = (LIR *) lir->target;
- intptr_t pc = lir->offset + 4;
- intptr_t target = targetLIR->offset;
+ LIR *targetLIR = lir->target;
+ uintptr_t pc = lir->offset + 4;
+ uintptr_t target = targetLIR->offset;
int delta = target - pc;
if (delta & 0x3) {
LOG(FATAL) << "PC-rel offset not multiple of 4: " << delta;
@@ -623,8 +623,8 @@
lir->operands[2] = delta >> 2;
}
} else if (lir->opcode == kMipsJal) {
- intptr_t curPC = (startAddr + lir->offset + 4) & ~3;
- intptr_t target = lir->operands[0];
+ uintptr_t curPC = (startAddr + lir->offset + 4) & ~3;
+ uintptr_t target = lir->operands[0];
/* ensure PC-region branch can be used */
DCHECK_EQ((curPC & 0xF0000000), (target & 0xF0000000));
if (target & 0x3) {
@@ -632,12 +632,12 @@
}
lir->operands[0] = target >> 2;
} else if (lir->opcode == kMipsLahi) { /* ld address hi (via lui) */
- LIR *targetLIR = (LIR *) lir->target;
- intptr_t target = startAddr + targetLIR->offset;
+ LIR *targetLIR = lir->target;
+ uintptr_t target = startAddr + targetLIR->offset;
lir->operands[1] = target >> 16;
} else if (lir->opcode == kMipsLalo) { /* ld address lo (via ori) */
- LIR *targetLIR = (LIR *) lir->target;
- intptr_t target = startAddr + targetLIR->offset;
+ LIR *targetLIR = lir->target;
+ uintptr_t target = startAddr + targetLIR->offset;
lir->operands[2] = lir->operands[2] + target;
}
}
@@ -689,8 +689,7 @@
bits |= value;
break;
default:
- LOG(FATAL) << "Bad encoder format: "
- << (int)encoder->fieldLoc[i].kind;
+ LOG(FATAL) << "Bad encoder format: " << encoder->fieldLoc[i].kind;
}
}
// We only support little-endian MIPS.
@@ -724,9 +723,7 @@
LIR* mipsLIR;
int offset = 0;
- for (mipsLIR = (LIR *) cUnit->firstLIRInsn;
- mipsLIR;
- mipsLIR = NEXT_LIR(mipsLIR)) {
+ for (mipsLIR = cUnit->firstLIRInsn; mipsLIR; mipsLIR = NEXT_LIR(mipsLIR)) {
mipsLIR->offset = offset;
if (mipsLIR->opcode >= 0) {
if (!mipsLIR->flags.isNop) {
diff --git a/src/compiler/codegen/mips/call_mips.cc b/src/compiler/codegen/mips/call_mips.cc
index bf67b42..1db4eee 100644
--- a/src/compiler/codegen/mips/call_mips.cc
+++ b/src/compiler/codegen/mips/call_mips.cc
@@ -65,14 +65,14 @@
dumpSparseSwitchTable(table);
}
// Add the table to the list - we'll process it later
- SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
- true, kAllocData);
+ SwitchTable *tabRec =
+ static_cast<SwitchTable*>(oatNew(cUnit, sizeof(SwitchTable), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
int elements = table[1];
- tabRec->targets = (LIR* *)oatNew(cUnit, elements * sizeof(LIR*), true,
- kAllocLIR);
- oatInsertGrowableList(cUnit, &cUnit->switchTables, (intptr_t)tabRec);
+ tabRec->targets =
+ static_cast<LIR**>(oatNew(cUnit, elements * sizeof(LIR*), true, kAllocLIR));
+ oatInsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
// The table is composed of 8-byte key/disp pairs
int byteSize = elements * 8;
@@ -100,7 +100,8 @@
// Remember base label so offsets can be computed later
tabRec->anchor = baseLabel;
int rBase = oatAllocTemp(cUnit);
- newLIR4(cUnit, kMipsDelta, rBase, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
+ newLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ reinterpret_cast<uintptr_t>(tabRec));
opRegRegReg(cUnit, kOpAdd, rEnd, rEnd, rBase);
// Grab switch test value
@@ -144,14 +145,13 @@
dumpPackedSwitchTable(table);
}
// Add the table to the list - we'll process it later
- SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
- true, kAllocData);
+ SwitchTable *tabRec =
+ static_cast<SwitchTable*>(oatNew(cUnit, sizeof(SwitchTable), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
- tabRec->targets = (LIR* *)oatNew(cUnit, size * sizeof(LIR*), true,
- kAllocLIR);
- oatInsertGrowableList(cUnit, &cUnit->switchTables, (intptr_t)tabRec);
+ tabRec->targets = static_cast<LIR**>(oatNew(cUnit, size * sizeof(LIR*), true, kAllocLIR));
+ oatInsertGrowableList(cUnit, &cUnit->switchTables, reinterpret_cast<uintptr_t>(tabRec));
// Get the switch value
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
@@ -195,7 +195,8 @@
// Materialize the table base pointer
int rBase = oatAllocTemp(cUnit);
- newLIR4(cUnit, kMipsDelta, rBase, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
+ newLIR4(cUnit, kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ reinterpret_cast<uintptr_t>(tabRec));
// Load the displacement from the switch table
int rDisp = oatAllocTemp(cUnit);
@@ -207,7 +208,7 @@
/* branchOver target here */
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = (LIR*)target;
+ branchOver->target = target;
}
/*
@@ -225,15 +226,15 @@
{
const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
- FillArrayData *tabRec = (FillArrayData *)
- oatNew(cUnit, sizeof(FillArrayData), true, kAllocData);
+ FillArrayData *tabRec =
+ reinterpret_cast<FillArrayData*>(oatNew(cUnit, sizeof(FillArrayData), true, kAllocData));
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
uint16_t width = tabRec->table[1];
uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
tabRec->size = (size * width) + 8;
- oatInsertGrowableList(cUnit, &cUnit->fillArrayData, (intptr_t)tabRec);
+ oatInsertGrowableList(cUnit, &cUnit->fillArrayData, reinterpret_cast<uintptr_t>(tabRec));
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
@@ -251,7 +252,8 @@
LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
// Materialize a pointer to the fill data image
- newLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
+ newLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, reinterpret_cast<uintptr_t>(baseLabel),
+ reinterpret_cast<uintptr_t>(tabRec));
// And go...
oatClobberCalleeSave(cUnit);
@@ -304,7 +306,7 @@
storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
- branchOver->target = (LIR*)target;
+ branchOver->target = target;
oatFreeTemp(cUnit, regCardBase);
oatFreeTemp(cUnit, regCardNo);
}
@@ -328,7 +330,7 @@
* a leaf *and* our frame size < fudge factor.
*/
bool skipOverflowCheck = ((cUnit->attrs & METHOD_IS_LEAF) &&
- ((size_t)cUnit->frameSize < Thread::kStackOverflowReservedBytes));
+ (static_cast<size_t>(cUnit->frameSize) < Thread::kStackOverflowReservedBytes));
newLIR0(cUnit, kPseudoMethodEntry);
int checkReg = oatAllocTemp(cUnit);
int newSP = oatAllocTemp(cUnit);
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index 5ee5de4..1954824 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -57,8 +57,7 @@
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR3(cUnit, (MipsOpCode)op, rlResult.lowReg, rlSrc1.lowReg,
- rlSrc2.lowReg);
+ newLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
storeValue(cUnit, rlDest, rlResult);
return false;
@@ -106,8 +105,7 @@
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
DCHECK(rlDest.wide);
DCHECK(rlResult.wide);
- newLIR3(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
- s2d(rlSrc1.lowReg, rlSrc1.highReg),
+ newLIR3(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), s2d(rlSrc1.lowReg, rlSrc1.highReg),
s2d(rlSrc2.lowReg, rlSrc2.highReg));
storeValueWide(cUnit, rlDest, rlResult);
return false;
@@ -155,12 +153,11 @@
}
if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
- srcReg);
+ newLIR2(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, (MipsOpCode)op, rlResult.lowReg, srcReg);
+ newLIR2(cUnit, op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
}
return false;
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 0e1ae62..82ac547 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -54,7 +54,7 @@
oatFreeTemp(cUnit, t0);
oatFreeTemp(cUnit, t1);
LIR* target = newLIR0(cUnit, kPseudoTargetLabel);
- branch->target = (LIR*)target;
+ branch->target = target;
storeValue(cUnit, rlDest, rlResult);
}
@@ -107,7 +107,7 @@
swapped = true;
break;
default:
- LOG(FATAL) << "No support for ConditionCode: " << (int) cond;
+ LOG(FATAL) << "No support for ConditionCode: " << cond;
return NULL;
}
if (cmpZero) {
@@ -177,7 +177,7 @@
LIR* opRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
LIR *res = opRegCopyNoInsert(cUnit, rDest, rSrc);
- oatAppendLIR(cUnit, (LIR*)res);
+ oatAppendLIR(cUnit, res);
return res;
}
diff --git a/src/compiler/codegen/mips/mips_lir.h b/src/compiler/codegen/mips/mips_lir.h
index 4b604d2..b6f686d 100644
--- a/src/compiler/codegen/mips/mips_lir.h
+++ b/src/compiler/codegen/mips/mips_lir.h
@@ -163,7 +163,7 @@
kMipsRegEnd = 51,
};
-#define ENCODE_MIPS_REG_LIST(N) ((uint64_t) N)
+#define ENCODE_MIPS_REG_LIST(N) (static_cast<uint64_t>(N))
#define ENCODE_MIPS_REG_SP (1ULL << kMipsRegSP)
#define ENCODE_MIPS_REG_LR (1ULL << kMipsRegLR)
#define ENCODE_MIPS_REG_PC (1ULL << kMipsRegPC)
@@ -303,7 +303,7 @@
#define kST kSYNC0
#define kSY kSYNC0
-#define isPseudoOpcode(opCode) ((int)(opCode) < 0)
+#define isPseudoOpcode(opCode) (static_cast<int>(opCode) < 0)
/*
* The following enum defines the list of supported Thumb instructions by the
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index a5a8d7e..e157760 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -199,7 +199,7 @@
strcpy(tbuf, "!");
} else {
DCHECK_LT(fmt, fmtEnd);
- DCHECK_LT((unsigned)(nc-'0'), 4u);
+ DCHECK_LT(static_cast<unsigned>(nc-'0'), 4u);
operand = lir->operands[nc-'0'];
switch (*fmt++) {
case 'b':
@@ -233,19 +233,19 @@
sprintf(tbuf,"%d", operand*2);
break;
case 't':
- sprintf(tbuf,"0x%08x (L%p)", (int) baseAddr + lir->offset + 4 +
+ sprintf(tbuf,"0x%08x (L%p)", reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4 +
(operand << 2), lir->target);
break;
case 'T':
- sprintf(tbuf,"0x%08x", (int) (operand << 2));
+ sprintf(tbuf,"0x%08x", operand << 2);
break;
case 'u': {
int offset_1 = lir->operands[0];
int offset_2 = NEXT_LIR(lir)->operands[0];
- intptr_t target =
- ((((intptr_t) baseAddr + lir->offset + 4) & ~3) +
+ uintptr_t target =
+ (((reinterpret_cast<uintptr_t>(baseAddr) + lir->offset + 4) & ~3) +
(offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc;
- sprintf(tbuf, "%p", (void *) target);
+ sprintf(tbuf, "%p", reinterpret_cast<void*>(target));
break;
}
@@ -275,11 +275,10 @@
}
// FIXME: need to redo resource maps for MIPS - fix this at that time
-void oatDumpResourceMask(LIR *lir, uint64_t mask, const char *prefix)
+void oatDumpResourceMask(LIR *mipsLIR, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
- LIR *mipsLIR = (LIR *) lir;
if (mask == ENCODE_ALL) {
strcpy(buf, "all");
@@ -467,12 +466,6 @@
oatFreeTemp(cUnit, rMIPS_ARG3);
}
-/* Convert an instruction to a NOP */
-void oatNopLIR( LIR* lir)
-{
- ((LIR*)lir)->flags.isNop = true;
-}
-
/*
* Determine the initial instruction set to be used for this trace.
* Later components may decide to change this.
@@ -544,17 +537,15 @@
int numFPRegs = 0;
int numFPTemps = 0;
#endif
- RegisterPool *pool = (RegisterPool *)oatNew(cUnit, sizeof(*pool), true,
- kAllocRegAlloc);
+ RegisterPool *pool =
+ static_cast<RegisterPool*>(oatNew(cUnit, sizeof(*pool), true, kAllocRegAlloc));
cUnit->regPool = pool;
pool->numCoreRegs = numRegs;
- pool->coreRegs = (RegisterInfo *)
- oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs),
- true, kAllocRegAlloc);
+ pool->coreRegs = static_cast<RegisterInfo*>
+ (oatNew(cUnit, numRegs * sizeof(*cUnit->regPool->coreRegs), true, kAllocRegAlloc));
pool->numFPRegs = numFPRegs;
- pool->FPRegs = (RegisterInfo *)
- oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true,
- kAllocRegAlloc);
+ pool->FPRegs = static_cast<RegisterInfo*>
+ (oatNew(cUnit, numFPRegs * sizeof(*cUnit->regPool->FPRegs), true, kAllocRegAlloc));
oatInitPool(pool->coreRegs, coreRegs, pool->numCoreRegs);
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
@@ -573,9 +564,8 @@
oatMarkTemp(cUnit, fpTemps[i]);
}
// Construct the alias map.
- cUnit->phiAliasMap = (int*)oatNew(cUnit, cUnit->numSSARegs *
- sizeof(cUnit->phiAliasMap[0]), false,
- kAllocDFInfo);
+ cUnit->phiAliasMap = static_cast<int*>
+ (oatNew(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, kAllocDFInfo));
for (int i = 0; i < cUnit->numSSARegs; i++) {
cUnit->phiAliasMap[i] = i;
}
@@ -645,48 +635,11 @@
opRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
}
-/*
- * Nop any unconditional branches that go to the next instruction.
- * Note: new redundant branches may be inserted later, and we'll
- * use a check in final instruction assembly to nop those out.
- */
-void removeRedundantBranches(CompilationUnit* cUnit)
+bool branchUnconditional(LIR* lir)
{
- LIR* thisLIR;
-
- for (thisLIR = (LIR*) cUnit->firstLIRInsn;
- thisLIR != (LIR*) cUnit->lastLIRInsn;
- thisLIR = NEXT_LIR(thisLIR)) {
-
- /* Branch to the next instruction */
- if (thisLIR->opcode == kMipsB) {
- LIR* nextLIR = thisLIR;
-
- while (true) {
- nextLIR = NEXT_LIR(nextLIR);
-
- /*
- * Is the branch target the next instruction?
- */
- if (nextLIR == (LIR*) thisLIR->target) {
- thisLIR->flags.isNop = true;
- break;
- }
-
- /*
- * Found real useful stuff between the branch and the target.
- * Need to explicitly check the lastLIRInsn here because it
- * might be the last real instruction.
- */
- if (!isPseudoOpcode(nextLIR->opcode) ||
- (nextLIR = (LIR*) cUnit->lastLIRInsn))
- break;
- }
- }
- }
+ return (lir->opcode == kMipsB);
}
-
/* Common initialization routine for an architecture family */
bool oatArchInit()
{
@@ -695,8 +648,7 @@
for (i = 0; i < kMipsLast; i++) {
if (EncodingMap[i].opcode != i) {
LOG(FATAL) << "Encoding order for " << EncodingMap[i].name <<
- " is wrong: expecting " << i << ", seeing " <<
- (int)EncodingMap[i].opcode;
+ " is wrong: expecting " << i << ", seeing " << static_cast<int>(EncodingMap[i].opcode);
}
}