diff --git a/src/compiler/codegen/arm/arm_lir.h b/src/compiler/codegen/arm/arm_lir.h
index a068502..503fbda 100644
--- a/src/compiler/codegen/arm/arm_lir.h
+++ b/src/compiler/codegen/arm/arm_lir.h
@@ -17,7 +17,6 @@
 #ifndef ART_SRC_COMPILER_CODEGEN_ARM_ARMLIR_H_
 #define ART_SRC_COMPILER_CODEGEN_ARM_ARMLIR_H_
 
-#include "../../dalvik.h"
 #include "../../compiler_internals.h"
 
 namespace art {
@@ -135,11 +134,11 @@
   kArmRegEnd   = 48,
 };
 
-#define ENCODE_ARM_REG_LIST(N)      ((u8) N)
+#define ENCODE_ARM_REG_LIST(N)      ((uint64_t) N)
 #define ENCODE_ARM_REG_SP           (1ULL << kArmRegSP)
 #define ENCODE_ARM_REG_LR           (1ULL << kArmRegLR)
 #define ENCODE_ARM_REG_PC           (1ULL << kArmRegPC)
-#define ENCODE_ARM_REG_FPCS_LIST(N) ((u8)N << kArmFPReg16)
+#define ENCODE_ARM_REG_FPCS_LIST(N) ((uint64_t)N << kArmFPReg16)
 
 enum ArmNativeRegisterPool {
   r0   = 0,
@@ -592,7 +591,7 @@
 
 /* Struct used to define the snippet positions for each Thumb opcode */
 struct ArmEncodingMap {
-  u4 skeleton;
+  uint32_t skeleton;
   struct {
     ArmEncodingKind kind;
     int end;   /* end for kFmtBitBlt, 1-bit slice end for FP regs */
@@ -605,11 +604,6 @@
   int size;   /* Size in bytes */
 };
 
-/* Keys for target-specific scheduling and other optimization hints */
-enum ArmTargetOptHints {
-  kMaxHoistDistance,
-};
-
 extern const ArmEncodingMap EncodingMap[kArmLast];
 
 }  // namespace art
diff --git a/src/compiler/codegen/arm/assemble_arm.cc b/src/compiler/codegen/arm/assemble_arm.cc
index e1b8672..6370f6c 100644
--- a/src/compiler/codegen/arm/assemble_arm.cc
+++ b/src/compiler/codegen/arm/assemble_arm.cc
@@ -14,10 +14,8 @@
  * limitations under the License.
  */
 
-#include "../../dalvik.h"
-#include "../../compiler_internals.h"
 #include "arm_lir.h"
-#include "codegen.h"
+#include "../codegen_util.h"
 
 namespace art {
 
@@ -1252,11 +1250,11 @@
       continue;
     }
     const ArmEncodingMap *encoder = &EncodingMap[lir->opcode];
-    u4 bits = encoder->skeleton;
+    uint32_t bits = encoder->skeleton;
     int i;
     for (i = 0; i < 4; i++) {
-      u4 operand;
-      u4 value;
+      uint32_t operand;
+      uint32_t value;
       operand = lir->operands[i];
       switch (encoder->fieldLoc[i].kind) {
         case kFmtUnused:
@@ -1337,13 +1335,13 @@
           bits |= value;
           break;
         case kFmtOff24: {
-          u4 signbit = (operand >> 31) & 0x1;
-          u4 i1 = (operand >> 22) & 0x1;
-          u4 i2 = (operand >> 21) & 0x1;
-          u4 imm10 = (operand >> 11) & 0x03ff;
-          u4 imm11 = operand & 0x07ff;
-          u4 j1 = (i1 ^ signbit) ? 0 : 1;
-          u4 j2 = (i2 ^ signbit) ? 0 : 1;
+          uint32_t signbit = (operand >> 31) & 0x1;
+          uint32_t i1 = (operand >> 22) & 0x1;
+          uint32_t i2 = (operand >> 21) & 0x1;
+          uint32_t imm10 = (operand >> 11) & 0x03ff;
+          uint32_t imm11 = operand & 0x07ff;
+          uint32_t j1 = (i1 ^ signbit) ? 0 : 1;
+          uint32_t j2 = (i2 ^ signbit) ? 0 : 1;
           value = (signbit << 26) | (j1 << 13) | (j2 << 11) | (imm10 << 16) |
               imm11;
           bits |= value;
diff --git a/src/compiler/codegen/arm/backend_arm.cc b/src/compiler/codegen/arm/backend_arm.cc
index d8f2996..47d1967 100644
--- a/src/compiler/codegen/arm/backend_arm.cc
+++ b/src/compiler/codegen/arm/backend_arm.cc
@@ -16,17 +16,14 @@
 #define _CODEGEN_C
 #define _ARMV7_A
 
-#include "../../dalvik.h"
-#include "../../compiler_internals.h"
 #include "arm_lir.h"
-#include "../ralloc.h"
-#include "codegen.h"
+#include "../ralloc_util.h"
 
 /* Common codegen utility code */
 #include "../codegen_util.cc"
 
 #include "utility_arm.cc"
-#include "../codegen_factory.cc"
+#include "../gen_loadstore.cc"
 #include "../gen_common.cc"
 #include "../gen_invoke.cc"
 #include "call_arm.cc"
diff --git a/src/compiler/codegen/arm/call_arm.cc b/src/compiler/codegen/arm/call_arm.cc
index 3fd5b15..92b067c 100644
--- a/src/compiler/codegen/arm/call_arm.cc
+++ b/src/compiler/codegen/arm/call_arm.cc
@@ -324,7 +324,7 @@
 void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
                      RegLocation rlSrc)
 {
-  const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+  const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
   if (cUnit->printMe) {
     dumpSparseSwitchTable(table);
   }
@@ -372,7 +372,7 @@
 void genPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
                      RegLocation rlSrc)
 {
-  const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+  const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
   if (cUnit->printMe) {
     dumpPackedSwitchTable(table);
   }
@@ -428,14 +428,14 @@
  */
 void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset, RegLocation rlSrc)
 {
-  const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+  const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
   // Add the table to the list - we'll process it later
   FillArrayData *tabRec = (FillArrayData *)
      oatNew(cUnit, sizeof(FillArrayData), true, kAllocData);
   tabRec->table = table;
   tabRec->vaddr = cUnit->currentDalvikOffset;
-  u2 width = tabRec->table[1];
-  u4 size = tabRec->table[2] | (((u4)tabRec->table[3]) << 16);
+  uint16_t width = tabRec->table[1];
+  uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
   tabRec->size = (size * width) + 8;
 
   oatInsertGrowableList(cUnit, &cUnit->fillArrayData, (intptr_t)tabRec);
@@ -456,10 +456,10 @@
  * Handle simple case (thin lock) inline.  If it's complicated, bail
  * out to the heavyweight lock/unlock routines.  We'll use dedicated
  * registers here in order to be in the right position in case we
- * to bail to dvm[Lock/Unlock]Object(self, object)
+ * to bail to oat[Lock/Unlock]Object(self, object)
  *
- * r0 -> self pointer [arg0 for dvm[Lock/Unlock]Object
- * r1 -> object [arg1 for dvm[Lock/Unlock]Object
+ * r0 -> self pointer [arg0 for oat[Lock/Unlock]Object
+ * r1 -> object [arg1 for oat[Lock/Unlock]Object
  * r2 -> intial contents of object->lock, later result of strex
  * r3 -> self->threadId
  * r12 -> allow to be used by utilities as general temp
diff --git a/src/compiler/codegen/arm/codegen.h b/src/compiler/codegen/arm/codegen.h
deleted file mode 100644
index 47f45c6..0000000
--- a/src/compiler/codegen/arm/codegen.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2012 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* This file contains register alloction support. */
-
-#include "../../compiler_ir.h"
-
-namespace art {
-
-#if defined(_CODEGEN_C)
-LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
-LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
-LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
-                    int checkValue, LIR* target);
-bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
-                RegLocation rlSrc);
-
-/* Forward declaraton the portable versions due to circular dependency */
-bool genArithOpFloatPortable(CompilationUnit* cUnit, Instruction::Code opcode,
-                             RegLocation rlDest, RegLocation rlSrc1,
-                             RegLocation rlSrc2);
-
-bool genArithOpDoublePortable(CompilationUnit* cUnit, Instruction::Code opcode,
-                              RegLocation rlDest, RegLocation rlSrc1,
-                              RegLocation rlSrc2);
-
-bool genConversionPortable(CompilationUnit* cUnit, Instruction::Code opcode,
-                           RegLocation rlDest, RegLocation rlSrc);
-
-ArmConditionCode oatArmConditionEncoding(ConditionCode code);
-
-int loadHelper(CompilationUnit* cUnit, int offset);
-LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
-void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
-                   int srcLo, int srcHi);
-LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
-void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
-                     RegLocation rlFree);
-
-
-/*
- * Return most flexible allowed register class based on size.
- * Bug: 2813841
- * Must use a core register for data types narrower than word (due
- * to possible unaligned load/store.
- */
-inline RegisterClass oatRegClassBySize(OpSize size)
-{
-  return (size == kUnsignedHalf ||
-          size == kSignedHalf ||
-          size == kUnsignedByte ||
-          size == kSignedByte ) ? kCoreReg : kAnyReg;
-}
-
-/*
- * Construct an s4 from two consecutive half-words of switch data.
- * This needs to check endianness because the DEX optimizer only swaps
- * half-words in instruction stream.
- *
- * "switchData" must be 32-bit aligned.
- */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-inline s4 s4FromSwitchData(const void* switchData) {
-  return *(s4*) switchData;
-}
-#else
-inline s4 s4FromSwitchData(const void* switchData) {
-  u2* data = switchData;
-  return data[0] | (((s4) data[1]) << 16);
-}
-#endif
-
-#endif
-
-extern void oatSetupResourceMasks(CompilationUnit* cUnit, LIR* lir);
-
-extern LIR* oatRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc);
-
-bool genAddLong(CompilationUnit* cUnit, RegLocation rlDest,
-                RegLocation rlSrc1, RegLocation rlSrc2);
-bool genSubLong(CompilationUnit* cUnit, RegLocation rlDest,
-                RegLocation rlSrc1, RegLocation rlSrc2);
-bool genAndLong(CompilationUnit* cUnit, RegLocation rlDest,
-                RegLocation rlSrc1, RegLocation rlSrc2);
-bool genOrLong(CompilationUnit* cUnit, RegLocation rlDest,
-               RegLocation rlSrc1, RegLocation rlSrc2);
-bool genXorLong(CompilationUnit* cUnit, RegLocation rlDest,
-               RegLocation rlSrc1, RegLocation rlSrc2);
-
-}  // namespace art
diff --git a/src/compiler/codegen/arm/target_arm.cc b/src/compiler/codegen/arm/target_arm.cc
index fc643ea..5838ca7 100644
--- a/src/compiler/codegen/arm/target_arm.cc
+++ b/src/compiler/codegen/arm/target_arm.cc
@@ -16,7 +16,8 @@
 
 #include "../../compiler_internals.h"
 #include "arm_lir.h"
-#include "../ralloc.h"
+#include "../ralloc_util.h"
+#include "../codegen_util.h"
 
 #include <string>
 
@@ -122,9 +123,9 @@
 /*
  * Decode the register id.
  */
-u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
+uint64_t getRegMaskCommon(CompilationUnit* cUnit, int reg)
 {
-  u8 seed;
+  uint64_t seed;
   int shift;
   int regId;
 
@@ -206,7 +207,7 @@
   }
   /* Fixup for kThumbPush/lr and kThumbPop/pc */
   if (opcode == kThumbPush || opcode == kThumbPop) {
-    u8 r8Mask = oatGetRegMaskCommon(cUnit, r8);
+    uint64_t r8Mask = oatGetRegMaskCommon(cUnit, r8);
     if ((opcode == kThumbPush) && (lir->useMask & r8Mask)) {
       lir->useMask &= ~r8Mask;
       lir->useMask |= ENCODE_ARM_REG_LR;
@@ -310,7 +311,7 @@
 int expandImmediate(int value)
 {
   int mode = (value & 0xf00) >> 8;
-  u4 bits = value & 0xff;
+  uint32_t bits = value & 0xff;
   switch (mode) {
     case 0:
       return bits;
@@ -472,7 +473,7 @@
   return buf;
 }
 
-void oatDumpResourceMask(LIR* lir, u8 mask, const char* prefix)
+void oatDumpResourceMask(LIR* lir, uint64_t mask, const char* prefix)
 {
   char buf[256];
   buf[0] = 0;
@@ -591,21 +592,6 @@
   return true;
 }
 
-int oatTargetOptHint(int key)
-{
-  int res = 0;
-  switch (key) {
-    case kMaxHoistDistance:
-      res = 7;
-      break;
-    default:
-      LOG(FATAL) << "Unknown target optimization hint key: " << key;
-    }
-  return res;
-}
-
-/* This file contains codegen for the Thumb ISA. */
-
 /*
  * Alloc a pair of core registers, or a double.  Low reg in low byte,
  * high reg in next byte.
@@ -755,8 +741,7 @@
       SRegToVReg(cUnit, info1->sReg))
       info1 = info2;
     int vReg = SRegToVReg(cUnit, info1->sReg);
-    oatFlushRegWideImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg),
-                        info1->reg, info1->partner);
+    storeBaseDispWide(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg), info1->reg, info1->partner);
   }
 }
 
@@ -766,7 +751,7 @@
   if (info->live && info->dirty) {
     info->dirty = false;
     int vReg = SRegToVReg(cUnit, info->sReg);
-    oatFlushRegImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
+    storeBaseDisp(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
   }
 }
 
diff --git a/src/compiler/codegen/arm/utility_arm.cc b/src/compiler/codegen/arm/utility_arm.cc
index e83093b..9069826 100644
--- a/src/compiler/codegen/arm/utility_arm.cc
+++ b/src/compiler/codegen/arm/utility_arm.cc
@@ -59,9 +59,9 @@
   return loadPcRel;
 }
 
-int leadingZeros(u4 val)
+int leadingZeros(uint32_t val)
 {
-  u4 alt;
+  uint32_t alt;
   int n;
   int count;
 
@@ -82,11 +82,11 @@
  * Determine whether value can be encoded as a Thumb2 modified
  * immediate.  If not, return -1.  If so, return i:imm3:a:bcdefgh form.
  */
-int modifiedImmediate(u4 value)
+int modifiedImmediate(uint32_t value)
 {
    int zLeading;
    int zTrailing;
-   u4 b0 = value & 0xff;
+   uint32_t b0 = value & 0xff;
 
    /* Note: case of value==0 must use 0:000:0:0000000 encoding */
    if (value <= 0xFF)