commit ec13743da80a80c1817cf6660c28917fc28846bc
author buzbee <buzbee@google.com> Tue Nov 13 12:13:16 2012 -0800
committer buzbee <buzbee@google.com> Tue Nov 13 13:13:40 2012 -0800
tree f551225a325636dc56e0a3c01c55a59316e9e829
parent f42b6f912dd390808bbd5c025d773ebb02a06ed7

Revert "Revert "Refactor codegen resource masks""

This reverts commit 4b39c9f1b77ff32cf5760e6bf77c189678e2c9a6.

The problem with the original commit was failure to widen a
couple of local variables to hold the newly widenened to 64-bits
EncodingMap flag field - thus we lost some high-order resource
attributes and broke instruction scheduling for x86.

Change-Id: I04d7caf79e2cc802c39369ca04666629218ccaea

src/compiler/codegen/arm/ArchUtility.cc

diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index 820f64e..8746b68 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -22,24 +22,57 @@
 
 namespace art {
 
+/*
+ * Decode the register id.
+ */
+u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
+{
+  u8 seed;
+  int shift;
+  int regId;
+
+
+  regId = reg & 0x1f;
+  /* Each double register is equal to a pair of single-precision FP registers */
+  seed = DOUBLEREG(reg) ? 3 : 1;
+  /* FP register starts at bit position 16 */
+  shift = FPREG(reg) ? kArmFPReg0 : 0;
+  /* Expand the double register id into single offset */
+  shift += regId;
+  return (seed << shift);
+}
+
+uint64_t getPCUseDefEncoding()
+{
+  return ENCODE_ARM_REG_PC;
+}
+
 void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
 {
   DCHECK_EQ(cUnit->instructionSet, kThumb2);
 
   // Thumb2 specific setup
-  int flags = EncodingMap[lir->opcode].flags;
+  uint64_t flags = EncodingMap[lir->opcode].flags;
   int opcode = lir->opcode;
 
+  if (flags & REG_DEF_SP) {
+    lir->defMask |= ENCODE_ARM_REG_SP;
+  }
+
+  if (flags & REG_USE_SP) {
+    lir->useMask |= ENCODE_ARM_REG_SP;
+  }
+
   if (flags & REG_DEF_LIST0) {
-    lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
+    lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
   }
 
   if (flags & REG_DEF_LIST1) {
-    lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
+    lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
   }
 
   if (flags & REG_DEF_FPCS_LIST0) {
-    lir->defMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
+    lir->defMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
   }
 
   if (flags & REG_DEF_FPCS_LIST2) {
@@ -49,7 +82,7 @@
   }
 
   if (flags & REG_USE_PC) {
-    lir->useMask |= ENCODE_REG_PC;
+    lir->useMask |= ENCODE_ARM_REG_PC;
   }
 
   /* Conservatively treat the IT block */
@@ -58,15 +91,15 @@
   }
 
   if (flags & REG_USE_LIST0) {
-    lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
+    lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
   }
 
   if (flags & REG_USE_LIST1) {
-    lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
+    lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
   }
 
   if (flags & REG_USE_FPCS_LIST0) {
-    lir->useMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
+    lir->useMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
   }
 
   if (flags & REG_USE_FPCS_LIST2) {
@@ -79,14 +112,14 @@
     u8 r8Mask = oatGetRegMaskCommon(cUnit, r8);
     if ((opcode == kThumbPush) && (lir->useMask & r8Mask)) {
       lir->useMask &= ~r8Mask;
-      lir->useMask |= ENCODE_REG_LR;
+      lir->useMask |= ENCODE_ARM_REG_LR;
     } else if ((opcode == kThumbPop) && (lir->defMask & r8Mask)) {
       lir->defMask &= ~r8Mask;
-      lir->defMask |= ENCODE_REG_PC;
+      lir->defMask |= ENCODE_ARM_REG_PC;
     }
   }
   if (flags & REG_DEF_LR) {
-    lir->defMask |= ENCODE_REG_LR;
+    lir->defMask |= ENCODE_ARM_REG_LR;
   }
 }
 
@@ -354,7 +387,7 @@
     char num[8];
     int i;
 
-    for (i = 0; i < kRegEnd; i++) {
+    for (i = 0; i < kArmRegEnd; i++) {
       if (mask & (1ULL << i)) {
         sprintf(num, "%d ", i);
         strcat(buf, num);