ART: Fixes an issue with REX prefix for instructions with no ModRM byte
There are instructions (such as push, pop, mov) in the x86 ISA
that encode first operands in their opcodes (opcode + reg).
In order to enable an extended 64bit registers (R9-R15) a special
prefix REX.B should be emitted before such instructions.
This patch fixes the issue when REX.R prefix was emitted before
instructions with no MorRM byte. So, the REX-prefix was simply
ignored by CPU for those instructions whose operands are encoded
in their opcodes.
This patch makes the jni_compiler_test passed with JNI compiler
enabled for x86_64 target.
Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc
index 7d02c7c..9507e12 100644
--- a/compiler/utils/x86_64/assembler_x86_64.cc
+++ b/compiler/utils/x86_64/assembler_x86_64.cc
@@ -1493,7 +1493,7 @@
}
void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) {
- EmitOptionalRex(false, false, reg.NeedsRex(), false, false);
+ EmitOptionalRex(false, false, false, false, reg.NeedsRex());
}
void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
@@ -1540,8 +1540,9 @@
}
void X86_64Assembler::EmitRex64(CpuRegister reg) {
- EmitOptionalRex(false, true, reg.NeedsRex(), false, false);
+ EmitOptionalRex(false, true, false, false, reg.NeedsRex());
}
+
void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex());
}
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc
index 68e77d4..1b96a2b 100644
--- a/disassembler/disassembler_x86.cc
+++ b/disassembler/disassembler_x86.cc
@@ -735,7 +735,7 @@
std::ostringstream args;
if (reg_in_opcode) {
DCHECK(!has_modrm);
- DumpReg(args, rex, *instr & 0x7, false, prefix[2], GPR);
+ DumpBaseReg(args, rex, *instr & 0x7);
}
instr++;
uint32_t address_bits = 0;