x86_64: JNI compiler
Passed all tests from jni_compiler_test and art/test on host with jni_copiler.
Incoming argument spill is enabled, entry_spills refactored. Now each entry spill
contains data type size (4 or 8) and offset which should be used for spill.
Assembler REX support implemented in opcodes used in JNI compiler.
Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875).
Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
diff --git a/compiler/utils/managed_register.h b/compiler/utils/managed_register.h
index 04c9723..f007d28 100644
--- a/compiler/utils/managed_register.h
+++ b/compiler/utils/managed_register.h
@@ -17,6 +17,8 @@
#ifndef ART_COMPILER_UTILS_MANAGED_REGISTER_H_
#define ART_COMPILER_UTILS_MANAGED_REGISTER_H_
+#include <vector>
+
namespace art {
namespace arm {
@@ -28,10 +30,15 @@
namespace mips {
class MipsManagedRegister;
}
+
namespace x86 {
class X86ManagedRegister;
}
+namespace x86_64 {
+class X86_64ManagedRegister;
+}
+
class ManagedRegister {
public:
// ManagedRegister is a value class. There exists no method to change the
@@ -48,6 +55,7 @@
arm64::Arm64ManagedRegister AsArm64() const;
mips::MipsManagedRegister AsMips() const;
x86::X86ManagedRegister AsX86() const;
+ x86_64::X86_64ManagedRegister AsX86_64() const;
// It is valid to invoke Equals on and with a NoRegister.
bool Equals(const ManagedRegister& other) const {
@@ -71,6 +79,44 @@
int id_;
};
+class ManagedRegisterSpill : public ManagedRegister {
+ public:
+ // ManagedRegisterSpill contains information about data type size and location in caller frame
+ // These additional attributes could be defined by calling convention (EntrySpills)
+ ManagedRegisterSpill(const ManagedRegister& other, uint32_t size, uint32_t spill_offset)
+ : ManagedRegister(other), size_(size), spill_offset_(spill_offset) { }
+
+ explicit ManagedRegisterSpill(const ManagedRegister& other)
+ : ManagedRegister(other), size_(-1), spill_offset_(-1) { }
+
+ int32_t getSpillOffset() {
+ return spill_offset_;
+ }
+
+ int32_t getSize() {
+ return size_;
+ }
+
+ private:
+ int32_t size_;
+ int32_t spill_offset_;
+};
+
+class ManagedRegisterEntrySpills : public std::vector<ManagedRegisterSpill> {
+ public:
+ // The ManagedRegister does not have information about size and offset.
+ // In this case it's size and offset determined by BuildFrame (assembler)
+ void push_back(ManagedRegister __x) {
+ ManagedRegisterSpill spill(__x);
+ std::vector<ManagedRegisterSpill>::push_back(spill);
+ }
+
+ void push_back(ManagedRegisterSpill __x) {
+ std::vector<ManagedRegisterSpill>::push_back(__x);
+ }
+ private:
+};
+
} // namespace art
#endif // ART_COMPILER_UTILS_MANAGED_REGISTER_H_