tree f36ede911525e6970486a1ae64dde540a2e7ddf7
parent 15a2eb0de3e5d66595350426bdd50905c46a0fb0
author Artem Serov <artem.serov@linaro.org> 1468242046 +0100
committer Meninblack007 <sanyam.53jain@gmail.com> 1497530607 +0530

ARM: Fix shifted register offset mem address mode for load signed.

For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.

Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1