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Ian Rogers3a5c1ce2012-02-29 10:06:46 -08001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "disassembler_arm.h"
18
Ian Rogers3a5c1ce2012-02-29 10:06:46 -080019#include <iostream>
20
Elliott Hughes0f3c5532012-03-30 14:51:51 -070021#include "logging.h"
22#include "stringprintf.h"
Elliott Hughes28fa76d2012-04-09 17:31:46 -070023#include "thread.h"
Elliott Hughes0f3c5532012-03-30 14:51:51 -070024
Ian Rogers3a5c1ce2012-02-29 10:06:46 -080025namespace art {
26namespace arm {
27
28DisassemblerArm::DisassemblerArm() {
29}
30
Ian Rogers3a5c1ce2012-02-29 10:06:46 -080031void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
32 if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) {
33 for (const uint8_t* cur = begin; cur < end; cur += 4) {
34 DumpArm(os, cur);
35 }
36 } else {
37 // remove thumb specifier bits
38 begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1);
39 end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1);
40 for (const uint8_t* cur = begin; cur < end;) {
41 cur += DumpThumb16(os, cur);
42 }
43 }
44}
45
Elliott Hughes77405792012-03-15 15:22:12 -070046static const char* kConditionCodeNames[] = {
Elliott Hughescbf0b612012-03-15 16:23:47 -070047 "eq", // 0000 - equal
48 "ne", // 0001 - not-equal
49 "cs", // 0010 - carry-set, greater than, equal or unordered
50 "cc", // 0011 - carry-clear, less than
51 "mi", // 0100 - minus, negative
52 "pl", // 0101 - plus, positive or zero
53 "vs", // 0110 - overflow
54 "vc", // 0111 - no overflow
55 "hi", // 1000 - unsigned higher
56 "ls", // 1001 - unsigned lower or same
57 "ge", // 1010 - signed greater than or equal
58 "lt", // 1011 - signed less than
59 "gt", // 1100 - signed greater than
60 "le", // 1101 - signed less than or equal
61 "", // 1110 - always
62 "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating)
Ian Rogers40627db2012-03-04 17:31:09 -080063};
64
65void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) {
66 if (cond < 15) {
Elliott Hughes77405792012-03-15 15:22:12 -070067 os << kConditionCodeNames[cond];
Ian Rogers40627db2012-03-04 17:31:09 -080068 } else {
69 os << "Unexpected condition: " << cond;
70 }
71}
72
Ian Rogers40627db2012-03-04 17:31:09 -080073void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) {
Elliott Hughes1ca98492012-04-12 17:21:02 -070074 os << StringPrintf("%+d (%p)", imm32, instr_ptr + imm32);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -080075}
76
77static uint32_t ReadU16(const uint8_t* ptr) {
78 return ptr[0] | (ptr[1] << 8);
79}
80
81static uint32_t ReadU32(const uint8_t* ptr) {
82 return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
83}
84
Elliott Hughes77405792012-03-15 15:22:12 -070085static const char* kDataProcessingOperations[] = {
Elliott Hughescbf0b612012-03-15 16:23:47 -070086 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc",
87 "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn",
Elliott Hughes77405792012-03-15 15:22:12 -070088};
89
Ian Rogersad03ef52012-03-18 19:34:47 -070090static const char* kThumbDataProcessingOperations[] = {
91 "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror",
92 "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn",
93};
94
Elliott Hughes77405792012-03-15 15:22:12 -070095struct ArmRegister {
96 ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); }
Elliott Hughes630e77d2012-03-22 19:20:56 -070097 ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); }
Elliott Hughes77405792012-03-15 15:22:12 -070098 uint32_t r;
99};
100std::ostream& operator<<(std::ostream& os, const ArmRegister& r) {
101 if (r.r == 13) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700102 os << "sp";
Elliott Hughes77405792012-03-15 15:22:12 -0700103 } else if (r.r == 14) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700104 os << "lr";
Elliott Hughes77405792012-03-15 15:22:12 -0700105 } else if (r.r == 15) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700106 os << "pc";
Elliott Hughes77405792012-03-15 15:22:12 -0700107 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700108 os << "r" << r.r;
Elliott Hughes77405792012-03-15 15:22:12 -0700109 }
110 return os;
111}
112
Elliott Hughes630e77d2012-03-22 19:20:56 -0700113struct ThumbRegister : ArmRegister {
114 ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {}
Elliott Hughes77405792012-03-15 15:22:12 -0700115};
116
117struct Rm {
118 Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {}
119 uint32_t shift;
120 ArmRegister rm;
121};
122std::ostream& operator<<(std::ostream& os, const Rm& r) {
123 os << r.rm;
124 if (r.shift != 0) {
125 os << "-shift-" << r.shift; // TODO
126 }
127 return os;
128}
129
Elliott Hughes1ca98492012-04-12 17:21:02 -0700130struct ShiftedImmediate {
131 ShiftedImmediate(uint32_t instruction) {
Elliott Hughes3d71d072012-04-10 18:28:35 -0700132 uint32_t rotate = ((instruction >> 8) & 0xf);
133 uint32_t imm = (instruction & 0xff);
134 value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate)));
135 }
136 uint32_t value;
Elliott Hughes77405792012-03-15 15:22:12 -0700137};
Elliott Hughes1ca98492012-04-12 17:21:02 -0700138std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) {
Elliott Hughes3d71d072012-04-10 18:28:35 -0700139 os << "#" << rhs.value;
Elliott Hughes77405792012-03-15 15:22:12 -0700140 return os;
141}
142
143struct RegisterList {
144 RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {}
145 uint32_t register_list;
146};
147std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) {
148 if (rhs.register_list == 0) {
149 os << "<no register list?>";
150 return os;
151 }
Elliott Hughes630e77d2012-03-22 19:20:56 -0700152 os << "{";
Elliott Hughes77405792012-03-15 15:22:12 -0700153 bool first = true;
154 for (size_t i = 0; i < 16; i++) {
155 if ((rhs.register_list & (1 << i)) != 0) {
156 if (first) {
Elliott Hughes77405792012-03-15 15:22:12 -0700157 first = false;
158 } else {
159 os << ", ";
160 }
161 os << ArmRegister(i);
162 }
163 }
164 os << "}";
165 return os;
166}
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800167
168void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) {
Elliott Hughes77405792012-03-15 15:22:12 -0700169 uint32_t instruction = ReadU32(instr_ptr);
170 uint32_t cond = (instruction >> 28) & 0xf;
171 uint32_t op1 = (instruction >> 25) & 0x7;
Elliott Hughes3d71d072012-04-10 18:28:35 -0700172 std::string opcode;
173 std::string suffixes;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700174 std::ostringstream args;
Elliott Hughes77405792012-03-15 15:22:12 -0700175 switch (op1) {
176 case 0:
177 case 1: // Data processing instructions.
178 {
Elliott Hughes3d71d072012-04-10 18:28:35 -0700179 if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT
180 opcode = "bkpt";
181 uint32_t imm12 = (instruction >> 8) & 0xfff;
182 uint32_t imm4 = (instruction & 0xf);
183 args << '#' << ((imm12 << 4) | imm4);
184 break;
185 }
Elliott Hughes77405792012-03-15 15:22:12 -0700186 if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register)
Elliott Hughes3d71d072012-04-10 18:28:35 -0700187 opcode = (((instruction >> 5) & 1) ? "blx" : "bx");
Elliott Hughescbf0b612012-03-15 16:23:47 -0700188 args << ArmRegister(instruction & 0xf);
Elliott Hughes77405792012-03-15 15:22:12 -0700189 break;
190 }
191 bool i = (instruction & (1 << 25)) != 0;
192 bool s = (instruction & (1 << 20)) != 0;
Elliott Hughes3d71d072012-04-10 18:28:35 -0700193 uint32_t op = (instruction >> 21) & 0xf;
194 opcode = kDataProcessingOperations[op];
195 bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN.
196 if (implicit_s) {
197 // Rd is unused (and not shown), and we don't show the 's' suffix either.
198 } else {
199 if (s) {
200 suffixes += 's';
201 }
202 args << ArmRegister(instruction, 12) << ", ";
203 }
Elliott Hughes77405792012-03-15 15:22:12 -0700204 if (i) {
Elliott Hughes1ca98492012-04-12 17:21:02 -0700205 args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction);
Elliott Hughes77405792012-03-15 15:22:12 -0700206 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700207 args << Rm(instruction);
Elliott Hughes77405792012-03-15 15:22:12 -0700208 }
209 }
210 break;
211 case 2: // Load/store word and unsigned byte.
212 {
213 bool p = (instruction & (1 << 24)) != 0;
214 bool b = (instruction & (1 << 22)) != 0;
215 bool w = (instruction & (1 << 21)) != 0;
216 bool l = (instruction & (1 << 20)) != 0;
Elliott Hughes3d71d072012-04-10 18:28:35 -0700217 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : ""));
Elliott Hughes630e77d2012-03-22 19:20:56 -0700218 args << ArmRegister(instruction, 12) << ", ";
219 ArmRegister rn(instruction, 16);
220 if (rn.r == 0xf) {
Elliott Hughes77405792012-03-15 15:22:12 -0700221 UNIMPLEMENTED(FATAL) << "literals";
222 } else {
223 bool wback = !p || w;
Elliott Hughes1ca98492012-04-12 17:21:02 -0700224 uint32_t offset = (instruction & 0xfff);
Elliott Hughes77405792012-03-15 15:22:12 -0700225 if (p && !wback) {
Elliott Hughes1ca98492012-04-12 17:21:02 -0700226 args << "[" << rn << ", #" << offset << "]";
Elliott Hughes77405792012-03-15 15:22:12 -0700227 } else if (p && wback) {
Elliott Hughes1ca98492012-04-12 17:21:02 -0700228 args << "[" << rn << ", #" << offset << "]!";
Elliott Hughes77405792012-03-15 15:22:12 -0700229 } else if (!p && wback) {
Elliott Hughes1ca98492012-04-12 17:21:02 -0700230 args << "[" << rn << "], #" << offset;
Elliott Hughes77405792012-03-15 15:22:12 -0700231 } else {
232 LOG(FATAL) << p << " " << w;
233 }
Elliott Hughes3d71d072012-04-10 18:28:35 -0700234 if (rn.r == 9) {
235 args << " ; ";
Elliott Hughes1ca98492012-04-12 17:21:02 -0700236 Thread::DumpThreadOffset(args, offset, 4);
Elliott Hughes3d71d072012-04-10 18:28:35 -0700237 }
Elliott Hughes77405792012-03-15 15:22:12 -0700238 }
239 }
240 break;
241 case 4: // Load/store multiple.
242 {
243 bool p = (instruction & (1 << 24)) != 0;
244 bool u = (instruction & (1 << 23)) != 0;
245 bool w = (instruction & (1 << 21)) != 0;
246 bool l = (instruction & (1 << 20)) != 0;
Elliott Hughes3d71d072012-04-10 18:28:35 -0700247 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a'));
Elliott Hughes630e77d2012-03-22 19:20:56 -0700248 args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction);
Elliott Hughes77405792012-03-15 15:22:12 -0700249 }
250 break;
Elliott Hughes3d71d072012-04-10 18:28:35 -0700251 case 5: // Branch/branch with link.
252 {
253 bool bl = (instruction & (1 << 24)) != 0;
254 opcode = (bl ? "bl" : "b");
Elliott Hughesd86261e2012-04-11 11:23:23 -0700255 int32_t imm26 = (instruction & 0xffffff) << 2;
256 int32_t imm32 = (imm26 << 6) >> 6; // Sign extend.
Elliott Hughes3d71d072012-04-10 18:28:35 -0700257 DumpBranchTarget(args, instr_ptr + 8, imm32);
258 }
259 break;
Elliott Hughes77405792012-03-15 15:22:12 -0700260 default:
Elliott Hughes3d71d072012-04-10 18:28:35 -0700261 opcode = "???";
Elliott Hughes77405792012-03-15 15:22:12 -0700262 break;
263 }
Elliott Hughes3d71d072012-04-10 18:28:35 -0700264 opcode += kConditionCodeNames[cond];
265 opcode += suffixes;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700266 // TODO: a more complete ARM disassembler could generate wider opcodes.
Elliott Hughes3d71d072012-04-10 18:28:35 -0700267 os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n';
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800268}
269
270size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) {
271 uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2);
272 // |111|1 1|1000000|0000|1111110000000000|
273 // |5 3|2 1|0987654|3 0|5 0 5 0|
274 // |---|---|-------|----|----------------|
275 // |332|2 2|2222222|1111|1111110000000000|
276 // |1 9|8 7|6543210|9 6|5 0 5 0|
277 // |---|---|-------|----|----------------|
278 // |111|op1| op2 | | |
279 uint32_t op1 = (instr >> 27) & 3;
Elliott Hughes77405792012-03-15 15:22:12 -0700280 if (op1 == 0) {
281 return DumpThumb16(os, instr_ptr);
282 }
283
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800284 uint32_t op2 = (instr >> 20) & 0x7F;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700285 std::ostringstream opcode;
286 std::ostringstream args;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800287 switch (op1) {
288 case 0:
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800289 break;
290 case 1:
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700291 if ((op2 & 0x64) == 0) { // 00x x0xx
292 // |111|11|10|00|0|00|0000|1111110000000000|
293 // |5 3|21|09|87|6|54|3 0|5 0 5 0|
294 // |---|--|--|--|-|--|----|----------------|
295 // |332|22|22|22|2|22|1111|1111110000000000|
296 // |1 9|87|65|43|2|10|9 6|5 0 5 0|
297 // |---|--|--|--|-|--|----|----------------|
298 // |111|01|00|op|0|WL| Rn | |
299 // |111|01| op2 | | |
300 // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr
301 // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr
302 // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr
303 // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr
304 uint32_t op = (instr >> 23) & 3;
305 uint32_t W = (instr >> 21) & 1;
306 uint32_t L = (instr >> 20) & 1;
307 ArmRegister Rn(instr, 16);
308 if (op == 1 || op == 2) {
309 if (op == 1) {
310 if (L == 0) {
311 opcode << "stm";
312 args << Rn << (W == 0 ? "" : "!") << ", ";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800313 } else {
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700314 if (Rn.r != 13) {
315 opcode << "ldm";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700316 args << Rn << (W == 0 ? "" : "!") << ", ";
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700317 } else {
318 opcode << "pop";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800319 }
320 }
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700321 } else {
322 if (L == 0) {
323 if (Rn.r != 13) {
324 opcode << "stmdb";
325 args << Rn << (W == 0 ? "" : "!") << ", ";
326 } else {
327 opcode << "push";
328 }
329 } else {
330 opcode << "ldmdb";
331 args << Rn << (W == 0 ? "" : "!") << ", ";
332 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800333 }
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700334 args << RegisterList(instr);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800335 }
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700336 } else if ((op2 & 0x60) == 0x20) { // 01x xxxx
337 // Data-processing (shifted register)
338 // |111|1110|0000|0|0000|1111|1100|0000|0000|
339 // |5 3|2109|8765|4|3 0|5 |10 8|7 5 |3 0|
340 // |---|----|----|-|----|----|----|----|----|
341 // |332|2222|2222|2|1111|1111|1100|0000|0000|
342 // |1 9|8765|4321|0|9 6|5 |10 8|7 5 |3 0|
343 // |---|----|----|-|----|----|----|----|----|
344 // |111|0101| op3|S| Rn | | Rd | | Rm |
345 uint32_t op3 = (instr >> 21) & 0xF;
346 uint32_t S = (instr >> 20) & 1;
347 uint32_t Rn = (instr >> 16) & 0xF;
348 ArmRegister Rd(instr, 8);
349 ArmRegister Rm(instr, 0);
350 switch (op3) {
351 case 0x0:
352 if (Rn != 0xF) {
353 opcode << "and";
354 } else {
355 opcode << "tst";
356 S = 0; // don't print 's'
357 }
358 break;
359 case 0x1: opcode << "bic"; break;
360 case 0x2:
361 if (Rn != 0xF) {
362 opcode << "orr";
363 } else {
364 opcode << "mov";
365 }
366 break;
367 case 0x3:
368 if (Rn != 0xF) {
369 opcode << "orn";
370 } else {
371 opcode << "mvn";
372 }
373 break;
374 case 0x4:
375 if (Rn != 0xF) {
376 opcode << "eor";
377 } else {
378 opcode << "teq";
379 S = 0; // don't print 's'
380 }
381 break;
382 case 0x6: opcode << "pkh"; break;
383 case 0x8:
384 if (Rn != 0xF) {
385 opcode << "add";
386 } else {
387 opcode << "cmn";
388 S = 0; // don't print 's'
389 }
390 break;
391 case 0xA: opcode << "adc"; break;
392 case 0xB: opcode << "sbc"; break;
393 }
Ian Rogers087b2412012-03-21 01:30:32 -0700394
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700395 if (S == 1) {
396 opcode << "s";
Ian Rogers087b2412012-03-21 01:30:32 -0700397 }
Ian Rogersc7fe4e02012-03-29 21:36:21 -0700398 opcode << ".w";
399 args << Rd << ", " << Rm;
400 } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx
401 // Co-processor instructions
402 // |111|1|11|000000|0000|1111|1100|000|0 |0000|
403 // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0|
404 // |---|-|--|------|----|----|----|---|---|----|
405 // |332|2|22|222222|1111|1111|1100|000|0 |0000|
406 // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0|
407 // |---|-|--|------|----|----|----|---|---|----|
408 // |111| |11| op3 | Rn | |copr| |op4| |
409 uint32_t op3 = (instr >> 20) & 0x3F;
410 uint32_t coproc = (instr >> 8) & 0xF;
411 uint32_t op4 = (instr >> 4) & 0x1;
412 if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0
413 if ((coproc & 0xE) == 0xA) {
414 // VFP data-processing instructions
415 // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000|
416 // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0|
417 // |---|-|----|----|----|----|---|-|----|-|-|----|
418 // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000|
419 // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0|
420 // |---|-|----|----|----|----|---|-|----|-|-|----|
421 // |111|T|1110|opc1|opc2| |101| |opc3| | | |
422 // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69
423 uint32_t opc1 = (instr >> 20) & 0xF;
424 uint32_t opc2 = (instr >> 16) & 0xF;
425 //uint32_t opc3 = (instr >> 6) & 0x3;
426 if ((opc1 & 0xB) == 0xB) { // 1x11
427 // Other VFP data-processing instructions.
428 switch (opc2) {
429 case 0x4: case 0x5: { // Vector compare
430 // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm
431 uint32_t D = (instr >> 22) & 0x1;
432 uint32_t Vd = (instr >> 12) & 0xF;
433 uint32_t sz = (instr >> 8) & 1;
434 uint32_t E = (instr >> 7) & 1;
435 uint32_t M = (instr >> 5) & 1;
436 uint32_t Vm = instr & 0xF;
437 bool dp_operation = sz == 1;
438 opcode << (E == 0 ? "vcmp" : "vcmpe");
439 opcode << (dp_operation ? ".f64" : ".f32");
440 if (dp_operation) {
441 args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm);
442 } else {
443 args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M);
444 }
445 break;
446 }
447 }
448 }
449 }
450 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800451 }
452 break;
Ian Rogers40627db2012-03-04 17:31:09 -0800453 case 2:
454 if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) {
455 // Data-processing (modified immediate)
456 // |111|11|10|0000|0|0000|1|111|1100|00000000|
457 // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0|
458 // |---|--|--|----|-|----|-|---|----|--------|
459 // |332|22|22|2222|2|1111|1|111|1100|00000000|
460 // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0|
461 // |---|--|--|----|-|----|-|---|----|--------|
462 // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii|
463 // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx
Ian Rogers40627db2012-03-04 17:31:09 -0800464 uint32_t i = (instr >> 26) & 1;
465 uint32_t op3 = (instr >> 21) & 0xF;
466 uint32_t S = (instr >> 20) & 1;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700467 ArmRegister Rn(instr, 16);
Ian Rogers40627db2012-03-04 17:31:09 -0800468 uint32_t imm3 = (instr >> 12) & 7;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700469 ArmRegister Rd(instr, 8);
Ian Rogers40627db2012-03-04 17:31:09 -0800470 uint32_t imm8 = instr & 0xFF;
471 int32_t imm32 = (i << 12) | (imm3 << 8) | imm8;
472 switch (op3) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700473 case 0x0: opcode << "and"; break;
474 case 0x1: opcode << "bic"; break;
475 case 0x2: opcode << "orr"; break;
476 case 0x3: opcode << "orn"; break;
477 case 0x4: opcode << "eor"; break;
478 case 0x8: opcode << "add"; break;
479 case 0xA: opcode << "adc"; break;
480 case 0xB: opcode << "sbc"; break;
481 case 0xD: opcode << "sub"; break;
482 case 0xE: opcode << "rsb"; break;
483 default: opcode << "UNKNOWN DPMI-" << op3; break;
Ian Rogers40627db2012-03-04 17:31:09 -0800484 }
485 if (S == 1) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700486 opcode << "s";
Ian Rogers40627db2012-03-04 17:31:09 -0800487 }
Elliott Hughes630e77d2012-03-22 19:20:56 -0700488 args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")";
Ian Rogers40627db2012-03-04 17:31:09 -0800489 } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) {
490 // Data-processing (plain binary immediate)
491 // |111|11|10|00000|0000|1|111110000000000|
492 // |5 3|21|09|87654|3 0|5|4 0 5 0|
493 // |---|--|--|-----|----|-|---------------|
494 // |332|22|22|22222|1111|1|111110000000000|
495 // |1 9|87|65|43210|9 6|5|4 0 5 0|
496 // |---|--|--|-----|----|-|---------------|
497 // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx|
498 uint32_t op3 = (instr >> 20) & 0x1F;
Ian Rogers40627db2012-03-04 17:31:09 -0800499 switch (op3) {
Ian Rogers66a3fca2012-04-09 19:51:34 -0700500 case 0x00: {
501 ArmRegister Rd(instr, 8);
502 ArmRegister Rn(instr, 16);
503 uint32_t i = (instr >> 26) & 1;
504 uint32_t imm3 = (instr >> 12) & 0x7;
505 uint32_t imm8 = instr & 0xFF;
506 uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8;
507 if (Rn.r != 0xF) {
508 opcode << "addw";
509 args << Rd << ", " << Rn << ", #" << imm12;
510 } else {
511 opcode << "adr";
512 args << Rd << ", ";
513 DumpBranchTarget(args, instr_ptr + 4, imm12);
514 }
515 break;
516 }
Ian Rogers40627db2012-03-04 17:31:09 -0800517 case 0x04: {
518 // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii
Elliott Hughes630e77d2012-03-22 19:20:56 -0700519 ArmRegister Rd(instr, 8);
Ian Rogers40627db2012-03-04 17:31:09 -0800520 uint32_t i = (instr >> 26) & 1;
521 uint32_t imm3 = (instr >> 12) & 0x7;
522 uint32_t imm8 = instr & 0xFF;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700523 uint32_t Rn = (instr >> 16) & 0xF;
Ian Rogers40627db2012-03-04 17:31:09 -0800524 uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700525 opcode << "movw";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700526 args << Rd << ", #" << imm16;
Ian Rogers40627db2012-03-04 17:31:09 -0800527 break;
528 }
529 case 0x0A: {
530 // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii
Elliott Hughes630e77d2012-03-22 19:20:56 -0700531 ArmRegister Rd(instr, 8);
532 ArmRegister Rn(instr, 16);
Ian Rogers40627db2012-03-04 17:31:09 -0800533 uint32_t i = (instr >> 26) & 1;
534 uint32_t imm3 = (instr >> 12) & 0x7;
535 uint32_t imm8 = instr & 0xFF;
536 uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700537 opcode << "sub.w";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700538 args << Rd << ", " << Rn << ", #" << imm12;
Ian Rogers40627db2012-03-04 17:31:09 -0800539 break;
540 }
541 default:
542 break;
543 }
544 } else {
545 // Branches and miscellaneous control
546 // |111|11|1000000|0000|1|111|1100|00000000|
547 // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0|
548 // |---|--|-------|----|-|---|----|--------|
549 // |332|22|2222222|1111|1|111|1100|00000000|
550 // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0|
551 // |---|--|-------|----|-|---|----|--------|
552 // |111|10| op2 | |1|op3|op4 | |
553
554 uint32_t op3 = (instr >> 12) & 7;
555 //uint32_t op4 = (instr >> 8) & 0xF;
556 switch (op3) {
557 case 0:
558 if ((op2 & 0x38) != 0x38) {
559 // Conditional branch
560 // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000|
561 // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0|
562 // |---|--|-|----|------|-|-|--|-|--|-----------|
563 // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000|
564 // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0|
565 // |---|--|-|----|------|-|-|--|-|--|-----------|
566 // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 |
567 uint32_t S = (instr >> 26) & 1;
568 uint32_t J2 = (instr >> 11) & 1;
569 uint32_t J1 = (instr >> 13) & 1;
570 uint32_t imm6 = (instr >> 16) & 0x3F;
571 uint32_t imm11 = instr & 0x7FF;
572 uint32_t cond = (instr >> 22) & 0xF;
573 int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
574 imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate
Elliott Hughescbf0b612012-03-15 16:23:47 -0700575 opcode << "b";
576 DumpCond(opcode, cond);
577 opcode << ".w";
578 DumpBranchTarget(args, instr_ptr + 4, imm32);
Ian Rogers40627db2012-03-04 17:31:09 -0800579 }
580 break;
581 case 2:
582 case 1: case 3:
583 break;
584 case 4: case 6: case 5: case 7: {
585 // BL, BLX (immediate)
586 // |111|11|1|0000000000|11|1 |1|1 |10000000000|
587 // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0|
588 // |---|--|-|----------|--|--|-|--|-----------|
589 // |332|22|2|2222221111|11|1 |1|1 |10000000000|
590 // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0|
591 // |---|--|-|----------|--|--|-|--|-----------|
592 // |111|10|S| imm10 |11|J1|L|J2| imm11 |
593 uint32_t S = (instr >> 26) & 1;
594 uint32_t J2 = (instr >> 11) & 1;
595 uint32_t L = (instr >> 12) & 1;
596 uint32_t J1 = (instr >> 13) & 1;
597 uint32_t imm10 = (instr >> 16) & 0x3FF;
598 uint32_t imm11 = instr & 0x7FF;
599 if (L == 0) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700600 opcode << "bx";
Ian Rogers40627db2012-03-04 17:31:09 -0800601 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700602 opcode << "blx";
Ian Rogers40627db2012-03-04 17:31:09 -0800603 }
604 uint32_t I1 = ~(J1 ^ S);
605 uint32_t I2 = ~(J2 ^ S);
606 int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
607 imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate.
Elliott Hughescbf0b612012-03-15 16:23:47 -0700608 DumpBranchTarget(args, instr_ptr + 4, imm32);
Ian Rogers40627db2012-03-04 17:31:09 -0800609 break;
610 }
611 }
612 }
613 break;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800614 case 3:
615 switch (op2) {
616 case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0
617 case 0x08: case 0x0A: case 0x0C: case 0x0E: {
618 // Store single data item
Ian Rogers40627db2012-03-04 17:31:09 -0800619 // |111|11|100|000|0|0000|1111|110000|000000|
620 // |5 3|21|098|765|4|3 0|5 2|10 6|5 0|
621 // |---|--|---|---|-|----|----|------|------|
622 // |332|22|222|222|2|1111|1111|110000|000000|
623 // |1 9|87|654|321|0|9 6|5 2|10 6|5 0|
624 // |---|--|---|---|-|----|----|------|------|
625 // |111|11|000|op3|0| | | op4 | |
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800626 uint32_t op3 = (instr >> 21) & 7;
627 //uint32_t op4 = (instr >> 6) & 0x3F;
628 switch (op3) {
Ian Rogers087b2412012-03-21 01:30:32 -0700629 case 0x0: case 0x4: {
630 // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii
631 // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm
Elliott Hughes630e77d2012-03-22 19:20:56 -0700632 ArmRegister Rn(instr, 16);
633 ArmRegister Rt(instr, 12);
Ian Rogers087b2412012-03-21 01:30:32 -0700634 opcode << "strb";
635 if ((instr & 0x800) != 0) {
636 uint32_t imm8 = instr & 0xFF;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700637 args << Rt << ", [" << Rn << ",#" << imm8 << "]";
Ian Rogers087b2412012-03-21 01:30:32 -0700638 } else {
639 uint32_t imm2 = (instr >> 4) & 3;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700640 ArmRegister Rm(instr, 0);
641 args << Rt << ", [" << Rn << ", " << Rm;
Ian Rogers087b2412012-03-21 01:30:32 -0700642 if (imm2 != 0) {
643 args << ", " << "lsl #" << imm2;
644 }
645 args << "]";
646 }
647 break;
648 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800649 case 0x2: case 0x6: {
Elliott Hughes630e77d2012-03-22 19:20:56 -0700650 ArmRegister Rn(instr, 16);
651 ArmRegister Rt(instr, 12);
Ian Rogers40627db2012-03-04 17:31:09 -0800652 if (op3 == 2) {
Ian Rogers66a3fca2012-04-09 19:51:34 -0700653 if ((instr & 0x800) != 0) {
654 // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii
655 uint32_t P = (instr >> 10) & 1;
656 uint32_t U = (instr >> 9) & 1;
657 uint32_t W = (instr >> 8) & 1;
658 uint32_t imm8 = instr & 0xFF;
659 int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8
660 if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) {
661 opcode << "push";
662 args << Rt;
663 } else if (Rn.r == 15 || (P == 0 && W == 0)) {
664 opcode << "UNDEFINED";
Ian Rogers40627db2012-03-04 17:31:09 -0800665 } else {
Ian Rogers66a3fca2012-04-09 19:51:34 -0700666 if (P == 1 && U == 1 && W == 0) {
667 opcode << "strt";
668 } else {
669 opcode << "str";
670 }
671 args << Rt << ", [" << Rn;
672 if (P == 0 && W == 1) {
673 args << "], #" << imm32;
674 } else {
675 args << ", #" << imm32 << "]";
676 if (W == 1) {
677 args << "!";
678 }
Ian Rogers40627db2012-03-04 17:31:09 -0800679 }
680 }
Ian Rogers66a3fca2012-04-09 19:51:34 -0700681 } else {
682 // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm
683 ArmRegister Rn(instr, 16);
684 ArmRegister Rt(instr, 12);
685 ArmRegister Rm(instr, 0);
686 uint32_t imm2 = (instr >> 4) & 3;
687 opcode << "str.w";
688 args << Rt << ", [" << Rn << ", " << Rm;
689 if (imm2 != 0) {
690 args << ", lsl #" << imm2;
691 }
692 args << "]";
Ian Rogers40627db2012-03-04 17:31:09 -0800693 }
694 } else if (op3 == 6) {
Ian Rogers66a3fca2012-04-09 19:51:34 -0700695 // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800696 uint32_t imm12 = instr & 0xFFF;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700697 opcode << "str.w";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700698 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800699 }
Ian Rogers40627db2012-03-04 17:31:09 -0800700 break;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800701 }
702 }
703
704 break;
705 }
706 case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101
707 // Load word
708 // |111|11|10|0 0|00|0|0000|1111|110000|000000|
709 // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0|
710 // |---|--|--|---|--|-|----|----|------|------|
711 // |332|22|22|2 2|22|2|1111|1111|110000|000000|
712 // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0|
713 // |---|--|--|---|--|-|----|----|------|------|
714 // |111|11|00|op3|10|1| Rn | Rt | op4 | |
715 // |111|11| op2 | | | imm12 |
716 uint32_t op3 = (instr >> 23) & 3;
717 uint32_t op4 = (instr >> 6) & 0x3F;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700718 ArmRegister Rn(instr, 16);
719 ArmRegister Rt(instr, 12);
720 if (op3 == 1 || Rn.r == 15) {
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800721 // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii
722 // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii
723 uint32_t imm12 = instr & 0xFFF;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700724 opcode << "ldr.w";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700725 args << Rt << ", [" << Rn << ", #" << imm12 << "]";
Elliott Hughes28fa76d2012-04-09 17:31:46 -0700726 if (Rn.r == 9) {
727 args << " ; ";
728 Thread::DumpThreadOffset(args, imm12, 4);
Ian Rogers5b9b1bc2012-04-09 22:51:43 -0700729 } else if (Rn.r == 15) {
730 intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr);
731 lit_adr = RoundDown(lit_adr, 4) + 4 + imm12;
732 args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr));
Elliott Hughes28fa76d2012-04-09 17:31:46 -0700733 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800734 } else if (op4 == 0) {
735 // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm
736 uint32_t imm2 = (instr >> 4) & 0xF;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700737 ArmRegister rm(instr, 0);
Elliott Hughescbf0b612012-03-15 16:23:47 -0700738 opcode << "ldr.w";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700739 args << Rt << ", [" << Rn << ", " << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800740 if (imm2 != 0) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700741 args << ", lsl #" << imm2;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800742 }
Elliott Hughescbf0b612012-03-15 16:23:47 -0700743 args << "]";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800744 } else {
745 // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii
746 uint32_t imm8 = instr & 0xFF;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700747 opcode << "ldrt";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700748 args << Rt << ", [" << Rn << ", #" << imm8 << "]";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800749 }
750 break;
751 }
752 }
753 default:
754 break;
755 }
Elliott Hughescbf0b612012-03-15 16:23:47 -0700756 os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n';
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800757 return 4;
758}
759
760size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) {
761 uint16_t instr = ReadU16(instr_ptr);
762 bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800);
763 if (is_32bit) {
764 return DumpThumb32(os, instr_ptr);
765 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700766 std::ostringstream opcode;
767 std::ostringstream args;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800768 uint16_t opcode1 = instr >> 10;
769 if (opcode1 < 0x10) {
770 // shift (immediate), add, subtract, move, and compare
771 uint16_t opcode2 = instr >> 9;
772 switch (opcode2) {
773 case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
774 case 0x8: case 0x9: case 0xA: case 0xB: {
775 // Logical shift left - 00 000xx xxxxxxxxx
776 // Logical shift right - 00 001xx xxxxxxxxx
777 // Arithmetic shift right - 00 010xx xxxxxxxxx
778 uint16_t imm5 = (instr >> 6) & 0x1F;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700779 ThumbRegister rm(instr, 3);
780 ThumbRegister Rd(instr, 7);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800781 if (opcode2 <= 3) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700782 opcode << "lsls";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800783 } else if (opcode2 <= 7) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700784 opcode << "lsrs";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800785 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700786 opcode << "asrs";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800787 }
Elliott Hughes630e77d2012-03-22 19:20:56 -0700788 args << Rd << ", " << rm << ", #" << imm5;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800789 break;
790 }
791 case 0xC: case 0xD: case 0xE: case 0xF: {
792 // Add register - 00 01100 mmm nnn ddd
793 // Sub register - 00 01101 mmm nnn ddd
794 // Add 3-bit immediate - 00 01110 iii nnn ddd
795 // Sub 3-bit immediate - 00 01111 iii nnn ddd
796 uint16_t imm3_or_Rm = (instr >> 6) & 7;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700797 ThumbRegister Rn(instr, 3);
798 ThumbRegister Rd(instr, 0);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800799 if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700800 opcode << "mov";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800801 } else {
802 if ((opcode2 & 1) == 0) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700803 opcode << "adds";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800804 } else {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700805 opcode << "subs";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800806 }
807 }
Elliott Hughes630e77d2012-03-22 19:20:56 -0700808 args << Rd << ", " << Rn;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800809 if ((opcode2 & 2) == 0) {
Elliott Hughes630e77d2012-03-22 19:20:56 -0700810 ArmRegister Rm(imm3_or_Rm);
811 args << ", " << Rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800812 } else if (imm3_or_Rm != 0) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700813 args << ", #" << imm3_or_Rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800814 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800815 break;
816 }
817 case 0x10: case 0x11: case 0x12: case 0x13:
818 case 0x14: case 0x15: case 0x16: case 0x17:
819 case 0x18: case 0x19: case 0x1A: case 0x1B:
820 case 0x1C: case 0x1D: case 0x1E: case 0x1F: {
821 // MOVS Rd, #imm8 - 00100 ddd iiiiiiii
822 // CMP Rn, #imm8 - 00101 nnn iiiiiiii
823 // ADDS Rn, #imm8 - 00110 nnn iiiiiiii
824 // SUBS Rn, #imm8 - 00111 nnn iiiiiiii
Elliott Hughes630e77d2012-03-22 19:20:56 -0700825 ThumbRegister Rn(instr, 8);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800826 uint16_t imm8 = instr & 0xFF;
827 switch (opcode2 >> 2) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700828 case 4: opcode << "movs"; break;
829 case 5: opcode << "cmp"; break;
830 case 6: opcode << "adds"; break;
831 case 7: opcode << "subs"; break;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800832 }
Elliott Hughes630e77d2012-03-22 19:20:56 -0700833 args << Rn << ", #" << imm8;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800834 break;
835 }
836 default:
837 break;
838 }
Ian Rogersad03ef52012-03-18 19:34:47 -0700839 } else if (opcode1 == 0x10) {
840 // Data-processing
841 uint16_t opcode2 = (instr >> 6) & 0xF;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700842 ThumbRegister rm(instr, 3);
843 ThumbRegister rdn(instr, 0);
Ian Rogersad03ef52012-03-18 19:34:47 -0700844 opcode << kThumbDataProcessingOperations[opcode2];
Elliott Hughes630e77d2012-03-22 19:20:56 -0700845 args << rdn << ", " << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800846 } else if (opcode1 == 0x11) {
847 // Special data instructions and branch and exchange
848 uint16_t opcode2 = (instr >> 6) & 0x0F;
849 switch (opcode2) {
850 case 0x0: case 0x1: case 0x2: case 0x3: {
851 // Add low registers - 010001 0000 xxxxxx
852 // Add high registers - 010001 0001/001x xxxxxx
853 uint16_t DN = (instr >> 7) & 1;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700854 ArmRegister rm(instr, 3);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800855 uint16_t Rdn = instr & 7;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700856 ArmRegister DN_Rdn((DN << 3) | Rdn);
Elliott Hughescbf0b612012-03-15 16:23:47 -0700857 opcode << "add";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700858 args << DN_Rdn << ", " << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800859 break;
860 }
861 case 0x8: case 0x9: case 0xA: case 0xB: {
862 // Move low registers - 010001 1000 xxxxxx
863 // Move high registers - 010001 1001/101x xxxxxx
864 uint16_t DN = (instr >> 7) & 1;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700865 ArmRegister rm(instr, 3);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800866 uint16_t Rdn = instr & 7;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700867 ArmRegister DN_Rdn((DN << 3) | Rdn);
Elliott Hughescbf0b612012-03-15 16:23:47 -0700868 opcode << "mov";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700869 args << DN_Rdn << ", " << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800870 break;
871 }
872 case 0x5: case 0x6: case 0x7: {
873 // Compare high registers - 010001 0101/011x xxxxxx
874 uint16_t N = (instr >> 7) & 1;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700875 ArmRegister rm(instr, 3);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800876 uint16_t Rn = instr & 7;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700877 ArmRegister N_Rn((N << 3) | Rn);
Elliott Hughescbf0b612012-03-15 16:23:47 -0700878 opcode << "cmp";
Elliott Hughes630e77d2012-03-22 19:20:56 -0700879 args << N_Rn << ", " << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800880 break;
881 }
882 case 0xC: case 0xD: case 0xE: case 0xF: {
883 // Branch and exchange - 010001 110x xxxxxx
884 // Branch with link and exchange - 010001 111x xxxxxx
Elliott Hughes630e77d2012-03-22 19:20:56 -0700885 ArmRegister rm(instr, 3);
886 opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx");
887 args << rm;
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800888 break;
889 }
890 default:
891 break;
892 }
893 } else if ((instr & 0xF000) == 0xB000) {
894 // Miscellaneous 16-bit instructions
895 uint16_t opcode2 = (instr >> 5) & 0x7F;
896 switch (opcode2) {
897 case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: {
898 // Add immediate to SP - 1011 00000 ii iiiii
899 // Subtract immediate from SP - 1011 00001 ii iiiii
900 int imm7 = instr & 0x7F;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700901 opcode << ((opcode2 & 4) == 0 ? "add" : "sub");
Elliott Hughescbf0b612012-03-15 16:23:47 -0700902 args << "sp, sp, #" << (imm7 << 2);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800903 break;
904 }
Ian Rogers087b2412012-03-21 01:30:32 -0700905 case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx
Ian Rogersebbc5772012-04-11 17:00:08 -0700906 case 0x0C: case 0x0D: case 0x0E: case 0x0F:
907 case 0x48: case 0x49: case 0x4A: case 0x4B: // 1001xxx
908 case 0x4C: case 0x4D: case 0x4E: case 0x4F: {
Ian Rogers087b2412012-03-21 01:30:32 -0700909 // CBNZ, CBZ
910 uint16_t op = (instr >> 11) & 1;
911 uint16_t i = (instr >> 9) & 1;
912 uint16_t imm5 = (instr >> 3) & 0x1F;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700913 ThumbRegister Rn(instr, 0);
Ian Rogers087b2412012-03-21 01:30:32 -0700914 opcode << (op != 0 ? "cbnz" : "cbz");
915 uint32_t imm32 = (i << 7) | (imm5 << 1);
Elliott Hughes630e77d2012-03-22 19:20:56 -0700916 args << Rn << ", ";
Ian Rogers087b2412012-03-21 01:30:32 -0700917 DumpBranchTarget(args, instr_ptr + 4, imm32);
918 break;
919 }
Ian Rogers40627db2012-03-04 17:31:09 -0800920 case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx
921 case 0x7C: case 0x7D: case 0x7E: case 0x7F: {
922 // If-Then, and hints
923 uint16_t opA = (instr >> 4) & 0xF;
924 uint16_t opB = instr & 0xF;
925 if (opB == 0) {
926 switch (opA) {
Elliott Hughescbf0b612012-03-15 16:23:47 -0700927 case 0: opcode << "nop"; break;
928 case 1: opcode << "yield"; break;
929 case 2: opcode << "wfe"; break;
930 case 3: opcode << "sev"; break;
Ian Rogers40627db2012-03-04 17:31:09 -0800931 default: break;
932 }
933 } else {
Elliott Hughes105afd22012-04-10 15:04:25 -0700934 uint32_t first_cond = opA;
935 uint32_t mask = opB;
Elliott Hughescbf0b612012-03-15 16:23:47 -0700936 opcode << "it";
Elliott Hughes105afd22012-04-10 15:04:25 -0700937
938 // Flesh out the base "it" opcode with the specific collection of 't's and 'e's,
939 // and store up the actual condition codes we'll want to add to the next few opcodes.
940 size_t count = 3 - CTZ(mask);
941 it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself.
942 for (size_t i = 0; i < count; ++i) {
943 bool positive_cond = ((first_cond & 1) != 0);
944 bool positive_mask = ((mask & (1 << (3 - i))) != 0);
945 if (positive_mask == positive_cond) {
946 opcode << 't';
947 it_conditions_[i] = kConditionCodeNames[first_cond];
948 } else {
949 opcode << 'e';
950 it_conditions_[i] = kConditionCodeNames[first_cond ^ 1];
951 }
952 }
953 it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'.
954
955 it_conditions_[count + 1] = ""; // No condition code for the IT itself...
956 DumpCond(args, first_cond); // ...because it's considered an argument.
Ian Rogers40627db2012-03-04 17:31:09 -0800957 }
958 break;
959 }
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800960 default:
961 break;
962 }
963 } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) ||
964 ((instr & 0xE000) == 0x8000)) {
965 // Load/store single data item
966 uint16_t opA = instr >> 12;
967 //uint16_t opB = (instr >> 9) & 7;
968 switch (opA) {
969 case 0x6: {
Elliott Hughes28fa76d2012-04-09 17:31:46 -0700970 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
971 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800972 uint16_t imm5 = (instr >> 6) & 0x1F;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700973 ThumbRegister Rn(instr, 3);
Elliott Hughes28fa76d2012-04-09 17:31:46 -0700974 ThumbRegister Rt(instr, 0);
Elliott Hughes630e77d2012-03-22 19:20:56 -0700975 opcode << ((instr & 0x800) == 0 ? "str" : "ldr");
976 args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800977 break;
978 }
979 case 0x9: {
980 // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii
981 // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
982 uint16_t imm8 = instr & 0xFF;
Elliott Hughes630e77d2012-03-22 19:20:56 -0700983 ThumbRegister Rt(instr, 8);
984 opcode << ((instr & 0x800) == 0 ? "str" : "ldr");
985 args << Rt << ", [sp, #" << (imm8 << 2) << "]";
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800986 break;
987 }
988 default:
989 break;
990 }
Ian Rogers40627db2012-03-04 17:31:09 -0800991 } else if (opcode1 == 0x38 || opcode1 == 0x39) {
992 uint16_t imm11 = instr & 0x7FFF;
993 int32_t imm32 = imm11 << 1;
994 imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate
Elliott Hughescbf0b612012-03-15 16:23:47 -0700995 opcode << "b";
996 DumpBranchTarget(args, instr_ptr + 4, imm32);
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800997 }
Elliott Hughes105afd22012-04-10 15:04:25 -0700998
999 // Apply any IT-block conditions to the opcode if necessary.
1000 if (!it_conditions_.empty()) {
1001 opcode << it_conditions_.back();
1002 it_conditions_.pop_back();
1003 }
1004
Elliott Hughescbf0b612012-03-15 16:23:47 -07001005 os << StringPrintf("\t\t\t%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n';
Ian Rogers3a5c1ce2012-02-29 10:06:46 -08001006 }
1007 return 2;
1008}
1009
1010} // namespace arm
1011} // namespace art