Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 17 | #include "codegen_arm.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 21 | #include <string> |
| 22 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "dex/compiler_internals.h" |
| 24 | #include "dex/quick/mir_to_lir-inl.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | static int core_regs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10, |
| 29 | r11, r12, rARM_SP, rARM_LR, rARM_PC}; |
| 30 | static int ReservedRegs[] = {rARM_SUSPEND, rARM_SELF, rARM_SP, rARM_LR, rARM_PC}; |
| 31 | static int FpRegs[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, |
| 32 | fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, |
| 33 | fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, |
| 34 | fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31}; |
| 35 | static int core_temps[] = {r0, r1, r2, r3, r12}; |
| 36 | static int fp_temps[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, |
| 37 | fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15}; |
| 38 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 39 | RegLocation ArmMir2Lir::LocCReturn() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 40 | return arm_loc_c_return; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 41 | } |
| 42 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 43 | RegLocation ArmMir2Lir::LocCReturnWide() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 44 | return arm_loc_c_return_wide; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 45 | } |
| 46 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 47 | RegLocation ArmMir2Lir::LocCReturnFloat() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 48 | return arm_loc_c_return_float; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | } |
| 50 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 51 | RegLocation ArmMir2Lir::LocCReturnDouble() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 52 | return arm_loc_c_return_double; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | // Return a target-dependent special register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 56 | RegStorage ArmMir2Lir::TargetReg(SpecialTargetRegister reg) { |
| 57 | int res_reg = RegStorage::kInvalidRegVal; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | switch (reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 59 | case kSelf: res_reg = rARM_SELF; break; |
| 60 | case kSuspend: res_reg = rARM_SUSPEND; break; |
| 61 | case kLr: res_reg = rARM_LR; break; |
| 62 | case kPc: res_reg = rARM_PC; break; |
| 63 | case kSp: res_reg = rARM_SP; break; |
| 64 | case kArg0: res_reg = rARM_ARG0; break; |
| 65 | case kArg1: res_reg = rARM_ARG1; break; |
| 66 | case kArg2: res_reg = rARM_ARG2; break; |
| 67 | case kArg3: res_reg = rARM_ARG3; break; |
| 68 | case kFArg0: res_reg = rARM_FARG0; break; |
| 69 | case kFArg1: res_reg = rARM_FARG1; break; |
| 70 | case kFArg2: res_reg = rARM_FARG2; break; |
| 71 | case kFArg3: res_reg = rARM_FARG3; break; |
| 72 | case kRet0: res_reg = rARM_RET0; break; |
| 73 | case kRet1: res_reg = rARM_RET1; break; |
| 74 | case kInvokeTgt: res_reg = rARM_INVOKE_TGT; break; |
| 75 | case kHiddenArg: res_reg = r12; break; |
| 76 | case kHiddenFpArg: res_reg = RegStorage::kInvalidRegVal; break; |
| 77 | case kCount: res_reg = rARM_COUNT; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 78 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 79 | return RegStorage::Solo32(res_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | } |
| 81 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 82 | RegStorage ArmMir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 83 | // For the 32-bit internal ABI, the first 3 arguments are passed in registers. |
| 84 | switch (arg_num) { |
| 85 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 86 | return rs_rARM_ARG1; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 87 | case 1: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 88 | return rs_rARM_ARG2; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 89 | case 2: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 90 | return rs_rARM_ARG3; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 91 | default: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 92 | return RegStorage::InvalidReg(); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 93 | } |
| 94 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 95 | |
| 96 | // Create a double from a pair of singles. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 97 | int ArmMir2Lir::S2d(int low_reg, int high_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | return ARM_S2D(low_reg, high_reg); |
| 99 | } |
| 100 | |
| 101 | // Return mask to strip off fp reg flags and bias. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 102 | uint32_t ArmMir2Lir::FpRegMask() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 103 | return ARM_FP_REG_MASK; |
| 104 | } |
| 105 | |
| 106 | // True if both regs single, both core or both double. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 107 | bool ArmMir2Lir::SameRegType(int reg1, int reg2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 108 | return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2)); |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * Decode the register id. |
| 113 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 114 | uint64_t ArmMir2Lir::GetRegMaskCommon(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 115 | uint64_t seed; |
| 116 | int shift; |
| 117 | int reg_id; |
| 118 | |
| 119 | |
| 120 | reg_id = reg & 0x1f; |
| 121 | /* Each double register is equal to a pair of single-precision FP registers */ |
| 122 | seed = ARM_DOUBLEREG(reg) ? 3 : 1; |
| 123 | /* FP register starts at bit position 16 */ |
| 124 | shift = ARM_FPREG(reg) ? kArmFPReg0 : 0; |
| 125 | /* Expand the double register id into single offset */ |
| 126 | shift += reg_id; |
| 127 | return (seed << shift); |
| 128 | } |
| 129 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 130 | uint64_t ArmMir2Lir::GetPCUseDefEncoding() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 131 | return ENCODE_ARM_REG_PC; |
| 132 | } |
| 133 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 134 | // Thumb2 specific setup. TODO: inline?: |
| 135 | void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 136 | DCHECK_EQ(cu_->instruction_set, kThumb2); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 137 | DCHECK(!lir->flags.use_def_invalid); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 138 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | int opcode = lir->opcode; |
| 140 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 141 | // These flags are somewhat uncommon - bypass if we can. |
| 142 | if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LIST0 | REG_DEF_LIST1 | |
| 143 | REG_DEF_FPCS_LIST0 | REG_DEF_FPCS_LIST2 | REG_USE_PC | IS_IT | REG_USE_LIST0 | |
| 144 | REG_USE_LIST1 | REG_USE_FPCS_LIST0 | REG_USE_FPCS_LIST2 | REG_DEF_LR)) != 0) { |
| 145 | if (flags & REG_DEF_SP) { |
| 146 | lir->u.m.def_mask |= ENCODE_ARM_REG_SP; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 147 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 148 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 149 | if (flags & REG_USE_SP) { |
| 150 | lir->u.m.use_mask |= ENCODE_ARM_REG_SP; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 151 | } |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 152 | |
| 153 | if (flags & REG_DEF_LIST0) { |
| 154 | lir->u.m.def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 156 | |
| 157 | if (flags & REG_DEF_LIST1) { |
| 158 | lir->u.m.def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]); |
| 159 | } |
| 160 | |
| 161 | if (flags & REG_DEF_FPCS_LIST0) { |
| 162 | lir->u.m.def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]); |
| 163 | } |
| 164 | |
| 165 | if (flags & REG_DEF_FPCS_LIST2) { |
| 166 | for (int i = 0; i < lir->operands[2]; i++) { |
| 167 | SetupRegMask(&lir->u.m.def_mask, lir->operands[1] + i); |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | if (flags & REG_USE_PC) { |
| 172 | lir->u.m.use_mask |= ENCODE_ARM_REG_PC; |
| 173 | } |
| 174 | |
| 175 | /* Conservatively treat the IT block */ |
| 176 | if (flags & IS_IT) { |
| 177 | lir->u.m.def_mask = ENCODE_ALL; |
| 178 | } |
| 179 | |
| 180 | if (flags & REG_USE_LIST0) { |
| 181 | lir->u.m.use_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]); |
| 182 | } |
| 183 | |
| 184 | if (flags & REG_USE_LIST1) { |
| 185 | lir->u.m.use_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]); |
| 186 | } |
| 187 | |
| 188 | if (flags & REG_USE_FPCS_LIST0) { |
| 189 | lir->u.m.use_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]); |
| 190 | } |
| 191 | |
| 192 | if (flags & REG_USE_FPCS_LIST2) { |
| 193 | for (int i = 0; i < lir->operands[2]; i++) { |
| 194 | SetupRegMask(&lir->u.m.use_mask, lir->operands[1] + i); |
| 195 | } |
| 196 | } |
| 197 | /* Fixup for kThumbPush/lr and kThumbPop/pc */ |
| 198 | if (opcode == kThumbPush || opcode == kThumbPop) { |
| 199 | uint64_t r8Mask = GetRegMaskCommon(r8); |
| 200 | if ((opcode == kThumbPush) && (lir->u.m.use_mask & r8Mask)) { |
| 201 | lir->u.m.use_mask &= ~r8Mask; |
| 202 | lir->u.m.use_mask |= ENCODE_ARM_REG_LR; |
| 203 | } else if ((opcode == kThumbPop) && (lir->u.m.def_mask & r8Mask)) { |
| 204 | lir->u.m.def_mask &= ~r8Mask; |
| 205 | lir->u.m.def_mask |= ENCODE_ARM_REG_PC; |
| 206 | } |
| 207 | } |
| 208 | if (flags & REG_DEF_LR) { |
| 209 | lir->u.m.def_mask |= ENCODE_ARM_REG_LR; |
| 210 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 211 | } |
| 212 | } |
| 213 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 214 | ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 215 | ArmConditionCode res; |
| 216 | switch (ccode) { |
| 217 | case kCondEq: res = kArmCondEq; break; |
| 218 | case kCondNe: res = kArmCondNe; break; |
| 219 | case kCondCs: res = kArmCondCs; break; |
| 220 | case kCondCc: res = kArmCondCc; break; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 221 | case kCondUlt: res = kArmCondCc; break; |
| 222 | case kCondUge: res = kArmCondCs; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 223 | case kCondMi: res = kArmCondMi; break; |
| 224 | case kCondPl: res = kArmCondPl; break; |
| 225 | case kCondVs: res = kArmCondVs; break; |
| 226 | case kCondVc: res = kArmCondVc; break; |
| 227 | case kCondHi: res = kArmCondHi; break; |
| 228 | case kCondLs: res = kArmCondLs; break; |
| 229 | case kCondGe: res = kArmCondGe; break; |
| 230 | case kCondLt: res = kArmCondLt; break; |
| 231 | case kCondGt: res = kArmCondGt; break; |
| 232 | case kCondLe: res = kArmCondLe; break; |
| 233 | case kCondAl: res = kArmCondAl; break; |
| 234 | case kCondNv: res = kArmCondNv; break; |
| 235 | default: |
| 236 | LOG(FATAL) << "Bad condition code " << ccode; |
| 237 | res = static_cast<ArmConditionCode>(0); // Quiet gcc |
| 238 | } |
| 239 | return res; |
| 240 | } |
| 241 | |
| 242 | static const char* core_reg_names[16] = { |
| 243 | "r0", |
| 244 | "r1", |
| 245 | "r2", |
| 246 | "r3", |
| 247 | "r4", |
| 248 | "r5", |
| 249 | "r6", |
| 250 | "r7", |
| 251 | "r8", |
| 252 | "rSELF", |
| 253 | "r10", |
| 254 | "r11", |
| 255 | "r12", |
| 256 | "sp", |
| 257 | "lr", |
| 258 | "pc", |
| 259 | }; |
| 260 | |
| 261 | |
| 262 | static const char* shift_names[4] = { |
| 263 | "lsl", |
| 264 | "lsr", |
| 265 | "asr", |
| 266 | "ror"}; |
| 267 | |
| 268 | /* Decode and print a ARM register name */ |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 269 | static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 270 | int i; |
| 271 | bool printed = false; |
| 272 | buf[0] = 0; |
| 273 | for (i = 0; i < 16; i++, vector >>= 1) { |
| 274 | if (vector & 0x1) { |
| 275 | int reg_id = i; |
| 276 | if (opcode == kThumbPush && i == 8) { |
| 277 | reg_id = r14lr; |
| 278 | } else if (opcode == kThumbPop && i == 8) { |
| 279 | reg_id = r15pc; |
| 280 | } |
| 281 | if (printed) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 282 | snprintf(buf + strlen(buf), buf_size - strlen(buf), ", r%d", reg_id); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 283 | } else { |
| 284 | printed = true; |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 285 | snprintf(buf, buf_size, "r%d", reg_id); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 286 | } |
| 287 | } |
| 288 | } |
| 289 | return buf; |
| 290 | } |
| 291 | |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 292 | static char* DecodeFPCSRegList(int count, int base, char* buf, size_t buf_size) { |
| 293 | snprintf(buf, buf_size, "s%d", base); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 294 | for (int i = 1; i < count; i++) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 295 | snprintf(buf + strlen(buf), buf_size - strlen(buf), ", s%d", base + i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 296 | } |
| 297 | return buf; |
| 298 | } |
| 299 | |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 300 | static int32_t ExpandImmediate(int value) { |
| 301 | int32_t mode = (value & 0xf00) >> 8; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 302 | uint32_t bits = value & 0xff; |
| 303 | switch (mode) { |
| 304 | case 0: |
| 305 | return bits; |
| 306 | case 1: |
| 307 | return (bits << 16) | bits; |
| 308 | case 2: |
| 309 | return (bits << 24) | (bits << 8); |
| 310 | case 3: |
| 311 | return (bits << 24) | (bits << 16) | (bits << 8) | bits; |
| 312 | default: |
| 313 | break; |
| 314 | } |
| 315 | bits = (bits | 0x80) << 24; |
| 316 | return bits >> (((value & 0xf80) >> 7) - 8); |
| 317 | } |
| 318 | |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 319 | const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
| 320 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 321 | /* |
| 322 | * Interpret a format string and build a string no longer than size |
| 323 | * See format key in Assemble.c. |
| 324 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 325 | std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 326 | std::string buf; |
| 327 | int i; |
| 328 | const char* fmt_end = &fmt[strlen(fmt)]; |
| 329 | char tbuf[256]; |
| 330 | const char* name; |
| 331 | char nc; |
| 332 | while (fmt < fmt_end) { |
| 333 | int operand; |
| 334 | if (*fmt == '!') { |
| 335 | fmt++; |
| 336 | DCHECK_LT(fmt, fmt_end); |
| 337 | nc = *fmt++; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 338 | if (nc == '!') { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 339 | strcpy(tbuf, "!"); |
| 340 | } else { |
| 341 | DCHECK_LT(fmt, fmt_end); |
| 342 | DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); |
| 343 | operand = lir->operands[nc-'0']; |
| 344 | switch (*fmt++) { |
| 345 | case 'H': |
| 346 | if (operand != 0) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 347 | snprintf(tbuf, arraysize(tbuf), ", %s %d", shift_names[operand & 0x3], operand >> 2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 348 | } else { |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 349 | strcpy(tbuf, ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 350 | } |
| 351 | break; |
| 352 | case 'B': |
| 353 | switch (operand) { |
| 354 | case kSY: |
| 355 | name = "sy"; |
| 356 | break; |
| 357 | case kST: |
| 358 | name = "st"; |
| 359 | break; |
| 360 | case kISH: |
| 361 | name = "ish"; |
| 362 | break; |
| 363 | case kISHST: |
| 364 | name = "ishst"; |
| 365 | break; |
| 366 | case kNSH: |
| 367 | name = "nsh"; |
| 368 | break; |
| 369 | case kNSHST: |
| 370 | name = "shst"; |
| 371 | break; |
| 372 | default: |
| 373 | name = "DecodeError2"; |
| 374 | break; |
| 375 | } |
| 376 | strcpy(tbuf, name); |
| 377 | break; |
| 378 | case 'b': |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 379 | strcpy(tbuf, "0000"); |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 380 | for (i = 3; i >= 0; i--) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 381 | tbuf[i] += operand & 1; |
| 382 | operand >>= 1; |
| 383 | } |
| 384 | break; |
| 385 | case 'n': |
| 386 | operand = ~ExpandImmediate(operand); |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 387 | snprintf(tbuf, arraysize(tbuf), "%d [%#x]", operand, operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 388 | break; |
| 389 | case 'm': |
| 390 | operand = ExpandImmediate(operand); |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 391 | snprintf(tbuf, arraysize(tbuf), "%d [%#x]", operand, operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 392 | break; |
| 393 | case 's': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 394 | snprintf(tbuf, arraysize(tbuf), "s%d", operand & ARM_FP_REG_MASK); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 395 | break; |
| 396 | case 'S': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 397 | snprintf(tbuf, arraysize(tbuf), "d%d", (operand & ARM_FP_REG_MASK) >> 1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 398 | break; |
| 399 | case 'h': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 400 | snprintf(tbuf, arraysize(tbuf), "%04x", operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | break; |
| 402 | case 'M': |
| 403 | case 'd': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 404 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 405 | break; |
| 406 | case 'C': |
| 407 | DCHECK_LT(operand, static_cast<int>( |
| 408 | sizeof(core_reg_names)/sizeof(core_reg_names[0]))); |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 409 | snprintf(tbuf, arraysize(tbuf), "%s", core_reg_names[operand]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 410 | break; |
| 411 | case 'E': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 412 | snprintf(tbuf, arraysize(tbuf), "%d", operand*4); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 413 | break; |
| 414 | case 'F': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 415 | snprintf(tbuf, arraysize(tbuf), "%d", operand*2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 416 | break; |
| 417 | case 'c': |
| 418 | strcpy(tbuf, cc_names[operand]); |
| 419 | break; |
| 420 | case 't': |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 421 | snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", |
| 422 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 1), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 423 | lir->target); |
| 424 | break; |
| 425 | case 'u': { |
| 426 | int offset_1 = lir->operands[0]; |
| 427 | int offset_2 = NEXT_LIR(lir)->operands[0]; |
| 428 | uintptr_t target = |
| 429 | (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & |
| 430 | ~3) + (offset_1 << 21 >> 9) + (offset_2 << 1)) & |
| 431 | 0xfffffffc; |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 432 | snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast<void *>(target)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 433 | break; |
| 434 | } |
| 435 | |
| 436 | /* Nothing to print for BLX_2 */ |
| 437 | case 'v': |
| 438 | strcpy(tbuf, "see above"); |
| 439 | break; |
| 440 | case 'R': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 441 | DecodeRegList(lir->opcode, operand, tbuf, arraysize(tbuf)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 442 | break; |
| 443 | case 'P': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 444 | DecodeFPCSRegList(operand, 16, tbuf, arraysize(tbuf)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | break; |
| 446 | case 'Q': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 447 | DecodeFPCSRegList(operand, 0, tbuf, arraysize(tbuf)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 448 | break; |
| 449 | default: |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 450 | strcpy(tbuf, "DecodeError1"); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 451 | break; |
| 452 | } |
| 453 | buf += tbuf; |
| 454 | } |
| 455 | } else { |
| 456 | buf += *fmt++; |
| 457 | } |
| 458 | } |
| 459 | return buf; |
| 460 | } |
| 461 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 462 | void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 463 | char buf[256]; |
| 464 | buf[0] = 0; |
| 465 | |
| 466 | if (mask == ENCODE_ALL) { |
| 467 | strcpy(buf, "all"); |
| 468 | } else { |
| 469 | char num[8]; |
| 470 | int i; |
| 471 | |
| 472 | for (i = 0; i < kArmRegEnd; i++) { |
| 473 | if (mask & (1ULL << i)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 474 | snprintf(num, arraysize(num), "%d ", i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 475 | strcat(buf, num); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | if (mask & ENCODE_CCODE) { |
| 480 | strcat(buf, "cc "); |
| 481 | } |
| 482 | if (mask & ENCODE_FP_STATUS) { |
| 483 | strcat(buf, "fpcc "); |
| 484 | } |
| 485 | |
| 486 | /* Memory bits */ |
| 487 | if (arm_lir && (mask & ENCODE_DALVIK_REG)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 488 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 489 | DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), |
| 490 | DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 491 | } |
| 492 | if (mask & ENCODE_LITERAL) { |
| 493 | strcat(buf, "lit "); |
| 494 | } |
| 495 | |
| 496 | if (mask & ENCODE_HEAP_REF) { |
| 497 | strcat(buf, "heap "); |
| 498 | } |
| 499 | if (mask & ENCODE_MUST_NOT_ALIAS) { |
| 500 | strcat(buf, "noalias "); |
| 501 | } |
| 502 | } |
| 503 | if (buf[0]) { |
| 504 | LOG(INFO) << prefix << ": " << buf; |
| 505 | } |
| 506 | } |
| 507 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 508 | bool ArmMir2Lir::IsUnconditionalBranch(LIR* lir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 509 | return ((lir->opcode == kThumbBUncond) || (lir->opcode == kThumb2BUncond)); |
| 510 | } |
| 511 | |
| 512 | ArmMir2Lir::ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
| 513 | : Mir2Lir(cu, mir_graph, arena) { |
| 514 | // Sanity check - make sure encoding map lines up. |
| 515 | for (int i = 0; i < kArmLast; i++) { |
| 516 | if (ArmMir2Lir::EncodingMap[i].opcode != i) { |
| 517 | LOG(FATAL) << "Encoding order for " << ArmMir2Lir::EncodingMap[i].name |
| 518 | << " is wrong: expecting " << i << ", seeing " |
| 519 | << static_cast<int>(ArmMir2Lir::EncodingMap[i].opcode); |
| 520 | } |
| 521 | } |
| 522 | } |
| 523 | |
| 524 | Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 525 | ArenaAllocator* const arena) { |
| 526 | return new ArmMir2Lir(cu, mir_graph, arena); |
| 527 | } |
| 528 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 529 | // Alloc a pair of core registers, or a double. |
| 530 | RegStorage ArmMir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 531 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 532 | return AllocTempDouble(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 533 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 534 | RegStorage low_reg = AllocTemp(); |
| 535 | RegStorage high_reg = AllocTemp(); |
| 536 | return RegStorage::MakeRegPair(low_reg, high_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 537 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 538 | } |
| 539 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 540 | RegStorage ArmMir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 541 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) |
| 542 | return AllocTempFloat(); |
| 543 | return AllocTemp(); |
| 544 | } |
| 545 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 546 | void ArmMir2Lir::CompilerInitializeRegAlloc() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 547 | int num_regs = sizeof(core_regs)/sizeof(*core_regs); |
| 548 | int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); |
| 549 | int num_temps = sizeof(core_temps)/sizeof(*core_temps); |
| 550 | int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); |
| 551 | int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 552 | reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 553 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 554 | reg_pool_->num_core_regs = num_regs; |
| 555 | reg_pool_->core_regs = reinterpret_cast<RegisterInfo*> |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 556 | (arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 557 | reg_pool_->num_fp_regs = num_fp_regs; |
| 558 | reg_pool_->FPRegs = static_cast<RegisterInfo*> |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame] | 559 | (arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 560 | CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); |
| 561 | CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); |
| 562 | // Keep special registers from being allocated |
| 563 | for (int i = 0; i < num_reserved; i++) { |
| 564 | if (NO_SUSPEND && (ReservedRegs[i] == rARM_SUSPEND)) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 565 | // To measure cost of suspend check |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 566 | continue; |
| 567 | } |
| 568 | MarkInUse(ReservedRegs[i]); |
| 569 | } |
| 570 | // Mark temp regs - all others not in use can be used for promotion |
| 571 | for (int i = 0; i < num_temps; i++) { |
| 572 | MarkTemp(core_temps[i]); |
| 573 | } |
| 574 | for (int i = 0; i < num_fp_temps; i++) { |
| 575 | MarkTemp(fp_temps[i]); |
| 576 | } |
| 577 | |
| 578 | // Start allocation at r2 in an attempt to avoid clobbering return values |
| 579 | reg_pool_->next_core_reg = r2; |
| 580 | } |
| 581 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 582 | void ArmMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { |
| 583 | DCHECK(rl_keep.wide); |
| 584 | DCHECK(rl_free.wide); |
| 585 | if ((rl_free.reg.GetLowReg() != rl_keep.reg.GetLowReg()) && |
| 586 | (rl_free.reg.GetLowReg() != rl_keep.reg.GetHighReg()) && |
| 587 | (rl_free.reg.GetHighReg() != rl_keep.reg.GetLowReg()) && |
| 588 | (rl_free.reg.GetHighReg() != rl_keep.reg.GetHighReg())) { |
| 589 | // No overlap, free. |
| 590 | FreeTemp(rl_free.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 591 | } |
| 592 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 593 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 594 | /* |
| 595 | * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some |
| 596 | * instructions might call out to C/assembly helper functions. Until |
| 597 | * machinery is in place, always spill lr. |
| 598 | */ |
| 599 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 600 | void ArmMir2Lir::AdjustSpillMask() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 601 | core_spill_mask_ |= (1 << rARM_LR); |
| 602 | num_core_spills_++; |
| 603 | } |
| 604 | |
| 605 | /* |
| 606 | * Mark a callee-save fp register as promoted. Note that |
| 607 | * vpush/vpop uses contiguous register lists so we must |
| 608 | * include any holes in the mask. Associate holes with |
| 609 | * Dalvik register INVALID_VREG (0xFFFFU). |
| 610 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 611 | void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 612 | DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE); |
| 613 | reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE; |
| 614 | // Ensure fp_vmap_table is large enough |
| 615 | int table_size = fp_vmap_table_.size(); |
| 616 | for (int i = table_size; i < (reg + 1); i++) { |
| 617 | fp_vmap_table_.push_back(INVALID_VREG); |
| 618 | } |
| 619 | // Add the current mapping |
| 620 | fp_vmap_table_[reg] = v_reg; |
| 621 | // Size of fp_vmap_table is high-water mark, use to set mask |
| 622 | num_fp_spills_ = fp_vmap_table_.size(); |
| 623 | fp_spill_mask_ = ((1 << num_fp_spills_) - 1) << ARM_FP_CALLEE_SAVE_BASE; |
| 624 | } |
| 625 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 626 | void ArmMir2Lir::FlushRegWide(RegStorage reg) { |
| 627 | RegisterInfo* info1 = GetRegInfo(reg.GetLowReg()); |
| 628 | RegisterInfo* info2 = GetRegInfo(reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 629 | DCHECK(info1 && info2 && info1->pair && info2->pair && |
| 630 | (info1->partner == info2->reg) && |
| 631 | (info2->partner == info1->reg)); |
| 632 | if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { |
| 633 | if (!(info1->is_temp && info2->is_temp)) { |
| 634 | /* Should not happen. If it does, there's a problem in eval_loc */ |
| 635 | LOG(FATAL) << "Long half-temp, half-promoted"; |
| 636 | } |
| 637 | |
| 638 | info1->dirty = false; |
| 639 | info2->dirty = false; |
| 640 | if (mir_graph_->SRegToVReg(info2->s_reg) < |
| 641 | mir_graph_->SRegToVReg(info1->s_reg)) |
| 642 | info1 = info2; |
| 643 | int v_reg = mir_graph_->SRegToVReg(info1->s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 644 | StoreBaseDispWide(rs_rARM_SP, VRegOffset(v_reg), |
| 645 | RegStorage(RegStorage::k64BitPair, info1->reg, info1->partner)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 649 | void ArmMir2Lir::FlushReg(RegStorage reg) { |
| 650 | DCHECK(!reg.IsPair()); |
| 651 | RegisterInfo* info = GetRegInfo(reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 652 | if (info->live && info->dirty) { |
| 653 | info->dirty = false; |
| 654 | int v_reg = mir_graph_->SRegToVReg(info->s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 655 | StoreBaseDisp(rs_rARM_SP, VRegOffset(v_reg), reg, kWord); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 656 | } |
| 657 | } |
| 658 | |
| 659 | /* Give access to the target-dependent FP register encoding to common code */ |
| 660 | bool ArmMir2Lir::IsFpReg(int reg) { |
| 661 | return ARM_FPREG(reg); |
| 662 | } |
| 663 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 664 | bool ArmMir2Lir::IsFpReg(RegStorage reg) { |
| 665 | return IsFpReg(reg.IsPair() ? reg.GetLowReg() : reg.GetReg()); |
| 666 | } |
| 667 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 668 | /* Clobber all regs that might be used by an external C call */ |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 669 | void ArmMir2Lir::ClobberCallerSave() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 670 | Clobber(r0); |
| 671 | Clobber(r1); |
| 672 | Clobber(r2); |
| 673 | Clobber(r3); |
| 674 | Clobber(r12); |
| 675 | Clobber(r14lr); |
| 676 | Clobber(fr0); |
| 677 | Clobber(fr1); |
| 678 | Clobber(fr2); |
| 679 | Clobber(fr3); |
| 680 | Clobber(fr4); |
| 681 | Clobber(fr5); |
| 682 | Clobber(fr6); |
| 683 | Clobber(fr7); |
| 684 | Clobber(fr8); |
| 685 | Clobber(fr9); |
| 686 | Clobber(fr10); |
| 687 | Clobber(fr11); |
| 688 | Clobber(fr12); |
| 689 | Clobber(fr13); |
| 690 | Clobber(fr14); |
| 691 | Clobber(fr15); |
| 692 | } |
| 693 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 694 | RegLocation ArmMir2Lir::GetReturnWideAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 695 | RegLocation res = LocCReturnWide(); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 696 | res.reg.SetReg(r2); |
| 697 | res.reg.SetHighReg(r3); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | Clobber(r2); |
| 699 | Clobber(r3); |
| 700 | MarkInUse(r2); |
| 701 | MarkInUse(r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 702 | MarkPair(res.reg.GetLowReg(), res.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 703 | return res; |
| 704 | } |
| 705 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 706 | RegLocation ArmMir2Lir::GetReturnAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 707 | RegLocation res = LocCReturn(); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 708 | res.reg.SetReg(r1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 709 | Clobber(r1); |
| 710 | MarkInUse(r1); |
| 711 | return res; |
| 712 | } |
| 713 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 714 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 715 | void ArmMir2Lir::LockCallTemps() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 716 | LockTemp(r0); |
| 717 | LockTemp(r1); |
| 718 | LockTemp(r2); |
| 719 | LockTemp(r3); |
| 720 | } |
| 721 | |
| 722 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 723 | void ArmMir2Lir::FreeCallTemps() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 724 | FreeTemp(r0); |
| 725 | FreeTemp(r1); |
| 726 | FreeTemp(r2); |
| 727 | FreeTemp(r3); |
| 728 | } |
| 729 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 730 | RegStorage ArmMir2Lir::LoadHelper(ThreadOffset offset) { |
| 731 | LoadWordDisp(rs_rARM_SELF, offset.Int32Value(), rs_rARM_LR); |
| 732 | return rs_rARM_LR; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 733 | } |
| 734 | |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 735 | LIR* ArmMir2Lir::CheckSuspendUsingLoad() { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame^] | 736 | RegStorage tmp = rs_r0; |
| 737 | LoadWordDisp(rs_rARM_SELF, Thread::ThreadSuspendTriggerOffset().Int32Value(), tmp); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 738 | LIR* load2 = LoadWordDisp(tmp, 0, tmp); |
| 739 | return load2; |
| 740 | } |
| 741 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 742 | uint64_t ArmMir2Lir::GetTargetInstFlags(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 743 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 744 | return ArmMir2Lir::EncodingMap[opcode].flags; |
| 745 | } |
| 746 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 747 | const char* ArmMir2Lir::GetTargetInstName(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 748 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 749 | return ArmMir2Lir::EncodingMap[opcode].name; |
| 750 | } |
| 751 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 752 | const char* ArmMir2Lir::GetTargetInstFmt(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 753 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 754 | return ArmMir2Lir::EncodingMap[opcode].fmt; |
| 755 | } |
| 756 | |
| 757 | } // namespace art |