Elliott Hughes | 2faa5f1 | 2012-01-30 14:42:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 16 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |
| 18 | #define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 19 | |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 20 | #include <vector> |
Elliott Hughes | 7616005 | 2012-12-12 16:31:20 -0800 | [diff] [blame] | 21 | #include "base/macros.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 22 | #include "constants_x86.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 23 | #include "globals.h" |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 24 | #include "managed_register_x86.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 25 | #include "offsets.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 26 | #include "utils/assembler.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 27 | #include "utils.h" |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 28 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 29 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 30 | namespace x86 { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 31 | |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 32 | class Immediate : public ValueObject { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 33 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 34 | explicit Immediate(int32_t value_in) : value_(value_in) {} |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 35 | |
| 36 | int32_t value() const { return value_; } |
| 37 | |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 38 | bool is_int8() const { return IsInt<8>(value_); } |
| 39 | bool is_uint8() const { return IsUint<8>(value_); } |
| 40 | bool is_int16() const { return IsInt<16>(value_); } |
| 41 | bool is_uint16() const { return IsUint<16>(value_); } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 42 | |
| 43 | private: |
| 44 | const int32_t value_; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 48 | class Operand : public ValueObject { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 49 | public: |
| 50 | uint8_t mod() const { |
| 51 | return (encoding_at(0) >> 6) & 3; |
| 52 | } |
| 53 | |
| 54 | Register rm() const { |
| 55 | return static_cast<Register>(encoding_at(0) & 7); |
| 56 | } |
| 57 | |
| 58 | ScaleFactor scale() const { |
| 59 | return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); |
| 60 | } |
| 61 | |
| 62 | Register index() const { |
| 63 | return static_cast<Register>((encoding_at(1) >> 3) & 7); |
| 64 | } |
| 65 | |
| 66 | Register base() const { |
| 67 | return static_cast<Register>(encoding_at(1) & 7); |
| 68 | } |
| 69 | |
| 70 | int8_t disp8() const { |
| 71 | CHECK_GE(length_, 2); |
| 72 | return static_cast<int8_t>(encoding_[length_ - 1]); |
| 73 | } |
| 74 | |
| 75 | int32_t disp32() const { |
| 76 | CHECK_GE(length_, 5); |
| 77 | int32_t value; |
| 78 | memcpy(&value, &encoding_[length_ - 4], sizeof(value)); |
| 79 | return value; |
| 80 | } |
| 81 | |
| 82 | bool IsRegister(Register reg) const { |
| 83 | return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only. |
| 84 | && ((encoding_[0] & 0x07) == reg); // Register codes match. |
| 85 | } |
| 86 | |
| 87 | protected: |
| 88 | // Operand can be sub classed (e.g: Address). |
| 89 | Operand() : length_(0) { } |
| 90 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 91 | void SetModRM(int mod_in, Register rm_in) { |
| 92 | CHECK_EQ(mod_in & ~3, 0); |
| 93 | encoding_[0] = (mod_in << 6) | rm_in; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 94 | length_ = 1; |
| 95 | } |
| 96 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 97 | void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 98 | CHECK_EQ(length_, 1); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 99 | CHECK_EQ(scale_in & ~3, 0); |
| 100 | encoding_[1] = (scale_in << 6) | (index_in << 3) | base_in; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 101 | length_ = 2; |
| 102 | } |
| 103 | |
| 104 | void SetDisp8(int8_t disp) { |
| 105 | CHECK(length_ == 1 || length_ == 2); |
| 106 | encoding_[length_++] = static_cast<uint8_t>(disp); |
| 107 | } |
| 108 | |
| 109 | void SetDisp32(int32_t disp) { |
| 110 | CHECK(length_ == 1 || length_ == 2); |
| 111 | int disp_size = sizeof(disp); |
| 112 | memmove(&encoding_[length_], &disp, disp_size); |
| 113 | length_ += disp_size; |
| 114 | } |
| 115 | |
| 116 | private: |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 117 | uint8_t length_; |
| 118 | uint8_t encoding_[6]; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 119 | |
| 120 | explicit Operand(Register reg) { SetModRM(3, reg); } |
| 121 | |
| 122 | // Get the operand encoding byte at the given index. |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 123 | uint8_t encoding_at(int index_in) const { |
| 124 | CHECK_GE(index_in, 0); |
| 125 | CHECK_LT(index_in, length_); |
| 126 | return encoding_[index_in]; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 127 | } |
| 128 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 129 | friend class X86Assembler; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | |
| 133 | class Address : public Operand { |
| 134 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 135 | Address(Register base_in, int32_t disp) { |
| 136 | Init(base_in, disp); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 139 | Address(Register base_in, Offset disp) { |
| 140 | Init(base_in, disp.Int32Value()); |
Ian Rogers | a04d397 | 2011-08-17 11:33:44 -0700 | [diff] [blame] | 141 | } |
| 142 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 143 | Address(Register base_in, FrameOffset disp) { |
| 144 | CHECK_EQ(base_in, ESP); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 145 | Init(ESP, disp.Int32Value()); |
| 146 | } |
| 147 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 148 | Address(Register base_in, MemberOffset disp) { |
| 149 | Init(base_in, disp.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 152 | void Init(Register base_in, int32_t disp) { |
| 153 | if (disp == 0 && base_in != EBP) { |
| 154 | SetModRM(0, base_in); |
| 155 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 156 | } else if (disp >= -128 && disp <= 127) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 157 | SetModRM(1, base_in); |
| 158 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 159 | SetDisp8(disp); |
| 160 | } else { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 161 | SetModRM(2, base_in); |
| 162 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 163 | SetDisp32(disp); |
| 164 | } |
| 165 | } |
| 166 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 167 | Address(Register index_in, ScaleFactor scale_in, int32_t disp) { |
| 168 | CHECK_NE(index_in, ESP); // Illegal addressing mode. |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 169 | SetModRM(0, ESP); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 170 | SetSIB(scale_in, index_in, EBP); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 171 | SetDisp32(disp); |
| 172 | } |
| 173 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 174 | Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) { |
| 175 | CHECK_NE(index_in, ESP); // Illegal addressing mode. |
| 176 | if (disp == 0 && base_in != EBP) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 177 | SetModRM(0, ESP); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 178 | SetSIB(scale_in, index_in, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 179 | } else if (disp >= -128 && disp <= 127) { |
| 180 | SetModRM(1, ESP); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 181 | SetSIB(scale_in, index_in, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 182 | SetDisp8(disp); |
| 183 | } else { |
| 184 | SetModRM(2, ESP); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 185 | SetSIB(scale_in, index_in, base_in); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 186 | SetDisp32(disp); |
| 187 | } |
| 188 | } |
| 189 | |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 190 | static Address Absolute(uintptr_t addr) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 191 | Address result; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 192 | result.SetModRM(0, EBP); |
| 193 | result.SetDisp32(addr); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 194 | return result; |
| 195 | } |
| 196 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 197 | static Address Absolute(ThreadOffset<4> addr) { |
| 198 | return Absolute(addr.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 199 | } |
| 200 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 201 | private: |
| 202 | Address() {} |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 203 | }; |
| 204 | |
| 205 | |
Ian Rogers | befbd57 | 2014-03-06 01:13:39 -0800 | [diff] [blame] | 206 | class X86Assembler FINAL : public Assembler { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 207 | public: |
David Srbecky | 8c57831 | 2015-04-07 19:46:22 +0100 | [diff] [blame] | 208 | explicit X86Assembler() {} |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 209 | virtual ~X86Assembler() {} |
buzbee | c143c55 | 2011-08-20 17:38:58 -0700 | [diff] [blame] | 210 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 211 | /* |
| 212 | * Emit Machine Instructions. |
| 213 | */ |
| 214 | void call(Register reg); |
| 215 | void call(const Address& address); |
| 216 | void call(Label* label); |
Nicolas Geoffray | 8ccc3f5 | 2014-03-19 10:34:11 +0000 | [diff] [blame] | 217 | void call(const ExternalLabel& label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 218 | |
| 219 | void pushl(Register reg); |
| 220 | void pushl(const Address& address); |
| 221 | void pushl(const Immediate& imm); |
| 222 | |
| 223 | void popl(Register reg); |
| 224 | void popl(const Address& address); |
| 225 | |
| 226 | void movl(Register dst, const Immediate& src); |
| 227 | void movl(Register dst, Register src); |
| 228 | |
| 229 | void movl(Register dst, const Address& src); |
| 230 | void movl(const Address& dst, Register src); |
| 231 | void movl(const Address& dst, const Immediate& imm); |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 232 | void movl(const Address& dst, Label* lbl); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 233 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 234 | void bswapl(Register dst); |
| 235 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 236 | void movzxb(Register dst, ByteRegister src); |
| 237 | void movzxb(Register dst, const Address& src); |
| 238 | void movsxb(Register dst, ByteRegister src); |
| 239 | void movsxb(Register dst, const Address& src); |
| 240 | void movb(Register dst, const Address& src); |
| 241 | void movb(const Address& dst, ByteRegister src); |
| 242 | void movb(const Address& dst, const Immediate& imm); |
| 243 | |
| 244 | void movzxw(Register dst, Register src); |
| 245 | void movzxw(Register dst, const Address& src); |
| 246 | void movsxw(Register dst, Register src); |
| 247 | void movsxw(Register dst, const Address& src); |
| 248 | void movw(Register dst, const Address& src); |
| 249 | void movw(const Address& dst, Register src); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 250 | void movw(const Address& dst, const Immediate& imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 251 | |
| 252 | void leal(Register dst, const Address& src); |
| 253 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 254 | void cmovl(Condition condition, Register dst, Register src); |
| 255 | |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 256 | void setb(Condition condition, Register dst); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 257 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 258 | void movaps(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 259 | void movss(XmmRegister dst, const Address& src); |
| 260 | void movss(const Address& dst, XmmRegister src); |
| 261 | void movss(XmmRegister dst, XmmRegister src); |
| 262 | |
| 263 | void movd(XmmRegister dst, Register src); |
| 264 | void movd(Register dst, XmmRegister src); |
| 265 | |
| 266 | void addss(XmmRegister dst, XmmRegister src); |
| 267 | void addss(XmmRegister dst, const Address& src); |
| 268 | void subss(XmmRegister dst, XmmRegister src); |
| 269 | void subss(XmmRegister dst, const Address& src); |
| 270 | void mulss(XmmRegister dst, XmmRegister src); |
| 271 | void mulss(XmmRegister dst, const Address& src); |
| 272 | void divss(XmmRegister dst, XmmRegister src); |
| 273 | void divss(XmmRegister dst, const Address& src); |
| 274 | |
| 275 | void movsd(XmmRegister dst, const Address& src); |
| 276 | void movsd(const Address& dst, XmmRegister src); |
| 277 | void movsd(XmmRegister dst, XmmRegister src); |
| 278 | |
Calin Juravle | 52c4896 | 2014-12-16 17:02:57 +0000 | [diff] [blame] | 279 | void psrlq(XmmRegister reg, const Immediate& shift_count); |
| 280 | void punpckldq(XmmRegister dst, XmmRegister src); |
| 281 | |
Nicolas Geoffray | 234d69d | 2015-03-09 10:28:50 +0000 | [diff] [blame] | 282 | void movhpd(XmmRegister dst, const Address& src); |
| 283 | void movhpd(const Address& dst, XmmRegister src); |
| 284 | |
| 285 | void psrldq(XmmRegister reg, const Immediate& shift_count); |
| 286 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 287 | void addsd(XmmRegister dst, XmmRegister src); |
| 288 | void addsd(XmmRegister dst, const Address& src); |
| 289 | void subsd(XmmRegister dst, XmmRegister src); |
| 290 | void subsd(XmmRegister dst, const Address& src); |
| 291 | void mulsd(XmmRegister dst, XmmRegister src); |
| 292 | void mulsd(XmmRegister dst, const Address& src); |
| 293 | void divsd(XmmRegister dst, XmmRegister src); |
| 294 | void divsd(XmmRegister dst, const Address& src); |
| 295 | |
| 296 | void cvtsi2ss(XmmRegister dst, Register src); |
| 297 | void cvtsi2sd(XmmRegister dst, Register src); |
| 298 | |
| 299 | void cvtss2si(Register dst, XmmRegister src); |
| 300 | void cvtss2sd(XmmRegister dst, XmmRegister src); |
| 301 | |
| 302 | void cvtsd2si(Register dst, XmmRegister src); |
| 303 | void cvtsd2ss(XmmRegister dst, XmmRegister src); |
| 304 | |
| 305 | void cvttss2si(Register dst, XmmRegister src); |
| 306 | void cvttsd2si(Register dst, XmmRegister src); |
| 307 | |
| 308 | void cvtdq2pd(XmmRegister dst, XmmRegister src); |
| 309 | |
| 310 | void comiss(XmmRegister a, XmmRegister b); |
| 311 | void comisd(XmmRegister a, XmmRegister b); |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 312 | void ucomiss(XmmRegister a, XmmRegister b); |
| 313 | void ucomisd(XmmRegister a, XmmRegister b); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 314 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 315 | void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 316 | void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 317 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 318 | void sqrtsd(XmmRegister dst, XmmRegister src); |
| 319 | void sqrtss(XmmRegister dst, XmmRegister src); |
| 320 | |
| 321 | void xorpd(XmmRegister dst, const Address& src); |
| 322 | void xorpd(XmmRegister dst, XmmRegister src); |
| 323 | void xorps(XmmRegister dst, const Address& src); |
| 324 | void xorps(XmmRegister dst, XmmRegister src); |
| 325 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 326 | void andpd(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 327 | void andpd(XmmRegister dst, const Address& src); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 328 | void andps(XmmRegister dst, XmmRegister src); |
| 329 | void andps(XmmRegister dst, const Address& src); |
| 330 | |
| 331 | void orpd(XmmRegister dst, XmmRegister src); |
| 332 | void orps(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 333 | |
| 334 | void flds(const Address& src); |
| 335 | void fstps(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 336 | void fsts(const Address& dst); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 337 | |
| 338 | void fldl(const Address& src); |
| 339 | void fstpl(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 340 | void fstl(const Address& dst); |
| 341 | |
| 342 | void fstsw(); |
| 343 | |
| 344 | void fucompp(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 345 | |
| 346 | void fnstcw(const Address& dst); |
| 347 | void fldcw(const Address& src); |
| 348 | |
| 349 | void fistpl(const Address& dst); |
| 350 | void fistps(const Address& dst); |
| 351 | void fildl(const Address& src); |
Serguei Katkov | 2d45b4d | 2015-04-07 17:04:50 +0600 | [diff] [blame^] | 352 | void filds(const Address& src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 353 | |
| 354 | void fincstp(); |
| 355 | void ffree(const Immediate& index); |
| 356 | |
| 357 | void fsin(); |
| 358 | void fcos(); |
| 359 | void fptan(); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 360 | void fprem(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 361 | |
| 362 | void xchgl(Register dst, Register src); |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 363 | void xchgl(Register reg, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 364 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 365 | void cmpw(const Address& address, const Immediate& imm); |
| 366 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 367 | void cmpl(Register reg, const Immediate& imm); |
| 368 | void cmpl(Register reg0, Register reg1); |
| 369 | void cmpl(Register reg, const Address& address); |
| 370 | |
| 371 | void cmpl(const Address& address, Register reg); |
| 372 | void cmpl(const Address& address, const Immediate& imm); |
| 373 | |
| 374 | void testl(Register reg1, Register reg2); |
| 375 | void testl(Register reg, const Immediate& imm); |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 376 | void testl(Register reg1, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 377 | |
| 378 | void andl(Register dst, const Immediate& imm); |
| 379 | void andl(Register dst, Register src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 380 | void andl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 381 | |
| 382 | void orl(Register dst, const Immediate& imm); |
| 383 | void orl(Register dst, Register src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 384 | void orl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 385 | |
| 386 | void xorl(Register dst, Register src); |
Nicolas Geoffray | b55f835 | 2014-04-07 15:26:35 +0100 | [diff] [blame] | 387 | void xorl(Register dst, const Immediate& imm); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 388 | void xorl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 389 | |
| 390 | void addl(Register dst, Register src); |
| 391 | void addl(Register reg, const Immediate& imm); |
| 392 | void addl(Register reg, const Address& address); |
| 393 | |
| 394 | void addl(const Address& address, Register reg); |
| 395 | void addl(const Address& address, const Immediate& imm); |
| 396 | |
| 397 | void adcl(Register dst, Register src); |
| 398 | void adcl(Register reg, const Immediate& imm); |
| 399 | void adcl(Register dst, const Address& address); |
| 400 | |
| 401 | void subl(Register dst, Register src); |
| 402 | void subl(Register reg, const Immediate& imm); |
| 403 | void subl(Register reg, const Address& address); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 404 | void subl(const Address& address, Register src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 405 | |
| 406 | void cdq(); |
| 407 | |
| 408 | void idivl(Register reg); |
| 409 | |
| 410 | void imull(Register dst, Register src); |
| 411 | void imull(Register reg, const Immediate& imm); |
| 412 | void imull(Register reg, const Address& address); |
| 413 | |
| 414 | void imull(Register reg); |
| 415 | void imull(const Address& address); |
| 416 | |
| 417 | void mull(Register reg); |
| 418 | void mull(const Address& address); |
| 419 | |
| 420 | void sbbl(Register dst, Register src); |
| 421 | void sbbl(Register reg, const Immediate& imm); |
| 422 | void sbbl(Register reg, const Address& address); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 423 | void sbbl(const Address& address, Register src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 424 | |
| 425 | void incl(Register reg); |
| 426 | void incl(const Address& address); |
| 427 | |
| 428 | void decl(Register reg); |
| 429 | void decl(const Address& address); |
| 430 | |
| 431 | void shll(Register reg, const Immediate& imm); |
| 432 | void shll(Register operand, Register shifter); |
| 433 | void shrl(Register reg, const Immediate& imm); |
| 434 | void shrl(Register operand, Register shifter); |
| 435 | void sarl(Register reg, const Immediate& imm); |
| 436 | void sarl(Register operand, Register shifter); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 437 | void shld(Register dst, Register src, Register shifter); |
| 438 | void shrd(Register dst, Register src, Register shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 439 | |
| 440 | void negl(Register reg); |
| 441 | void notl(Register reg); |
| 442 | |
| 443 | void enter(const Immediate& imm); |
| 444 | void leave(); |
| 445 | |
| 446 | void ret(); |
| 447 | void ret(const Immediate& imm); |
| 448 | |
| 449 | void nop(); |
| 450 | void int3(); |
| 451 | void hlt(); |
| 452 | |
| 453 | void j(Condition condition, Label* label); |
| 454 | |
| 455 | void jmp(Register reg); |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 456 | void jmp(const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 457 | void jmp(Label* label); |
| 458 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 459 | X86Assembler* lock(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 460 | void cmpxchgl(const Address& address, Register reg); |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 461 | void cmpxchg8b(const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 462 | |
Elliott Hughes | 79ab9e3 | 2012-03-12 15:41:35 -0700 | [diff] [blame] | 463 | void mfence(); |
| 464 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 465 | X86Assembler* fs(); |
Ian Rogers | befbd57 | 2014-03-06 01:13:39 -0800 | [diff] [blame] | 466 | X86Assembler* gs(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 467 | |
| 468 | // |
| 469 | // Macros for High-level operations. |
| 470 | // |
| 471 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 472 | void AddImmediate(Register reg, const Immediate& imm); |
| 473 | |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 474 | void LoadLongConstant(XmmRegister dst, int64_t value); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 475 | void LoadDoubleConstant(XmmRegister dst, double value); |
| 476 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 477 | void LockCmpxchgl(const Address& address, Register reg) { |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 478 | lock()->cmpxchgl(address, reg); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 479 | } |
| 480 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 481 | void LockCmpxchg8b(const Address& address) { |
| 482 | lock()->cmpxchg8b(address); |
| 483 | } |
| 484 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 485 | // |
| 486 | // Misc. functionality |
| 487 | // |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 488 | int PreferredLoopAlignment() { return 16; } |
| 489 | void Align(int alignment, int offset); |
| 490 | void Bind(Label* label); |
| 491 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 492 | // |
| 493 | // Overridden common assembler high-level functionality |
| 494 | // |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 495 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 496 | // Emit code that will create an activation on the stack |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 497 | void BuildFrame(size_t frame_size, ManagedRegister method_reg, |
| 498 | const std::vector<ManagedRegister>& callee_save_regs, |
| 499 | const ManagedRegisterEntrySpills& entry_spills) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 500 | |
| 501 | // Emit code that will remove an activation from the stack |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 502 | void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs) |
| 503 | OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 504 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 505 | void IncreaseFrameSize(size_t adjust) OVERRIDE; |
| 506 | void DecreaseFrameSize(size_t adjust) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 507 | |
| 508 | // Store routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 509 | void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE; |
| 510 | void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE; |
| 511 | void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 512 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 513 | void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 514 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 515 | void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister scratch) |
| 516 | OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 517 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 518 | void StoreStackOffsetToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, |
| 519 | ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 520 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 521 | void StoreStackPointerToThread32(ThreadOffset<4> thr_offs) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 522 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 523 | void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off, |
| 524 | ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 525 | |
| 526 | // Load routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 527 | void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 528 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 529 | void LoadFromThread32(ManagedRegister dest, ThreadOffset<4> src, size_t size) OVERRIDE; |
Ian Rogers | 5a7a74a | 2011-09-26 16:32:29 -0700 | [diff] [blame] | 530 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 531 | void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 532 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 533 | void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 534 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 535 | void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 536 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 537 | void LoadRawPtrFromThread32(ManagedRegister dest, ThreadOffset<4> offs) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 538 | |
| 539 | // Copying routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 540 | void Move(ManagedRegister dest, ManagedRegister src, size_t size) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 541 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 542 | void CopyRawPtrFromThread32(FrameOffset fr_offs, ThreadOffset<4> thr_offs, |
| 543 | ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 544 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 545 | void CopyRawPtrToThread32(ThreadOffset<4> thr_offs, FrameOffset fr_offs, ManagedRegister scratch) |
| 546 | OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 547 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 548 | void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 549 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 550 | void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 551 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 552 | void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch, |
| 553 | size_t size) OVERRIDE; |
Ian Rogers | dc51b79 | 2011-09-22 20:41:37 -0700 | [diff] [blame] | 554 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 555 | void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch, |
| 556 | size_t size) OVERRIDE; |
Ian Rogers | 5a7a74a | 2011-09-26 16:32:29 -0700 | [diff] [blame] | 557 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 558 | void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch, |
| 559 | size_t size) OVERRIDE; |
Ian Rogers | dc51b79 | 2011-09-22 20:41:37 -0700 | [diff] [blame] | 560 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 561 | void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset, |
| 562 | ManagedRegister scratch, size_t size) OVERRIDE; |
Ian Rogers | 5a7a74a | 2011-09-26 16:32:29 -0700 | [diff] [blame] | 563 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 564 | void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, |
| 565 | ManagedRegister scratch, size_t size) OVERRIDE; |
Ian Rogers | dc51b79 | 2011-09-22 20:41:37 -0700 | [diff] [blame] | 566 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 567 | void MemoryBarrier(ManagedRegister) OVERRIDE; |
Ian Rogers | e5de95b | 2011-09-18 20:31:38 -0700 | [diff] [blame] | 568 | |
jeffhao | 58136ca | 2012-05-24 13:40:11 -0700 | [diff] [blame] | 569 | // Sign extension |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 570 | void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
jeffhao | 58136ca | 2012-05-24 13:40:11 -0700 | [diff] [blame] | 571 | |
jeffhao | cee4d0c | 2012-06-15 14:42:01 -0700 | [diff] [blame] | 572 | // Zero extension |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 573 | void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
jeffhao | cee4d0c | 2012-06-15 14:42:01 -0700 | [diff] [blame] | 574 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 575 | // Exploit fast access in managed code to Thread::Current() |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 576 | void GetCurrentThread(ManagedRegister tr) OVERRIDE; |
| 577 | void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 578 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 579 | // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 580 | // value is null and null_allowed. in_reg holds a possibly stale reference |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 581 | // that can be used to avoid loading the handle scope entry to see if the value is |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 582 | // NULL. |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 583 | void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, ManagedRegister in_reg, |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 584 | bool null_allowed) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 585 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 586 | // Set up out_off to hold a Object** into the handle scope, or to be NULL if the |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 587 | // value is null and null_allowed. |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 588 | void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister scratch, |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 589 | bool null_allowed) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 590 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 591 | // src holds a handle scope entry (Object**) load this into dst |
| 592 | void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 593 | |
| 594 | // Heap::VerifyObject on src. In some cases (such as a reference to this) we |
| 595 | // know that src may not be null. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 596 | void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE; |
| 597 | void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 598 | |
| 599 | // Call to address held at [base+offset] |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 600 | void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE; |
| 601 | void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE; |
| 602 | void CallFromThread32(ThreadOffset<4> offset, ManagedRegister scratch) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 603 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 604 | // Generate code to check if Thread::Current()->exception_ is non-null |
| 605 | // and branch to a ExceptionSlowPath if it is. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 606 | void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 607 | |
| 608 | private: |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 609 | inline void EmitUint8(uint8_t value); |
| 610 | inline void EmitInt32(int32_t value); |
| 611 | inline void EmitRegisterOperand(int rm, int reg); |
| 612 | inline void EmitXmmRegisterOperand(int rm, XmmRegister reg); |
| 613 | inline void EmitFixup(AssemblerFixup* fixup); |
| 614 | inline void EmitOperandSizeOverride(); |
| 615 | |
| 616 | void EmitOperand(int rm, const Operand& operand); |
| 617 | void EmitImmediate(const Immediate& imm); |
| 618 | void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); |
| 619 | void EmitLabel(Label* label, int instruction_size); |
| 620 | void EmitLabelLink(Label* label); |
| 621 | void EmitNearLabelLink(Label* label); |
| 622 | |
| 623 | void EmitGenericShift(int rm, Register reg, const Immediate& imm); |
| 624 | void EmitGenericShift(int rm, Register operand, Register shifter); |
| 625 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 626 | DISALLOW_COPY_AND_ASSIGN(X86Assembler); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 627 | }; |
| 628 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 629 | inline void X86Assembler::EmitUint8(uint8_t value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 630 | buffer_.Emit<uint8_t>(value); |
| 631 | } |
| 632 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 633 | inline void X86Assembler::EmitInt32(int32_t value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 634 | buffer_.Emit<int32_t>(value); |
| 635 | } |
| 636 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 637 | inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 638 | CHECK_GE(rm, 0); |
| 639 | CHECK_LT(rm, 8); |
| 640 | buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg); |
| 641 | } |
| 642 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 643 | inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 644 | EmitRegisterOperand(rm, static_cast<Register>(reg)); |
| 645 | } |
| 646 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 647 | inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 648 | buffer_.EmitFixup(fixup); |
| 649 | } |
| 650 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 651 | inline void X86Assembler::EmitOperandSizeOverride() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 652 | EmitUint8(0x66); |
| 653 | } |
| 654 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 655 | // Slowpath entered when Thread::Current()->_exception is non-null |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 656 | class X86ExceptionSlowPath FINAL : public SlowPath { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 657 | public: |
Brian Carlstrom | 93ba893 | 2013-07-17 21:31:49 -0700 | [diff] [blame] | 658 | explicit X86ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {} |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 659 | virtual void Emit(Assembler *sp_asm) OVERRIDE; |
Ian Rogers | 00f7d0e | 2012-07-19 15:28:27 -0700 | [diff] [blame] | 660 | private: |
| 661 | const size_t stack_adjust_; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 662 | }; |
| 663 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 664 | } // namespace x86 |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 665 | } // namespace art |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 666 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 667 | #endif // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |