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gerrit-public.fairphone.software / platform / art / 3a5c1ce3f11805a3382046f699c8fb1410a602b3 / . / src / disassembler_arm.cc
blob: a2c890db72084fc649be8e236df49f62903712b1 [file] [log] [blame]
Ian Rogers3a5c1ce2012-02-29 10:06:46 -0800[diff] [blame^]1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "disassembler_arm.h"
18
19#include "stringprintf.h"
20
21#include <iostream>
22
23namespace art {
24namespace arm {
25
26DisassemblerArm::DisassemblerArm() {
27}
28
29
30void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
31 if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) {
32 for (const uint8_t* cur = begin; cur < end; cur += 4) {
33 DumpArm(os, cur);
34 }
35 } else {
36 // remove thumb specifier bits
37 begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1);
38 end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1);
39 for (const uint8_t* cur = begin; cur < end;) {
40 cur += DumpThumb16(os, cur);
41 }
42 }
43}
44
45void DisassemblerArm::DumpReg(std::ostream& os, uint32_t reg) {
46 switch (reg) {
47 case 14: os << "LR"; break;
48 case 15: os << "PC"; break;
49 default: os << "r" << reg; break;
50 }
51}
52
53void DisassemblerArm::DumpRegList(std::ostream& os, uint32_t reg_list) {
54 if (reg_list == 0) {
55 os << "<no register list?>";
56 return;
57 }
58 bool first = true;
59 for (size_t i = 0; i < 16; i++) {
60 if ((reg_list & (1 << i)) != 0) {
61 if (first) {
62 os << "{";
63 first = false;
64 } else {
65 os << ", ";
66 }
67 DumpReg(os, i);
68 }
69 }
70 os << "}";
71
72}
73
74static uint32_t ReadU16(const uint8_t* ptr) {
75 return ptr[0] | (ptr[1] << 8);
76}
77
78static uint32_t ReadU32(const uint8_t* ptr) {
79 return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
80}
81
82
83void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) {
84 os << StringPrintf("\t\t\t%p: %08x\n", instr_ptr, ReadU32(instr_ptr));
85}
86
87size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) {
88 uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2);
89 // |111|1 1|1000000|0000|1111110000000000|
90 // |5 3|2 1|0987654|3 0|5 0 5 0|
91 // |---|---|-------|----|----------------|
92 // |332|2 2|2222222|1111|1111110000000000|
93 // |1 9|8 7|6543210|9 6|5 0 5 0|
94 // |---|---|-------|----|----------------|
95 // |111|op1| op2 | | |
96 uint32_t op1 = (instr >> 27) & 3;
97 uint32_t op2 = (instr >> 20) & 0x7F;
98 os << StringPrintf("\t\t\t%p: ", instr_ptr);
99 switch (op1) {
100 case 0:
101 return DumpThumb16(os, instr_ptr);
102 break;
103 case 1:
104 switch (op2) {
105 case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0A: case 0x0B:
106 case 0x10: case 0x11: case 0x12: case 0x13: case 0x18: case 0x19: case 0x1A: case 0x1B: {
107 // |111|11|10|00|0|00|0000|1111110000000000|
108 // |5 3|21|09|87|6|54|3 0|5 0 5 0|
109 // |---|--|--|--|-|--|----|----------------|
110 // |332|22|22|22|2|22|1111|1111110000000000|
111 // |1 9|87|65|43|2|10|9 6|5 0 5 0|
112 // |---|--|--|--|-|--|----|----------------|
113 // |111|01|00|op|0|WL| Rn | |
114 // |111|01| op2 | | |
115 // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr
116 // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr
117 // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr
118 // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr
119 uint32_t op = (instr >> 23) & 3;
120 uint32_t W = (instr >> 21) & 1;
121 uint32_t L = (instr >> 20) & 1;
122 uint32_t Rn = (instr >> 16) & 0xF;
123 uint32_t reg_list = instr & 0xFFFF;
124 if (op == 1 || op == 2) {
125 if (op == 1) {
126 if (L == 0) {
127 os << "STM ";
128 DumpReg(os, Rn);
129 if (W == 0) {
130 os << ", ";
131 } else {
132 os << "!, ";
133 }
134 } else {
135 if (Rn != 13) {
136 os << "LDM ";
137 DumpReg(os, Rn);
138 if (W == 0) {
139 os << ", ";
140 } else {
141 os << "!, ";
142 }
143 } else {
144 os << "POP ";
145 }
146 }
147 } else {
148 if (L == 0) {
149 if (Rn != 13) {
150 os << "STMDB ";
151 DumpReg(os, Rn);
152 if (W == 0) {
153 os << ", ";
154 } else {
155 os << "!, ";
156 }
157 } else {
158 os << "PUSH ";
159 }
160 } else {
161 os << "LDMDB ";
162 DumpReg(os, Rn);
163 if (W == 0) {
164 os << ", ";
165 } else {
166 os << "!, ";
167 }
168 }
169 }
170 DumpRegList(os, reg_list);
171 os << " // ";
172 }
173 break;
174 }
175 default:
176 break;
177 }
178 break;
179 case 3:
180 switch (op2) {
181 case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0
182 case 0x08: case 0x0A: case 0x0C: case 0x0E: {
183 // Store single data item
184 uint32_t op3 = (instr >> 21) & 7;
185 //uint32_t op4 = (instr >> 6) & 0x3F;
186 switch (op3) {
187 case 0x2: case 0x6: {
188 // Load word
189 // |111|11|100|000|0|0000|1111|110000|000000|
190 // |5 3|21|098|765|4|3 0|5 2|10 6|5 0|
191 // |---|--|---|---|-|----|----|------|------|
192 // |332|22|222|222|2|1111|1111|110000|000000|
193 // |1 9|87|654|321|0|9 6|5 2|10 6|5 0|
194 // |---|--|---|---|-|----|----|------|------|
195 // |111|11|000|op3|0| | | op4 | |
196
197 // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii
198 // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii
199 uint32_t Rn = (instr >> 16) & 0xF;
200 uint32_t Rt = (instr >> 12) & 0xF;
201 if (op3 == 6) {
202 uint32_t imm12 = instr & 0xFFF;
203 os << "STR.W ";
204 DumpReg(os, Rt);
205 os << ", [";
206 DumpReg(os, Rn);
207 os << ", #" << imm12 << "] // ";
208 }
209 }
210 }
211
212 break;
213 }
214 case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101
215 // Load word
216 // |111|11|10|0 0|00|0|0000|1111|110000|000000|
217 // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0|
218 // |---|--|--|---|--|-|----|----|------|------|
219 // |332|22|22|2 2|22|2|1111|1111|110000|000000|
220 // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0|
221 // |---|--|--|---|--|-|----|----|------|------|
222 // |111|11|00|op3|10|1| Rn | Rt | op4 | |
223 // |111|11| op2 | | | imm12 |
224 uint32_t op3 = (instr >> 23) & 3;
225 uint32_t op4 = (instr >> 6) & 0x3F;
226 uint32_t Rn = (instr >> 16) & 0xF;
227 uint32_t Rt = (instr >> 12) & 0xF;
228 if (op3 == 1 || Rn == 15) {
229 // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii
230 // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii
231 uint32_t imm12 = instr & 0xFFF;
232 os << "LDR.W ";
233 DumpReg(os, Rt);
234 os << ", [";
235 DumpReg(os, Rn);
236 os << ", #" << imm12 << "] // ";
237 } else if (op4 == 0) {
238 // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm
239 uint32_t imm2 = (instr >> 4) & 0xF;
240 uint32_t Rm = instr & 0xF;
241 os << "LDR.W ";
242 DumpReg(os, Rt);
243 os << ", [";
244 DumpReg(os, Rn);
245 os << ", ";
246 DumpReg(os, Rm);
247 if (imm2 != 0) {
248 os << ", LSL #" << imm2;
249 }
250 os << "] // ";
251 } else {
252 // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii
253 uint32_t imm8 = instr & 0xFF;
254 os << "LDRT ";
255 DumpReg(os, Rt);
256 os << ", [";
257 DumpReg(os, Rn);
258 os << ", #" << imm8 << "] // ";
259 }
260 break;
261 }
262 }
263 default:
264 break;
265 }
266 os << StringPrintf("%08x\n", instr);
267 return 4;
268}
269
270size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) {
271 uint16_t instr = ReadU16(instr_ptr);
272 bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800);
273 if (is_32bit) {
274 return DumpThumb32(os, instr_ptr);
275 } else {
276 os << StringPrintf("\t\t\t%p: ", instr_ptr);
277 uint16_t opcode1 = instr >> 10;
278 if (opcode1 < 0x10) {
279 // shift (immediate), add, subtract, move, and compare
280 uint16_t opcode2 = instr >> 9;
281 switch (opcode2) {
282 case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
283 case 0x8: case 0x9: case 0xA: case 0xB: {
284 // Logical shift left - 00 000xx xxxxxxxxx
285 // Logical shift right - 00 001xx xxxxxxxxx
286 // Arithmetic shift right - 00 010xx xxxxxxxxx
287 uint16_t imm5 = (instr >> 6) & 0x1F;
288 uint16_t Rm = (instr >> 3) & 7;
289 uint16_t Rd = instr & 7;
290 if (opcode2 <= 3) {
291 os << "LSLS ";
292 } else if (opcode2 <= 7) {
293 os << "LSRS ";
294 } else {
295 os << "ASRS ";
296 }
297 DumpReg(os, Rd);
298 os << ", ";
299 DumpReg(os, Rm);
300 os << ", #" << imm5 << " // ";
301 break;
302 }
303 case 0xC: case 0xD: case 0xE: case 0xF: {
304 // Add register - 00 01100 mmm nnn ddd
305 // Sub register - 00 01101 mmm nnn ddd
306 // Add 3-bit immediate - 00 01110 iii nnn ddd
307 // Sub 3-bit immediate - 00 01111 iii nnn ddd
308 uint16_t imm3_or_Rm = (instr >> 6) & 7;
309 uint16_t Rn = (instr >> 3) & 7;
310 uint16_t Rd = instr & 7;
311 if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) {
312 os << "MOV ";
313 } else {
314 if ((opcode2 & 1) == 0) {
315 os << "ADDS ";
316 } else {
317 os << "SUBS ";
318 }
319 }
320 DumpReg(os, Rd);
321 os << ", ";
322 DumpReg(os, Rn);
323 if ((opcode2 & 2) == 0) {
324 os << ", ";
325 DumpReg(os, imm3_or_Rm);
326 } else if (imm3_or_Rm != 0) {
327 os << ", #" << imm3_or_Rm;
328 }
329 os << " // ";
330 break;
331 }
332 case 0x10: case 0x11: case 0x12: case 0x13:
333 case 0x14: case 0x15: case 0x16: case 0x17:
334 case 0x18: case 0x19: case 0x1A: case 0x1B:
335 case 0x1C: case 0x1D: case 0x1E: case 0x1F: {
336 // MOVS Rd, #imm8 - 00100 ddd iiiiiiii
337 // CMP Rn, #imm8 - 00101 nnn iiiiiiii
338 // ADDS Rn, #imm8 - 00110 nnn iiiiiiii
339 // SUBS Rn, #imm8 - 00111 nnn iiiiiiii
340 uint16_t Rn = (instr >> 8) & 7;
341 uint16_t imm8 = instr & 0xFF;
342 switch (opcode2 >> 2) {
343 case 4: os << "MOVS "; break;
344 case 5: os << "CMP "; break;
345 case 6: os << "ADDS "; break;
346 case 7: os << "SUBS "; break;
347 }
348 DumpReg(os, Rn);
349 os << ", #" << imm8 << " // ";
350 break;
351 }
352 default:
353 break;
354 }
355 } else if (opcode1 == 0x11) {
356 // Special data instructions and branch and exchange
357 uint16_t opcode2 = (instr >> 6) & 0x0F;
358 switch (opcode2) {
359 case 0x0: case 0x1: case 0x2: case 0x3: {
360 // Add low registers - 010001 0000 xxxxxx
361 // Add high registers - 010001 0001/001x xxxxxx
362 uint16_t DN = (instr >> 7) & 1;
363 uint16_t Rm = (instr >> 3) & 0xF;
364 uint16_t Rdn = instr & 7;
365 uint16_t DN_Rdn = (DN << 3) | Rdn;
366 os << "ADD ";
367 DumpReg(os, DN_Rdn);
368 os << ", ";
369 DumpReg(os, Rm);
370 os << " // ";
371 break;
372 }
373 case 0x8: case 0x9: case 0xA: case 0xB: {
374 // Move low registers - 010001 1000 xxxxxx
375 // Move high registers - 010001 1001/101x xxxxxx
376 uint16_t DN = (instr >> 7) & 1;
377 uint16_t Rm = (instr >> 3) & 0xF;
378 uint16_t Rdn = instr & 7;
379 uint16_t DN_Rdn = (DN << 3) | Rdn;
380 os << "MOV ";
381 DumpReg(os, DN_Rdn);
382 os << ", ";
383 DumpReg(os, Rm);
384 os << " // ";
385 break;
386 }
387 case 0x5: case 0x6: case 0x7: {
388 // Compare high registers - 010001 0101/011x xxxxxx
389 uint16_t N = (instr >> 7) & 1;
390 uint16_t Rm = (instr >> 3) & 0xF;
391 uint16_t Rn = instr & 7;
392 uint16_t N_Rn = (N << 3) | Rn;
393 os << "CMP ";
394 DumpReg(os, N_Rn);
395 os << ", ";
396 DumpReg(os, Rm);
397 os << " // ";
398 break;
399 }
400 case 0xC: case 0xD: case 0xE: case 0xF: {
401 // Branch and exchange - 010001 110x xxxxxx
402 // Branch with link and exchange - 010001 111x xxxxxx
403 uint16_t Rm = instr >> 3 & 0xF;
404 if ((opcode2 & 0x2) == 0) {
405 os << "BX ";
406 } else {
407 os << "BLX ";
408 }
409 DumpReg(os, Rm);
410 os << " // ";
411 break;
412 }
413 default:
414 break;
415 }
416 } else if ((instr & 0xF000) == 0xB000) {
417 // Miscellaneous 16-bit instructions
418 uint16_t opcode2 = (instr >> 5) & 0x7F;
419 switch (opcode2) {
420 case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: {
421 // Add immediate to SP - 1011 00000 ii iiiii
422 // Subtract immediate from SP - 1011 00001 ii iiiii
423 int imm7 = instr & 0x7F;
424 if ((opcode2 & 4) == 0) {
425 os << "ADD SP, SP, #";
426 } else {
427 os << "SUB SP, SP, #";
428 }
429 os << (imm7 << 2) << " // ";
430 break;
431 }
432 default:
433 break;
434 }
435 } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) ||
436 ((instr & 0xE000) == 0x8000)) {
437 // Load/store single data item
438 uint16_t opA = instr >> 12;
439 //uint16_t opB = (instr >> 9) & 7;
440 switch (opA) {
441 case 0x6: {
442 // STR Rt, Rn, #imm - 01100 iiiii nnn ttt
443 // LDR Rt, Rn, #imm - 01101 iiiii nnn ttt
444 uint16_t imm5 = (instr >> 6) & 0x1F;
445 uint16_t Rn = (instr >> 3) & 7;
446 uint16_t Rt = instr & 7;
447 if ((instr & 0x800) == 0) {
448 os << "STR ";
449 } else {
450 os << "LDR ";
451 }
452 DumpReg(os, Rt);
453 os << ", [";
454 DumpReg(os, Rn);
455 os << ", #" << (imm5 << 2) << "] // ";
456 break;
457 }
458 case 0x9: {
459 // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii
460 // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
461 uint16_t imm8 = instr & 0xFF;
462 uint16_t Rt = (instr >> 8) & 7;
463 if ((instr & 0x800) == 0) {
464 os << "STR ";
465 } else {
466 os << "LDR ";
467 }
468 DumpReg(os, Rt);
469 os << ", [SP, #" << (imm8 << 2) << "] // ";
470 break;
471 }
472 default:
473 break;
474 }
475 }
476 os << StringPrintf("%04x\n", instr);
477 }
478 return 2;
479}
480
481} // namespace arm
482} // namespace art