Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
| 19 | #include "stringprintf.h" |
| 20 | |
| 21 | #include <iostream> |
| 22 | |
| 23 | namespace art { |
| 24 | namespace arm { |
| 25 | |
| 26 | DisassemblerArm::DisassemblerArm() { |
| 27 | } |
| 28 | |
| 29 | |
| 30 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 31 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 32 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 33 | DumpArm(os, cur); |
| 34 | } |
| 35 | } else { |
| 36 | // remove thumb specifier bits |
| 37 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 38 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 39 | for (const uint8_t* cur = begin; cur < end;) { |
| 40 | cur += DumpThumb16(os, cur); |
| 41 | } |
| 42 | } |
| 43 | } |
| 44 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 45 | static const char* ConditionCodeNames[] = { |
| 46 | "EQ", // 0000 - equal |
| 47 | "NE", // 0001 - not-equal |
| 48 | "CS", // 0010 - carry-set, greater than, equal or unordered |
| 49 | "CC", // 0011 - carry-clear, less than |
| 50 | "MI", // 0100 - minus, negative |
| 51 | "PL", // 0101 - plus, positive or zero |
| 52 | "VS", // 0110 - overflow |
| 53 | "VC", // 0111 - no overflow |
| 54 | "HI", // 1000 - unsigned higher |
| 55 | "LS", // 1001 - unsigned lower or same |
| 56 | "GE", // 1010 - signed greater than or equal |
| 57 | "LT", // 1011 - signed less than |
| 58 | "GT", // 1100 - signed greater than |
| 59 | "LE", // 1101 - signed less than or equal |
| 60 | "AL", // 1110 - always |
| 61 | }; |
| 62 | |
| 63 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 64 | if (cond < 15) { |
| 65 | os << ConditionCodeNames[cond]; |
| 66 | } else { |
| 67 | os << "Unexpected condition: " << cond; |
| 68 | } |
| 69 | } |
| 70 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 71 | void DisassemblerArm::DumpReg(std::ostream& os, uint32_t reg) { |
| 72 | switch (reg) { |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 73 | case 13: os << "SP"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 74 | case 14: os << "LR"; break; |
| 75 | case 15: os << "PC"; break; |
| 76 | default: os << "r" << reg; break; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | void DisassemblerArm::DumpRegList(std::ostream& os, uint32_t reg_list) { |
| 81 | if (reg_list == 0) { |
| 82 | os << "<no register list?>"; |
| 83 | return; |
| 84 | } |
| 85 | bool first = true; |
| 86 | for (size_t i = 0; i < 16; i++) { |
| 87 | if ((reg_list & (1 << i)) != 0) { |
| 88 | if (first) { |
| 89 | os << "{"; |
| 90 | first = false; |
| 91 | } else { |
| 92 | os << ", "; |
| 93 | } |
| 94 | DumpReg(os, i); |
| 95 | } |
| 96 | } |
| 97 | os << "}"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 98 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 99 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 100 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
| 101 | os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 105 | return ptr[0] | (ptr[1] << 8); |
| 106 | } |
| 107 | |
| 108 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 109 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 110 | } |
| 111 | |
| 112 | |
| 113 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
| 114 | os << StringPrintf("\t\t\t%p: %08x\n", instr_ptr, ReadU32(instr_ptr)); |
| 115 | } |
| 116 | |
| 117 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 118 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 119 | // |111|1 1|1000000|0000|1111110000000000| |
| 120 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 121 | // |---|---|-------|----|----------------| |
| 122 | // |332|2 2|2222222|1111|1111110000000000| |
| 123 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 124 | // |---|---|-------|----|----------------| |
| 125 | // |111|op1| op2 | | | |
| 126 | uint32_t op1 = (instr >> 27) & 3; |
| 127 | uint32_t op2 = (instr >> 20) & 0x7F; |
| 128 | os << StringPrintf("\t\t\t%p: ", instr_ptr); |
| 129 | switch (op1) { |
| 130 | case 0: |
| 131 | return DumpThumb16(os, instr_ptr); |
| 132 | break; |
| 133 | case 1: |
| 134 | switch (op2) { |
| 135 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 136 | case 0x10: case 0x11: case 0x12: case 0x13: case 0x18: case 0x19: case 0x1A: case 0x1B: { |
| 137 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 138 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 139 | // |---|--|--|--|-|--|----|----------------| |
| 140 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 141 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 142 | // |---|--|--|--|-|--|----|----------------| |
| 143 | // |111|01|00|op|0|WL| Rn | | |
| 144 | // |111|01| op2 | | | |
| 145 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 146 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 147 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 148 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 149 | uint32_t op = (instr >> 23) & 3; |
| 150 | uint32_t W = (instr >> 21) & 1; |
| 151 | uint32_t L = (instr >> 20) & 1; |
| 152 | uint32_t Rn = (instr >> 16) & 0xF; |
| 153 | uint32_t reg_list = instr & 0xFFFF; |
| 154 | if (op == 1 || op == 2) { |
| 155 | if (op == 1) { |
| 156 | if (L == 0) { |
| 157 | os << "STM "; |
| 158 | DumpReg(os, Rn); |
| 159 | if (W == 0) { |
| 160 | os << ", "; |
| 161 | } else { |
| 162 | os << "!, "; |
| 163 | } |
| 164 | } else { |
| 165 | if (Rn != 13) { |
| 166 | os << "LDM "; |
| 167 | DumpReg(os, Rn); |
| 168 | if (W == 0) { |
| 169 | os << ", "; |
| 170 | } else { |
| 171 | os << "!, "; |
| 172 | } |
| 173 | } else { |
| 174 | os << "POP "; |
| 175 | } |
| 176 | } |
| 177 | } else { |
| 178 | if (L == 0) { |
| 179 | if (Rn != 13) { |
| 180 | os << "STMDB "; |
| 181 | DumpReg(os, Rn); |
| 182 | if (W == 0) { |
| 183 | os << ", "; |
| 184 | } else { |
| 185 | os << "!, "; |
| 186 | } |
| 187 | } else { |
| 188 | os << "PUSH "; |
| 189 | } |
| 190 | } else { |
| 191 | os << "LDMDB "; |
| 192 | DumpReg(os, Rn); |
| 193 | if (W == 0) { |
| 194 | os << ", "; |
| 195 | } else { |
| 196 | os << "!, "; |
| 197 | } |
| 198 | } |
| 199 | } |
| 200 | DumpRegList(os, reg_list); |
| 201 | os << " // "; |
| 202 | } |
| 203 | break; |
| 204 | } |
| 205 | default: |
| 206 | break; |
| 207 | } |
| 208 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 209 | case 2: |
| 210 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 211 | // Data-processing (modified immediate) |
| 212 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 213 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 214 | // |---|--|--|----|-|----|-|---|----|--------| |
| 215 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 216 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 217 | // |---|--|--|----|-|----|-|---|----|--------| |
| 218 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 219 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
| 220 | // 111 10 00 0110 0 0000 1 000 0000 10101101 - f0c080ad |
| 221 | uint32_t i = (instr >> 26) & 1; |
| 222 | uint32_t op3 = (instr >> 21) & 0xF; |
| 223 | uint32_t S = (instr >> 20) & 1; |
| 224 | uint32_t Rn = (instr >> 16) & 0xF; |
| 225 | uint32_t imm3 = (instr >> 12) & 7; |
| 226 | uint32_t Rd = (instr >> 8) & 0xF; |
| 227 | uint32_t imm8 = instr & 0xFF; |
| 228 | int32_t imm32 = (i << 12) | (imm3 << 8) | imm8; |
| 229 | switch (op3) { |
| 230 | case 0x0: os << "AND"; break; |
| 231 | case 0x1: os << "BIC"; break; |
| 232 | case 0x2: os << "ORR"; break; |
| 233 | case 0x3: os << "ORN"; break; |
| 234 | case 0x4: os << "EOR"; break; |
| 235 | case 0x8: os << "ADD"; break; |
| 236 | case 0xA: os << "ADC"; break; |
| 237 | case 0xB: os << "SBC"; break; |
| 238 | case 0xD: os << "SUB"; break; |
| 239 | case 0xE: os << "RSB"; break; |
| 240 | default: os << "UNKNOWN DPMI-" << op3; break; |
| 241 | } |
| 242 | if (S == 1) { |
| 243 | os << "S "; |
| 244 | } else { |
| 245 | os << " "; |
| 246 | } |
| 247 | DumpReg(os, Rd); |
| 248 | os << ", "; |
| 249 | DumpReg(os, Rn); |
| 250 | os << ", ThumbExpand(" << imm32 << ") // "; |
| 251 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 252 | // Data-processing (plain binary immediate) |
| 253 | // |111|11|10|00000|0000|1|111110000000000| |
| 254 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 255 | // |---|--|--|-----|----|-|---------------| |
| 256 | // |332|22|22|22222|1111|1|111110000000000| |
| 257 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 258 | // |---|--|--|-----|----|-|---------------| |
| 259 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 260 | uint32_t op3 = (instr >> 20) & 0x1F; |
| 261 | uint32_t Rn = (instr >> 16) & 0xF; |
| 262 | switch (op3) { |
| 263 | case 0x04: { |
| 264 | // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
| 265 | uint32_t Rd = (instr >> 8) & 0xF; |
| 266 | uint32_t i = (instr >> 26) & 1; |
| 267 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 268 | uint32_t imm8 = instr & 0xFF; |
| 269 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
| 270 | os << "MOVW "; |
| 271 | DumpReg(os, Rd); |
| 272 | os << ", #" << imm16 << " // "; |
| 273 | break; |
| 274 | } |
| 275 | case 0x0A: { |
| 276 | // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
| 277 | uint32_t Rd = (instr >> 8) & 0xF; |
| 278 | uint32_t i = (instr >> 26) & 1; |
| 279 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 280 | uint32_t imm8 = instr & 0xFF; |
| 281 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
| 282 | os << "SUB.W "; |
| 283 | DumpReg(os, Rd); |
| 284 | os << ", "; |
| 285 | DumpReg(os, Rn); |
| 286 | os << ", #" << imm12 << " // "; |
| 287 | break; |
| 288 | } |
| 289 | default: |
| 290 | break; |
| 291 | } |
| 292 | } else { |
| 293 | // Branches and miscellaneous control |
| 294 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 295 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 296 | // |---|--|-------|----|-|---|----|--------| |
| 297 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 298 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 299 | // |---|--|-------|----|-|---|----|--------| |
| 300 | // |111|10| op2 | |1|op3|op4 | | |
| 301 | |
| 302 | uint32_t op3 = (instr >> 12) & 7; |
| 303 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 304 | switch (op3) { |
| 305 | case 0: |
| 306 | if ((op2 & 0x38) != 0x38) { |
| 307 | // Conditional branch |
| 308 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 309 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 310 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 311 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 312 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 313 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 314 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 315 | uint32_t S = (instr >> 26) & 1; |
| 316 | uint32_t J2 = (instr >> 11) & 1; |
| 317 | uint32_t J1 = (instr >> 13) & 1; |
| 318 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 319 | uint32_t imm11 = instr & 0x7FF; |
| 320 | uint32_t cond = (instr >> 22) & 0xF; |
| 321 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 322 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
| 323 | os << "B"; |
| 324 | DumpCond(os, cond); |
| 325 | os << ".W "; |
| 326 | DumpBranchTarget(os, instr_ptr + 4, imm32); |
| 327 | os << " // "; |
| 328 | } |
| 329 | break; |
| 330 | case 2: |
| 331 | case 1: case 3: |
| 332 | break; |
| 333 | case 4: case 6: case 5: case 7: { |
| 334 | // BL, BLX (immediate) |
| 335 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 336 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 337 | // |---|--|-|----------|--|--|-|--|-----------| |
| 338 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 339 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 340 | // |---|--|-|----------|--|--|-|--|-----------| |
| 341 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 342 | uint32_t S = (instr >> 26) & 1; |
| 343 | uint32_t J2 = (instr >> 11) & 1; |
| 344 | uint32_t L = (instr >> 12) & 1; |
| 345 | uint32_t J1 = (instr >> 13) & 1; |
| 346 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 347 | uint32_t imm11 = instr & 0x7FF; |
| 348 | if (L == 0) { |
| 349 | os << "BX "; |
| 350 | } else { |
| 351 | os << "BLX "; |
| 352 | } |
| 353 | uint32_t I1 = ~(J1 ^ S); |
| 354 | uint32_t I2 = ~(J2 ^ S); |
| 355 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 356 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
| 357 | DumpBranchTarget(os, instr_ptr + 4, imm32); |
| 358 | break; |
| 359 | } |
| 360 | } |
| 361 | } |
| 362 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 363 | case 3: |
| 364 | switch (op2) { |
| 365 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 366 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 367 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 368 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 369 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 370 | // |---|--|---|---|-|----|----|------|------| |
| 371 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 372 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 373 | // |---|--|---|---|-|----|----|------|------| |
| 374 | // |111|11|000|op3|0| | | op4 | | |
| 375 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 376 | uint32_t op3 = (instr >> 21) & 7; |
| 377 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 378 | switch (op3) { |
| 379 | case 0x2: case 0x6: { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 380 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
| 381 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 382 | uint32_t Rn = (instr >> 16) & 0xF; |
| 383 | uint32_t Rt = (instr >> 12) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 384 | if (op3 == 2) { |
| 385 | uint32_t P = (instr >> 10) & 1; |
| 386 | uint32_t U = (instr >> 9) & 1; |
| 387 | uint32_t W = (instr >> 8) & 1; |
| 388 | uint32_t imm8 = instr & 0xFF; |
| 389 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 390 | if (Rn == 13 && P == 1 && U == 0 && W == 1) { |
| 391 | os << "PUSH "; |
| 392 | DumpReg(os, Rt); |
| 393 | os << " // "; |
| 394 | } else if (Rn == 15 || (P == 0 && W == 0)) { |
| 395 | os << "UNDEFINED "; |
| 396 | } else { |
| 397 | if (P == 1 && U == 1 && W == 0) { |
| 398 | os << "STRT "; |
| 399 | } else { |
| 400 | os << "STR "; |
| 401 | } |
| 402 | DumpReg(os, Rt); |
| 403 | os << ", ["; |
| 404 | DumpReg(os, Rn); |
| 405 | if (P == 0 && W == 1) { |
| 406 | os << "], #" << imm32; |
| 407 | } else { |
| 408 | os << ", #" << imm32 << "]"; |
| 409 | if (W == 1) { |
| 410 | os << "!"; |
| 411 | } |
| 412 | } |
| 413 | os << " // "; |
| 414 | } |
| 415 | } else if (op3 == 6) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 416 | uint32_t imm12 = instr & 0xFFF; |
| 417 | os << "STR.W "; |
| 418 | DumpReg(os, Rt); |
| 419 | os << ", ["; |
| 420 | DumpReg(os, Rn); |
| 421 | os << ", #" << imm12 << "] // "; |
| 422 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 423 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 424 | } |
| 425 | } |
| 426 | |
| 427 | break; |
| 428 | } |
| 429 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 430 | // Load word |
| 431 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 432 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 433 | // |---|--|--|---|--|-|----|----|------|------| |
| 434 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 435 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 436 | // |---|--|--|---|--|-|----|----|------|------| |
| 437 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 438 | // |111|11| op2 | | | imm12 | |
| 439 | uint32_t op3 = (instr >> 23) & 3; |
| 440 | uint32_t op4 = (instr >> 6) & 0x3F; |
| 441 | uint32_t Rn = (instr >> 16) & 0xF; |
| 442 | uint32_t Rt = (instr >> 12) & 0xF; |
| 443 | if (op3 == 1 || Rn == 15) { |
| 444 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 445 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 446 | uint32_t imm12 = instr & 0xFFF; |
| 447 | os << "LDR.W "; |
| 448 | DumpReg(os, Rt); |
| 449 | os << ", ["; |
| 450 | DumpReg(os, Rn); |
| 451 | os << ", #" << imm12 << "] // "; |
| 452 | } else if (op4 == 0) { |
| 453 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 454 | uint32_t imm2 = (instr >> 4) & 0xF; |
| 455 | uint32_t Rm = instr & 0xF; |
| 456 | os << "LDR.W "; |
| 457 | DumpReg(os, Rt); |
| 458 | os << ", ["; |
| 459 | DumpReg(os, Rn); |
| 460 | os << ", "; |
| 461 | DumpReg(os, Rm); |
| 462 | if (imm2 != 0) { |
| 463 | os << ", LSL #" << imm2; |
| 464 | } |
| 465 | os << "] // "; |
| 466 | } else { |
| 467 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 468 | uint32_t imm8 = instr & 0xFF; |
| 469 | os << "LDRT "; |
| 470 | DumpReg(os, Rt); |
| 471 | os << ", ["; |
| 472 | DumpReg(os, Rn); |
| 473 | os << ", #" << imm8 << "] // "; |
| 474 | } |
| 475 | break; |
| 476 | } |
| 477 | } |
| 478 | default: |
| 479 | break; |
| 480 | } |
| 481 | os << StringPrintf("%08x\n", instr); |
| 482 | return 4; |
| 483 | } |
| 484 | |
| 485 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 486 | uint16_t instr = ReadU16(instr_ptr); |
| 487 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 488 | if (is_32bit) { |
| 489 | return DumpThumb32(os, instr_ptr); |
| 490 | } else { |
| 491 | os << StringPrintf("\t\t\t%p: ", instr_ptr); |
| 492 | uint16_t opcode1 = instr >> 10; |
| 493 | if (opcode1 < 0x10) { |
| 494 | // shift (immediate), add, subtract, move, and compare |
| 495 | uint16_t opcode2 = instr >> 9; |
| 496 | switch (opcode2) { |
| 497 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 498 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 499 | // Logical shift left - 00 000xx xxxxxxxxx |
| 500 | // Logical shift right - 00 001xx xxxxxxxxx |
| 501 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 502 | uint16_t imm5 = (instr >> 6) & 0x1F; |
| 503 | uint16_t Rm = (instr >> 3) & 7; |
| 504 | uint16_t Rd = instr & 7; |
| 505 | if (opcode2 <= 3) { |
| 506 | os << "LSLS "; |
| 507 | } else if (opcode2 <= 7) { |
| 508 | os << "LSRS "; |
| 509 | } else { |
| 510 | os << "ASRS "; |
| 511 | } |
| 512 | DumpReg(os, Rd); |
| 513 | os << ", "; |
| 514 | DumpReg(os, Rm); |
| 515 | os << ", #" << imm5 << " // "; |
| 516 | break; |
| 517 | } |
| 518 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 519 | // Add register - 00 01100 mmm nnn ddd |
| 520 | // Sub register - 00 01101 mmm nnn ddd |
| 521 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 522 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 523 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
| 524 | uint16_t Rn = (instr >> 3) & 7; |
| 525 | uint16_t Rd = instr & 7; |
| 526 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
| 527 | os << "MOV "; |
| 528 | } else { |
| 529 | if ((opcode2 & 1) == 0) { |
| 530 | os << "ADDS "; |
| 531 | } else { |
| 532 | os << "SUBS "; |
| 533 | } |
| 534 | } |
| 535 | DumpReg(os, Rd); |
| 536 | os << ", "; |
| 537 | DumpReg(os, Rn); |
| 538 | if ((opcode2 & 2) == 0) { |
| 539 | os << ", "; |
| 540 | DumpReg(os, imm3_or_Rm); |
| 541 | } else if (imm3_or_Rm != 0) { |
| 542 | os << ", #" << imm3_or_Rm; |
| 543 | } |
| 544 | os << " // "; |
| 545 | break; |
| 546 | } |
| 547 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 548 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 549 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 550 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 551 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 552 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 553 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 554 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
| 555 | uint16_t Rn = (instr >> 8) & 7; |
| 556 | uint16_t imm8 = instr & 0xFF; |
| 557 | switch (opcode2 >> 2) { |
| 558 | case 4: os << "MOVS "; break; |
| 559 | case 5: os << "CMP "; break; |
| 560 | case 6: os << "ADDS "; break; |
| 561 | case 7: os << "SUBS "; break; |
| 562 | } |
| 563 | DumpReg(os, Rn); |
| 564 | os << ", #" << imm8 << " // "; |
| 565 | break; |
| 566 | } |
| 567 | default: |
| 568 | break; |
| 569 | } |
| 570 | } else if (opcode1 == 0x11) { |
| 571 | // Special data instructions and branch and exchange |
| 572 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 573 | switch (opcode2) { |
| 574 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 575 | // Add low registers - 010001 0000 xxxxxx |
| 576 | // Add high registers - 010001 0001/001x xxxxxx |
| 577 | uint16_t DN = (instr >> 7) & 1; |
| 578 | uint16_t Rm = (instr >> 3) & 0xF; |
| 579 | uint16_t Rdn = instr & 7; |
| 580 | uint16_t DN_Rdn = (DN << 3) | Rdn; |
| 581 | os << "ADD "; |
| 582 | DumpReg(os, DN_Rdn); |
| 583 | os << ", "; |
| 584 | DumpReg(os, Rm); |
| 585 | os << " // "; |
| 586 | break; |
| 587 | } |
| 588 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 589 | // Move low registers - 010001 1000 xxxxxx |
| 590 | // Move high registers - 010001 1001/101x xxxxxx |
| 591 | uint16_t DN = (instr >> 7) & 1; |
| 592 | uint16_t Rm = (instr >> 3) & 0xF; |
| 593 | uint16_t Rdn = instr & 7; |
| 594 | uint16_t DN_Rdn = (DN << 3) | Rdn; |
| 595 | os << "MOV "; |
| 596 | DumpReg(os, DN_Rdn); |
| 597 | os << ", "; |
| 598 | DumpReg(os, Rm); |
| 599 | os << " // "; |
| 600 | break; |
| 601 | } |
| 602 | case 0x5: case 0x6: case 0x7: { |
| 603 | // Compare high registers - 010001 0101/011x xxxxxx |
| 604 | uint16_t N = (instr >> 7) & 1; |
| 605 | uint16_t Rm = (instr >> 3) & 0xF; |
| 606 | uint16_t Rn = instr & 7; |
| 607 | uint16_t N_Rn = (N << 3) | Rn; |
| 608 | os << "CMP "; |
| 609 | DumpReg(os, N_Rn); |
| 610 | os << ", "; |
| 611 | DumpReg(os, Rm); |
| 612 | os << " // "; |
| 613 | break; |
| 614 | } |
| 615 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 616 | // Branch and exchange - 010001 110x xxxxxx |
| 617 | // Branch with link and exchange - 010001 111x xxxxxx |
| 618 | uint16_t Rm = instr >> 3 & 0xF; |
| 619 | if ((opcode2 & 0x2) == 0) { |
| 620 | os << "BX "; |
| 621 | } else { |
| 622 | os << "BLX "; |
| 623 | } |
| 624 | DumpReg(os, Rm); |
| 625 | os << " // "; |
| 626 | break; |
| 627 | } |
| 628 | default: |
| 629 | break; |
| 630 | } |
| 631 | } else if ((instr & 0xF000) == 0xB000) { |
| 632 | // Miscellaneous 16-bit instructions |
| 633 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 634 | switch (opcode2) { |
| 635 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 636 | // Add immediate to SP - 1011 00000 ii iiiii |
| 637 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 638 | int imm7 = instr & 0x7F; |
| 639 | if ((opcode2 & 4) == 0) { |
| 640 | os << "ADD SP, SP, #"; |
| 641 | } else { |
| 642 | os << "SUB SP, SP, #"; |
| 643 | } |
| 644 | os << (imm7 << 2) << " // "; |
| 645 | break; |
| 646 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 647 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 648 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 649 | // If-Then, and hints |
| 650 | uint16_t opA = (instr >> 4) & 0xF; |
| 651 | uint16_t opB = instr & 0xF; |
| 652 | if (opB == 0) { |
| 653 | switch (opA) { |
| 654 | case 0: os << "NOP // "; break; |
| 655 | case 1: os << "YIELD // "; break; |
| 656 | case 2: os << "WFE // "; break; |
| 657 | case 3: os << "SEV // "; break; |
| 658 | default: break; |
| 659 | } |
| 660 | } else { |
| 661 | os << "IT " << reinterpret_cast<void*>(opB) << " "; |
| 662 | DumpCond(os, opA); |
| 663 | os << " // "; |
| 664 | } |
| 665 | break; |
| 666 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 667 | default: |
| 668 | break; |
| 669 | } |
| 670 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 671 | ((instr & 0xE000) == 0x8000)) { |
| 672 | // Load/store single data item |
| 673 | uint16_t opA = instr >> 12; |
| 674 | //uint16_t opB = (instr >> 9) & 7; |
| 675 | switch (opA) { |
| 676 | case 0x6: { |
| 677 | // STR Rt, Rn, #imm - 01100 iiiii nnn ttt |
| 678 | // LDR Rt, Rn, #imm - 01101 iiiii nnn ttt |
| 679 | uint16_t imm5 = (instr >> 6) & 0x1F; |
| 680 | uint16_t Rn = (instr >> 3) & 7; |
| 681 | uint16_t Rt = instr & 7; |
| 682 | if ((instr & 0x800) == 0) { |
| 683 | os << "STR "; |
| 684 | } else { |
| 685 | os << "LDR "; |
| 686 | } |
| 687 | DumpReg(os, Rt); |
| 688 | os << ", ["; |
| 689 | DumpReg(os, Rn); |
| 690 | os << ", #" << (imm5 << 2) << "] // "; |
| 691 | break; |
| 692 | } |
| 693 | case 0x9: { |
| 694 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 695 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 696 | uint16_t imm8 = instr & 0xFF; |
| 697 | uint16_t Rt = (instr >> 8) & 7; |
| 698 | if ((instr & 0x800) == 0) { |
| 699 | os << "STR "; |
| 700 | } else { |
| 701 | os << "LDR "; |
| 702 | } |
| 703 | DumpReg(os, Rt); |
| 704 | os << ", [SP, #" << (imm8 << 2) << "] // "; |
| 705 | break; |
| 706 | } |
| 707 | default: |
| 708 | break; |
| 709 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame^] | 710 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 711 | uint16_t imm11 = instr & 0x7FFF; |
| 712 | int32_t imm32 = imm11 << 1; |
| 713 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
| 714 | os << "B "; |
| 715 | DumpBranchTarget(os, instr_ptr + 4, imm32); |
| 716 | os << " // "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 717 | } |
| 718 | os << StringPrintf("%04x\n", instr); |
| 719 | } |
| 720 | return 2; |
| 721 | } |
| 722 | |
| 723 | } // namespace arm |
| 724 | } // namespace art |