Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_OPTIMIZING_NODES_ARM64_H_ |
| 18 | #define ART_COMPILER_OPTIMIZING_NODES_ARM64_H_ |
| 19 | |
| 20 | namespace art { |
| 21 | |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 22 | class HArm64DataProcWithShifterOp : public HExpression<2> { |
| 23 | public: |
| 24 | enum OpKind { |
| 25 | kLSL, // Logical shift left. |
| 26 | kLSR, // Logical shift right. |
| 27 | kASR, // Arithmetic shift right. |
| 28 | kUXTB, // Unsigned extend byte. |
| 29 | kUXTH, // Unsigned extend half-word. |
| 30 | kUXTW, // Unsigned extend word. |
| 31 | kSXTB, // Signed extend byte. |
| 32 | kSXTH, // Signed extend half-word. |
| 33 | kSXTW, // Signed extend word. |
| 34 | |
| 35 | // Aliases. |
| 36 | kFirstShiftOp = kLSL, |
| 37 | kLastShiftOp = kASR, |
| 38 | kFirstExtensionOp = kUXTB, |
| 39 | kLastExtensionOp = kSXTW |
| 40 | }; |
| 41 | HArm64DataProcWithShifterOp(HInstruction* instr, |
| 42 | HInstruction* left, |
| 43 | HInstruction* right, |
| 44 | OpKind op, |
| 45 | // The shift argument is unused if the operation |
| 46 | // is an extension. |
| 47 | int shift = 0, |
| 48 | uint32_t dex_pc = kNoDexPc) |
| 49 | : HExpression(instr->GetType(), SideEffects::None(), dex_pc), |
| 50 | instr_kind_(instr->GetKind()), op_kind_(op), shift_amount_(shift) { |
| 51 | DCHECK(!instr->HasSideEffects()); |
| 52 | SetRawInputAt(0, left); |
| 53 | SetRawInputAt(1, right); |
| 54 | } |
| 55 | |
| 56 | bool CanBeMoved() const OVERRIDE { return true; } |
| 57 | bool InstructionDataEquals(HInstruction* other_instr) const OVERRIDE { |
| 58 | HArm64DataProcWithShifterOp* other = other_instr->AsArm64DataProcWithShifterOp(); |
| 59 | return instr_kind_ == other->instr_kind_ && |
| 60 | op_kind_ == other->op_kind_ && |
| 61 | shift_amount_ == other->shift_amount_; |
| 62 | } |
| 63 | |
| 64 | static bool IsShiftOp(OpKind op_kind) { |
| 65 | return kFirstShiftOp <= op_kind && op_kind <= kLastShiftOp; |
| 66 | } |
| 67 | |
| 68 | static bool IsExtensionOp(OpKind op_kind) { |
| 69 | return kFirstExtensionOp <= op_kind && op_kind <= kLastExtensionOp; |
| 70 | } |
| 71 | |
| 72 | // Find the operation kind and shift amount from a bitfield move instruction. |
| 73 | static void GetOpInfoFromInstruction(HInstruction* bitfield_op, |
| 74 | /*out*/OpKind* op_kind, |
| 75 | /*out*/int* shift_amount); |
| 76 | |
| 77 | InstructionKind GetInstrKind() const { return instr_kind_; } |
| 78 | OpKind GetOpKind() const { return op_kind_; } |
| 79 | int GetShiftAmount() const { return shift_amount_; } |
| 80 | |
| 81 | DECLARE_INSTRUCTION(Arm64DataProcWithShifterOp); |
| 82 | |
| 83 | private: |
| 84 | InstructionKind instr_kind_; |
| 85 | OpKind op_kind_; |
| 86 | int shift_amount_; |
| 87 | |
| 88 | friend std::ostream& operator<<(std::ostream& os, OpKind op); |
| 89 | |
| 90 | DISALLOW_COPY_AND_ASSIGN(HArm64DataProcWithShifterOp); |
| 91 | }; |
| 92 | |
| 93 | std::ostream& operator<<(std::ostream& os, const HArm64DataProcWithShifterOp::OpKind op); |
| 94 | |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 95 | // This instruction computes an intermediate address pointing in the 'middle' of an object. The |
| 96 | // result pointer cannot be handled by GC, so extra care is taken to make sure that this value is |
| 97 | // never used across anything that can trigger GC. |
| 98 | class HArm64IntermediateAddress : public HExpression<2> { |
| 99 | public: |
| 100 | HArm64IntermediateAddress(HInstruction* base_address, HInstruction* offset, uint32_t dex_pc) |
| 101 | : HExpression(Primitive::kPrimNot, SideEffects::DependsOnGC(), dex_pc) { |
| 102 | SetRawInputAt(0, base_address); |
| 103 | SetRawInputAt(1, offset); |
| 104 | } |
| 105 | |
| 106 | bool CanBeMoved() const OVERRIDE { return true; } |
| 107 | bool InstructionDataEquals(HInstruction* other ATTRIBUTE_UNUSED) const OVERRIDE { return true; } |
| 108 | |
| 109 | HInstruction* GetBaseAddress() const { return InputAt(0); } |
| 110 | HInstruction* GetOffset() const { return InputAt(1); } |
| 111 | |
| 112 | DECLARE_INSTRUCTION(Arm64IntermediateAddress); |
| 113 | |
| 114 | private: |
| 115 | DISALLOW_COPY_AND_ASSIGN(HArm64IntermediateAddress); |
| 116 | }; |
| 117 | |
Alexandre Rames | 418318f | 2015-11-20 15:55:47 +0000 | [diff] [blame] | 118 | class HArm64MultiplyAccumulate : public HExpression<3> { |
| 119 | public: |
| 120 | HArm64MultiplyAccumulate(Primitive::Type type, |
| 121 | InstructionKind op, |
| 122 | HInstruction* accumulator, |
| 123 | HInstruction* mul_left, |
| 124 | HInstruction* mul_right, |
| 125 | uint32_t dex_pc = kNoDexPc) |
| 126 | : HExpression(type, SideEffects::None(), dex_pc), op_kind_(op) { |
| 127 | SetRawInputAt(kInputAccumulatorIndex, accumulator); |
| 128 | SetRawInputAt(kInputMulLeftIndex, mul_left); |
| 129 | SetRawInputAt(kInputMulRightIndex, mul_right); |
| 130 | } |
| 131 | |
| 132 | static constexpr int kInputAccumulatorIndex = 0; |
| 133 | static constexpr int kInputMulLeftIndex = 1; |
| 134 | static constexpr int kInputMulRightIndex = 2; |
| 135 | |
| 136 | bool CanBeMoved() const OVERRIDE { return true; } |
| 137 | bool InstructionDataEquals(HInstruction* other) const OVERRIDE { |
| 138 | return op_kind_ == other->AsArm64MultiplyAccumulate()->op_kind_; |
| 139 | } |
| 140 | |
| 141 | InstructionKind GetOpKind() const { return op_kind_; } |
| 142 | |
| 143 | DECLARE_INSTRUCTION(Arm64MultiplyAccumulate); |
| 144 | |
| 145 | private: |
| 146 | // Indicates if this is a MADD or MSUB. |
| 147 | InstructionKind op_kind_; |
| 148 | |
| 149 | DISALLOW_COPY_AND_ASSIGN(HArm64MultiplyAccumulate); |
| 150 | }; |
| 151 | |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 152 | } // namespace art |
| 153 | |
| 154 | #endif // ART_COMPILER_OPTIMIZING_NODES_ARM64_H_ |