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gerrit-public.fairphone.software / platform / art / 468532ea115657709bc32ee498e701a4c71762d4 / . / compiler / dex / quick / arm / codegen_arm.h
blob: f1ccfa015edbf4a265e3632a1aecd4e0c38a807f [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]19
20#include "dex/compiler_internals.h"
21
22namespace art {
23
24class ArmMir2Lir : public Mir2Lir {
25 public:
26 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
27
28 // Required for target - codegen helpers.
29 bool SmallLiteralDivide(Instruction::Code dalvik_opcode, RegLocation rl_src,
30 RegLocation rl_dest, int lit);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame^]31 int LoadHelper(ThreadOffset offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
33 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
34 int s_reg);
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
37 int r_dest, int r_dest_hi, OpSize size, int s_reg);
38 LIR* LoadConstantNoClobber(int r_dest, int value);
39 LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
41 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
44 int r_src, int r_src_hi, OpSize size, int s_reg);
45 void MarkGCCard(int val_reg, int tgt_addr_reg);
46
47 // Required for target - register utilities.
48 bool IsFpReg(int reg);
49 bool SameRegType(int reg1, int reg2);
50 int AllocTypedTemp(bool fp_hint, int reg_class);
51 int AllocTypedTempPair(bool fp_hint, int reg_class);
52 int S2d(int low_reg, int high_reg);
53 int TargetReg(SpecialTargetRegister reg);
54 RegisterInfo* GetRegInfo(int reg);
55 RegLocation GetReturnAlt();
56 RegLocation GetReturnWideAlt();
57 RegLocation LocCReturn();
58 RegLocation LocCReturnDouble();
59 RegLocation LocCReturnFloat();
60 RegLocation LocCReturnWide();
61 uint32_t FpRegMask();
62 uint64_t GetRegMaskCommon(int reg);
63 void AdjustSpillMask();
64 void ClobberCalleeSave();
65 void FlushReg(int reg);
66 void FlushRegWide(int reg1, int reg2);
67 void FreeCallTemps();
68 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
69 void LockCallTemps();
70 void MarkPreservedSingle(int v_reg, int reg);
71 void CompilerInitializeRegAlloc();
72
73 // Required for target - miscellaneous.
74 AssemblerStatus AssembleInstructions(uintptr_t start_addr);
75 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
76 void SetupTargetResourceMasks(LIR* lir);
77 const char* GetTargetInstFmt(int opcode);
78 const char* GetTargetInstName(int opcode);
79 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
80 uint64_t GetPCUseDefEncoding();
81 uint64_t GetTargetInstFlags(int opcode);
82 int GetInsnSize(LIR* lir);
83 bool IsUnconditionalBranch(LIR* lir);
84
85 // Required for target - Dalvik-level generators.
86 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
87 RegLocation rl_src1, RegLocation rl_src2);
88 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index,
89 RegLocation rl_src, int scale);
90 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
91 RegLocation rl_index, RegLocation rl_dest, int scale);
92 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
93 RegLocation rl_index, RegLocation rl_src, int scale);
94 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
95 RegLocation rl_src1, RegLocation rl_shift);
96 void GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
97 void GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
98 void GenAndLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
99 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
100 RegLocation rl_src1, RegLocation rl_src2);
101 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
102 RegLocation rl_src1, RegLocation rl_src2);
103 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
104 RegLocation rl_src2);
105 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
106 bool GenInlinedCas32(CallInfo* info, bool need_write_barrier);
107 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
108 bool GenInlinedSqrt(CallInfo* info);
109 void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
110 void GenOrLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
111 void GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
112 void GenXorLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
113 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
114 ThrowKind kind);
115 RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
116 RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
117 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
118 void GenDivZeroCheck(int reg_lo, int reg_hi);
119 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
120 void GenExitSequence();
121 void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
122 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
123 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
124 void GenSelect(BasicBlock* bb, MIR* mir);
125 void GenMemBarrier(MemBarrierKind barrier_kind);
126 void GenMonitorEnter(int opt_flags, RegLocation rl_src);
127 void GenMonitorExit(int opt_flags, RegLocation rl_src);
128 void GenMoveException(RegLocation rl_dest);
129 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
130 int first_bit, int second_bit);
131 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
132 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
133 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
134 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSpecialCase(BasicBlock* bb, MIR* mir, SpecialCaseHandler special_case);
136
137 // Required for target - single operation generators.
138 LIR* OpUnconditionalBranch(LIR* target);
139 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
140 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
141 LIR* OpCondBranch(ConditionCode cc, LIR* target);
142 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
143 LIR* OpFpRegCopy(int r_dest, int r_src);
144 LIR* OpIT(ConditionCode cond, const char* guide);
145 LIR* OpMem(OpKind op, int rBase, int disp);
146 LIR* OpPcRelLoad(int reg, LIR* target);
147 LIR* OpReg(OpKind op, int r_dest_src);
148 LIR* OpRegCopy(int r_dest, int r_src);
149 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
150 LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
151 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
152 LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
153 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
154 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
155 LIR* OpTestSuspend(LIR* target);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame^]156 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]157 LIR* OpVldm(int rBase, int count);
158 LIR* OpVstm(int rBase, int count);
159 void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
160 void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
Ian Rogers468532e2013-08-05 10:56:33 -0700[diff] [blame^]161 void OpTlsCmp(ThreadOffset offset, int val);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700[diff] [blame]162
163 RegLocation ArgLoc(RegLocation loc);
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
165 int s_reg);
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
167 void GenPrintLabel(MIR* mir);
168 LIR* OpRegRegRegShift(OpKind op, int r_dest, int r_src1, int r_src2, int shift);
169 LIR* OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, int shift);
170 static const ArmEncodingMap EncodingMap[kArmLast];
171 int EncodeShift(int code, int amount);
172 int ModifiedImmediate(uint32_t value);
173 ArmConditionCode ArmConditionEncoding(ConditionCode code);
174 bool InexpensiveConstantInt(int32_t value);
175 bool InexpensiveConstantFloat(int32_t value);
176 bool InexpensiveConstantLong(int64_t value);
177 bool InexpensiveConstantDouble(int64_t value);
178
179 private:
180 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
181 ConditionCode ccode);
182 int InPosition(int s_reg);
183 RegLocation LoadArg(RegLocation loc);
184 void LockLiveArgs(MIR* mir);
185 MIR* GetNextMir(BasicBlock** p_bb, MIR* mir);
186 MIR* SpecialIGet(BasicBlock** bb, MIR* mir, OpSize size, bool long_or_double, bool is_object);
187 MIR* SpecialIPut(BasicBlock** bb, MIR* mir, OpSize size, bool long_or_double, bool is_object);
188 MIR* SpecialIdentity(MIR* mir);
189 LIR* LoadFPConstantValue(int r_dest, int value);
190 bool BadOverlap(RegLocation rl_src, RegLocation rl_dest);
191};
192
193} // namespace art
194
Brian Carlstromfc0e3212013-07-17 14:40:12 -0700[diff] [blame]195#endif // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_