blob: 9350677b3fa861317872a9f896eebddfb1fcc4c3 [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
Brian Carlstromfc0e3212013-07-17 14:40:12 -070017#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_
18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_
Brian Carlstrom7940e442013-07-12 13:46:57 -070019
20#include "invoke_type.h"
21#include "compiled_method.h"
22#include "dex/compiler_enums.h"
23#include "dex/compiler_ir.h"
Bill Buzbee00e1ec62014-02-27 23:44:13 +000024#include "dex/reg_storage.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070025#include "dex/backend.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070026#include "driver/compiler_driver.h"
Brian Carlstroma1ce1fe2014-02-24 23:23:58 -080027#include "leb128.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070028#include "safe_map.h"
Nicolas Geoffray818f2102014-02-18 16:43:35 +000029#include "utils/arena_allocator.h"
30#include "utils/growable_array.h"
Brian Carlstrom7940e442013-07-12 13:46:57 -070031
32namespace art {
33
buzbee0d829482013-10-11 15:24:55 -070034/*
35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to
36 * add type safety (see runtime/offsets.h).
37 */
38typedef uint32_t DexOffset; // Dex offset in code units.
39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff.
40typedef uint32_t CodeOffset; // Native code offset in bytes.
41
Brian Carlstrom7940e442013-07-12 13:46:57 -070042// Set to 1 to measure cost of suspend check.
43#define NO_SUSPEND 0
44
45#define IS_BINARY_OP (1ULL << kIsBinaryOp)
46#define IS_BRANCH (1ULL << kIsBranch)
47#define IS_IT (1ULL << kIsIT)
48#define IS_LOAD (1ULL << kMemLoad)
49#define IS_QUAD_OP (1ULL << kIsQuadOp)
50#define IS_QUIN_OP (1ULL << kIsQuinOp)
51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp)
52#define IS_STORE (1ULL << kMemStore)
53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp)
54#define IS_UNARY_OP (1ULL << kIsUnaryOp)
55#define NEEDS_FIXUP (1ULL << kPCRelFixup)
56#define NO_OPERAND (1ULL << kNoOperand)
57#define REG_DEF0 (1ULL << kRegDef0)
58#define REG_DEF1 (1ULL << kRegDef1)
59#define REG_DEFA (1ULL << kRegDefA)
60#define REG_DEFD (1ULL << kRegDefD)
61#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0)
62#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2)
63#define REG_DEF_LIST0 (1ULL << kRegDefList0)
64#define REG_DEF_LIST1 (1ULL << kRegDefList1)
65#define REG_DEF_LR (1ULL << kRegDefLR)
66#define REG_DEF_SP (1ULL << kRegDefSP)
67#define REG_USE0 (1ULL << kRegUse0)
68#define REG_USE1 (1ULL << kRegUse1)
69#define REG_USE2 (1ULL << kRegUse2)
70#define REG_USE3 (1ULL << kRegUse3)
71#define REG_USE4 (1ULL << kRegUse4)
72#define REG_USEA (1ULL << kRegUseA)
73#define REG_USEC (1ULL << kRegUseC)
74#define REG_USED (1ULL << kRegUseD)
Vladimir Marko70b797d2013-12-03 15:25:24 +000075#define REG_USEB (1ULL << kRegUseB)
Brian Carlstrom7940e442013-07-12 13:46:57 -070076#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0)
77#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2)
78#define REG_USE_LIST0 (1ULL << kRegUseList0)
79#define REG_USE_LIST1 (1ULL << kRegUseList1)
80#define REG_USE_LR (1ULL << kRegUseLR)
81#define REG_USE_PC (1ULL << kRegUsePC)
82#define REG_USE_SP (1ULL << kRegUseSP)
83#define SETS_CCODES (1ULL << kSetsCCodes)
84#define USES_CCODES (1ULL << kUsesCCodes)
85
86// Common combo register usage patterns.
87#define REG_DEF01 (REG_DEF0 | REG_DEF1)
88#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
89#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01)
90#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0)
91#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12)
Vladimir Marko3e5af822013-11-21 15:01:20 +000092#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123)
Brian Carlstrom7940e442013-07-12 13:46:57 -070093#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1)
94#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2)
95#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED)
96#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD)
97#define REG_DEFA_USEA (REG_DEFA | REG_USEA)
98#define REG_USE012 (REG_USE01 | REG_USE2)
99#define REG_USE014 (REG_USE01 | REG_USE4)
100#define REG_USE01 (REG_USE0 | REG_USE1)
101#define REG_USE02 (REG_USE0 | REG_USE2)
102#define REG_USE12 (REG_USE1 | REG_USE2)
103#define REG_USE23 (REG_USE2 | REG_USE3)
Vladimir Marko3e5af822013-11-21 15:01:20 +0000104#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3)
Brian Carlstrom7940e442013-07-12 13:46:57 -0700105
106struct BasicBlock;
107struct CallInfo;
108struct CompilationUnit;
Vladimir Marko5816ed42013-11-27 17:04:20 +0000109struct InlineMethod;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700110struct MIR;
buzbeeb48819d2013-09-14 16:15:25 -0700111struct LIR;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700112struct RegLocation;
113struct RegisterInfo;
Vladimir Marko5c96e6b2013-11-14 15:34:17 +0000114class DexFileMethodInliner;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700115class MIRGraph;
116class Mir2Lir;
117
118typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int,
119 const MethodReference& target_method,
120 uint32_t method_idx, uintptr_t direct_code,
121 uintptr_t direct_method, InvokeType type);
122
123typedef std::vector<uint8_t> CodeBuffer;
124
buzbeeb48819d2013-09-14 16:15:25 -0700125struct UseDefMasks {
126 uint64_t use_mask; // Resource mask for use.
127 uint64_t def_mask; // Resource mask for def.
128};
129
130struct AssemblyInfo {
131 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups.
132 uint8_t bytes[16]; // Encoded instruction bytes.
133};
Brian Carlstrom7940e442013-07-12 13:46:57 -0700134
135struct LIR {
buzbee0d829482013-10-11 15:24:55 -0700136 CodeOffset offset; // Offset of this instruction.
137 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words).
buzbeeb48819d2013-09-14 16:15:25 -0700138 int16_t opcode;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700139 LIR* next;
140 LIR* prev;
141 LIR* target;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700142 struct {
buzbeeb48819d2013-09-14 16:15:25 -0700143 unsigned int alias_info:17; // For Dalvik register disambiguation.
144 bool is_nop:1; // LIR is optimized away.
145 unsigned int size:4; // Note: size of encoded instruction is in bytes.
146 bool use_def_invalid:1; // If true, masks should not be used.
147 unsigned int generation:1; // Used to track visitation state during fixup pass.
148 unsigned int fixup:8; // Fixup kind.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700149 } flags;
buzbeeb48819d2013-09-14 16:15:25 -0700150 union {
buzbee0d829482013-10-11 15:24:55 -0700151 UseDefMasks m; // Use & Def masks used during optimization.
152 AssemblyInfo a; // Instruction encoding used during assembly phase.
buzbeeb48819d2013-09-14 16:15:25 -0700153 } u;
buzbee0d829482013-10-11 15:24:55 -0700154 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2].
Brian Carlstrom7940e442013-07-12 13:46:57 -0700155};
156
157// Target-specific initialization.
158Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
159 ArenaAllocator* const arena);
160Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
161 ArenaAllocator* const arena);
162Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
163 ArenaAllocator* const arena);
164
165// Utility macros to traverse the LIR list.
166#define NEXT_LIR(lir) (lir->next)
167#define PREV_LIR(lir) (lir->prev)
168
169// Defines for alias_info (tracks Dalvik register references).
170#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff)
buzbeeb48819d2013-09-14 16:15:25 -0700171#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000)
Brian Carlstrom7940e442013-07-12 13:46:57 -0700172#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0)
173#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0))
174
175// Common resource macros.
176#define ENCODE_CCODE (1ULL << kCCode)
177#define ENCODE_FP_STATUS (1ULL << kFPStatus)
178
179// Abstract memory locations.
180#define ENCODE_DALVIK_REG (1ULL << kDalvikReg)
181#define ENCODE_LITERAL (1ULL << kLiteral)
182#define ENCODE_HEAP_REF (1ULL << kHeapRef)
183#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias)
184
185#define ENCODE_ALL (~0ULL)
186#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \
187 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS)
buzbeec729a6b2013-09-14 16:04:31 -0700188
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -0800189#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8))
190#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \
191 do { \
192 low_reg = both_regs & 0xff; \
193 high_reg = (both_regs >> 8) & 0xff; \
194 } while (false)
195
buzbeec729a6b2013-09-14 16:04:31 -0700196// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits.
197#define STARTING_DOUBLE_SREG 0x10000
198
Brian Carlstrom7934ac22013-07-26 10:54:15 -0700199// TODO: replace these macros
Brian Carlstrom7940e442013-07-12 13:46:57 -0700200#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath))
201#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath))
202#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath))
203#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath))
204#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath))
Brian Carlstrom7940e442013-07-12 13:46:57 -0700205
206class Mir2Lir : public Backend {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700207 public:
buzbee0d829482013-10-11 15:24:55 -0700208 /*
209 * Auxiliary information describing the location of data embedded in the Dalvik
210 * byte code stream.
211 */
212 struct EmbeddedData {
213 CodeOffset offset; // Code offset of data block.
214 const uint16_t* table; // Original dex data.
215 DexOffset vaddr; // Dalvik offset of parent opcode.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700216 };
217
buzbee0d829482013-10-11 15:24:55 -0700218 struct FillArrayData : EmbeddedData {
219 int32_t size;
220 };
221
222 struct SwitchTable : EmbeddedData {
223 LIR* anchor; // Reference instruction for relative offsets.
224 LIR** targets; // Array of case targets.
Brian Carlstrom7940e442013-07-12 13:46:57 -0700225 };
226
227 /* Static register use counts */
228 struct RefCounts {
229 int count;
230 int s_reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700231 };
232
233 /*
234 * Data structure tracking the mapping between a Dalvik register (pair) and a
235 * native register (pair). The idea is to reuse the previously loaded value
236 * if possible, otherwise to keep the value in a native register as long as
237 * possible.
238 */
239 struct RegisterInfo {
240 int reg; // Reg number
241 bool in_use; // Has it been allocated?
242 bool is_temp; // Can allocate as temp?
243 bool pair; // Part of a register pair?
244 int partner; // If pair, other reg of pair.
245 bool live; // Is there an associated SSA name?
246 bool dirty; // If live, is it dirty?
247 int s_reg; // Name of live value.
248 LIR *def_start; // Starting inst in last def sequence.
249 LIR *def_end; // Ending inst in last def sequence.
250 };
251
Brian Carlstrom6f485c62013-07-18 15:35:35 -0700252 struct RegisterPool {
253 int num_core_regs;
254 RegisterInfo *core_regs;
255 int next_core_reg;
256 int num_fp_regs;
257 RegisterInfo *FPRegs;
258 int next_fp_reg;
259 };
Brian Carlstrom7940e442013-07-12 13:46:57 -0700260
261 struct PromotionMap {
262 RegLocationType core_location:3;
263 uint8_t core_reg;
264 RegLocationType fp_location:3;
265 uint8_t FpReg;
266 bool first_in_pair;
267 };
268
Dave Allisonbcec6fb2014-01-17 12:52:22 -0800269 //
270 // Slow paths. This object is used generate a sequence of code that is executed in the
271 // slow path. For example, resolving a string or class is slow as it will only be executed
272 // once (after that it is resolved and doesn't need to be done again). We want slow paths
273 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward
274 // branch over them.
275 //
276 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide
277 // the Compile() function that will be called near the end of the code generated by the
278 // method.
279 //
280 // The basic flow for a slow path is:
281 //
282 // CMP reg, #value
283 // BEQ fromfast
284 // cont:
285 // ...
286 // fast path code
287 // ...
288 // more code
289 // ...
290 // RETURN
291 ///
292 // fromfast:
293 // ...
294 // slow path code
295 // ...
296 // B cont
297 //
298 // So you see we need two labels and two branches. The first branch (called fromfast) is
299 // the conditional branch to the slow path code. The second label (called cont) is used
300 // as an unconditional branch target for getting back to the code after the slow path
301 // has completed.
302 //
303
304 class LIRSlowPath {
305 public:
306 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast,
307 LIR* cont = nullptr) :
308 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) {
309 }
310 virtual ~LIRSlowPath() {}
311 virtual void Compile() = 0;
312
313 static void* operator new(size_t size, ArenaAllocator* arena) {
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000314 return arena->Alloc(size, kArenaAllocData);
Dave Allisonbcec6fb2014-01-17 12:52:22 -0800315 }
316
317 protected:
318 LIR* GenerateTargetLabel();
319
320 Mir2Lir* const m2l_;
321 const DexOffset current_dex_pc_;
322 LIR* const fromfast_;
323 LIR* const cont_;
324 };
325
Brian Carlstrom9b7085a2013-07-18 15:15:21 -0700326 virtual ~Mir2Lir() {}
Brian Carlstrom7940e442013-07-12 13:46:57 -0700327
328 int32_t s4FromSwitchData(const void* switch_data) {
329 return *reinterpret_cast<const int32_t*>(switch_data);
330 }
331
332 RegisterClass oat_reg_class_by_size(OpSize size) {
333 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte ||
Brian Carlstromdf629502013-07-17 22:39:56 -0700334 size == kSignedByte) ? kCoreReg : kAnyReg;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700335 }
336
337 size_t CodeBufferSizeInBytes() {
338 return code_buffer_.size() / sizeof(code_buffer_[0]);
339 }
340
buzbee409fe942013-10-11 10:49:56 -0700341 bool IsPseudoLirOp(int opcode) {
342 return (opcode < 0);
343 }
344
buzbee0d829482013-10-11 15:24:55 -0700345 /*
346 * LIR operands are 32-bit integers. Sometimes, (especially for managing
347 * instructions which require PC-relative fixups), we need the operands to carry
348 * pointers. To do this, we assign these pointers an index in pointer_storage_, and
349 * hold that index in the operand array.
350 * TUNING: If use of these utilities becomes more common on 32-bit builds, it
351 * may be worth conditionally-compiling a set of identity functions here.
352 */
353 uint32_t WrapPointer(void* pointer) {
354 uint32_t res = pointer_storage_.Size();
355 pointer_storage_.Insert(pointer);
356 return res;
357 }
358
359 void* UnwrapPointer(size_t index) {
360 return pointer_storage_.Get(index);
361 }
362
363 // strdup(), but allocates from the arena.
364 char* ArenaStrdup(const char* str) {
365 size_t len = strlen(str) + 1;
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000366 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc));
buzbee0d829482013-10-11 15:24:55 -0700367 if (res != NULL) {
368 strncpy(res, str, len);
369 }
370 return res;
371 }
372
Brian Carlstrom7940e442013-07-12 13:46:57 -0700373 // Shared by all targets - implemented in codegen_util.cc
374 void AppendLIR(LIR* lir);
375 void InsertLIRBefore(LIR* current_lir, LIR* new_lir);
376 void InsertLIRAfter(LIR* current_lir, LIR* new_lir);
377
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -0800378 /**
379 * @brief Provides the maximum number of compiler temporaries that the backend can/wants
380 * to place in a frame.
381 * @return Returns the maximum number of compiler temporaries.
382 */
383 size_t GetMaxPossibleCompilerTemps() const;
384
385 /**
386 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries.
387 * @return Returns the size in bytes for space needed for compiler temporary spill region.
388 */
389 size_t GetNumBytesForCompilerTempSpillRegion();
390
Dave Allisonbcec6fb2014-01-17 12:52:22 -0800391 DexOffset GetCurrentDexPc() const {
392 return current_dalvik_offset_;
393 }
394
Brian Carlstrom7940e442013-07-12 13:46:57 -0700395 int ComputeFrameSize();
396 virtual void Materialize();
397 virtual CompiledMethod* GetCompiledMethod();
398 void MarkSafepointPC(LIR* inst);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700399 void SetupResourceMasks(LIR* lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700400 void SetMemRefType(LIR* lir, bool is_load, int mem_type);
401 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
402 void SetupRegMask(uint64_t* mask, int reg);
403 void DumpLIRInsn(LIR* arg, unsigned char* base_addr);
404 void DumpPromotionMap();
405 void CodegenDump();
buzbee0d829482013-10-11 15:24:55 -0700406 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700407 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL);
408 LIR* NewLIR0(int opcode);
409 LIR* NewLIR1(int opcode, int dest);
410 LIR* NewLIR2(int opcode, int dest, int src1);
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800411 LIR* NewLIR2NoDest(int opcode, int src, int info);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700412 LIR* NewLIR3(int opcode, int dest, int src1, int src2);
413 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info);
414 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2);
415 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta);
416 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi);
417 LIR* AddWordData(LIR* *constant_list_p, int value);
418 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi);
419 void ProcessSwitchTables();
420 void DumpSparseSwitchTable(const uint16_t* table);
421 void DumpPackedSwitchTable(const uint16_t* table);
buzbee0d829482013-10-11 15:24:55 -0700422 void MarkBoundary(DexOffset offset, const char* inst_str);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700423 void NopLIR(LIR* lir);
buzbee252254b2013-09-08 16:20:53 -0700424 void UnlinkLIR(LIR* lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700425 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2);
426 bool IsInexpensiveConstant(RegLocation rl_src);
427 ConditionCode FlipComparisonOrder(ConditionCode before);
Vladimir Markoa1a70742014-03-03 10:28:05 +0000428 ConditionCode NegateComparison(ConditionCode before);
Mark Mendell55d0eac2014-02-06 11:02:52 -0800429 virtual void InstallLiteralPools();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700430 void InstallSwitchTables();
431 void InstallFillArrayData();
432 bool VerifyCatchEntries();
433 void CreateMappingTables();
434 void CreateNativeGcMap();
buzbee0d829482013-10-11 15:24:55 -0700435 int AssignLiteralOffset(CodeOffset offset);
436 int AssignSwitchTablesOffset(CodeOffset offset);
437 int AssignFillArrayDataOffset(CodeOffset offset);
438 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal);
439 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec);
440 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700441
442 // Shared by all targets - implemented in local_optimizations.cc
443 void ConvertMemOpIntoMove(LIR* orig_lir, int dest, int src);
444 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir);
445 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir);
446 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700447
448 // Shared by all targets - implemented in ralloc_util.cc
449 int GetSRegHi(int lowSreg);
450 bool oat_live_out(int s_reg);
451 int oatSSASrc(MIR* mir, int num);
452 void SimpleRegAlloc();
453 void ResetRegPool();
454 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num);
455 void DumpRegPool(RegisterInfo* p, int num_regs);
456 void DumpCoreRegPool();
457 void DumpFpRegPool();
458 /* Mark a temp register as dead. Does not affect allocation state. */
459 void Clobber(int reg) {
460 ClobberBody(GetRegInfo(reg));
461 }
462 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg);
463 void ClobberSReg(int s_reg);
464 int SRegToPMap(int s_reg);
465 void RecordCorePromotion(int reg, int s_reg);
466 int AllocPreservedCoreReg(int s_reg);
467 void RecordFpPromotion(int reg, int s_reg);
buzbeec729a6b2013-09-14 16:04:31 -0700468 int AllocPreservedSingle(int s_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700469 int AllocPreservedDouble(int s_reg);
buzbeec729a6b2013-09-14 16:04:31 -0700470 int AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required);
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000471 virtual int AllocTempDouble();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700472 int AllocFreeTemp();
473 int AllocTemp();
474 int AllocTempFloat();
475 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg);
476 RegisterInfo* AllocLive(int s_reg, int reg_class);
477 void FreeTemp(int reg);
478 RegisterInfo* IsLive(int reg);
479 RegisterInfo* IsTemp(int reg);
480 RegisterInfo* IsPromoted(int reg);
481 bool IsDirty(int reg);
482 void LockTemp(int reg);
483 void ResetDef(int reg);
484 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2);
485 void MarkDef(RegLocation rl, LIR *start, LIR *finish);
486 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish);
487 RegLocation WideToNarrow(RegLocation rl);
488 void ResetDefLoc(RegLocation rl);
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000489 virtual void ResetDefLocWide(RegLocation rl);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700490 void ResetDefTracking();
491 void ClobberAllRegs();
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800492 void FlushSpecificReg(RegisterInfo* info);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700493 void FlushAllRegsBody(RegisterInfo* info, int num_regs);
494 void FlushAllRegs();
495 bool RegClassMatches(int reg_class, int reg);
496 void MarkLive(int reg, int s_reg);
497 void MarkTemp(int reg);
498 void UnmarkTemp(int reg);
499 void MarkPair(int low_reg, int high_reg);
500 void MarkClean(RegLocation loc);
501 void MarkDirty(RegLocation loc);
502 void MarkInUse(int reg);
503 void CopyRegInfo(int new_reg, int old_reg);
504 bool CheckCorePoolSanity();
505 RegLocation UpdateLoc(RegLocation loc);
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000506 virtual RegLocation UpdateLocWide(RegLocation loc);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700507 RegLocation UpdateRawLoc(RegLocation loc);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800508
509 /**
510 * @brief Used to load register location into a typed temporary or pair of temporaries.
511 * @see EvalLoc
512 * @param loc The register location to load from.
513 * @param reg_class Type of register needed.
514 * @param update Whether the liveness information should be updated.
515 * @return Returns the properly typed temporary in physical register pairs.
516 */
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000517 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800518
519 /**
520 * @brief Used to load register location into a typed temporary.
521 * @param loc The register location to load from.
522 * @param reg_class Type of register needed.
523 * @param update Whether the liveness information should be updated.
524 * @return Returns the properly typed temporary in physical register.
525 */
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000526 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800527
buzbeec729a6b2013-09-14 16:04:31 -0700528 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700529 void DumpCounts(const RefCounts* arr, int size, const char* msg);
530 void DoPromotion();
531 int VRegOffset(int v_reg);
532 int SRegOffset(int s_reg);
533 RegLocation GetReturnWide(bool is_double);
534 RegLocation GetReturn(bool is_float);
buzbeebd663de2013-09-10 15:41:31 -0700535 RegisterInfo* GetRegInfo(int reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700536
537 // Shared by all targets - implemented in gen_common.cc.
buzbee11b63d12013-08-27 07:34:17 -0700538 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700539 RegLocation rl_src, RegLocation rl_dest, int lit);
540 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit);
541 void HandleSuspendLaunchPads();
542 void HandleIntrinsicLaunchPads();
543 void HandleThrowLaunchPads();
Dave Allisonbcec6fb2014-01-17 12:52:22 -0800544 void HandleSlowPaths();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700545 void GenBarrier();
546 LIR* GenCheck(ConditionCode c_code, ThrowKind kind);
547 LIR* GenImmedCheck(ConditionCode c_code, int reg, int imm_val,
548 ThrowKind kind);
549 LIR* GenNullCheck(int s_reg, int m_reg, int opt_flags);
550 LIR* GenRegRegCheck(ConditionCode c_code, int reg1, int reg2,
551 ThrowKind kind);
552 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
553 RegLocation rl_src2, LIR* taken, LIR* fall_through);
554 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src,
555 LIR* taken, LIR* fall_through);
556 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src);
557 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
558 RegLocation rl_src);
559 void GenNewArray(uint32_t type_idx, RegLocation rl_dest,
560 RegLocation rl_src);
561 void GenFilledNewArray(CallInfo* info);
Vladimir Markobe0e5462014-02-26 11:24:15 +0000562 void GenSput(MIR* mir, RegLocation rl_src,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700563 bool is_long_or_double, bool is_object);
Vladimir Markobe0e5462014-02-26 11:24:15 +0000564 void GenSget(MIR* mir, RegLocation rl_dest,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700565 bool is_long_or_double, bool is_object);
Vladimir Markobe0e5462014-02-26 11:24:15 +0000566 void GenIGet(MIR* mir, int opt_flags, OpSize size,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700567 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object);
Vladimir Markobe0e5462014-02-26 11:24:15 +0000568 void GenIPut(MIR* mir, int opt_flags, OpSize size,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700569 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object);
Ian Rogersa9a82542013-10-04 11:17:26 -0700570 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index,
571 RegLocation rl_src);
572
Brian Carlstrom7940e442013-07-12 13:46:57 -0700573 void GenConstClass(uint32_t type_idx, RegLocation rl_dest);
574 void GenConstString(uint32_t string_idx, RegLocation rl_dest);
575 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest);
576 void GenThrow(RegLocation rl_src);
577 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest,
578 RegLocation rl_src);
579 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx,
580 RegLocation rl_src);
581 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest,
582 RegLocation rl_src1, RegLocation rl_src2);
583 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
584 RegLocation rl_src1, RegLocation rl_shift);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700585 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest,
586 RegLocation rl_src, int lit);
587 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,
588 RegLocation rl_src1, RegLocation rl_src2);
Ian Rogers468532e2013-08-05 10:56:33 -0700589 void GenConversionCall(ThreadOffset func_offset, RegLocation rl_dest,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700590 RegLocation rl_src);
591 void GenSuspendTest(int opt_flags);
592 void GenSuspendTestAndBranch(int opt_flags, LIR* target);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800593
Bill Buzbeed61ba4b2014-01-13 21:44:01 +0000594 // This will be overridden by x86 implementation.
595 virtual void GenConstWide(RegLocation rl_dest, int64_t value);
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800596 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
597 RegLocation rl_src1, RegLocation rl_src2);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700598
599 // Shared by all targets - implemented in gen_invoke.cc.
Ian Rogers468532e2013-08-05 10:56:33 -0700600 int CallHelperSetup(ThreadOffset helper_offset);
601 LIR* CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc);
602 void CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc);
603 void CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc);
604 void CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0,
605 bool safepoint_pc);
606 void CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700607 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700608 void CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700609 RegLocation arg1, bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700610 void CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700611 int arg1, bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700612 void CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700613 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700614 void CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700615 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700616 void CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700617 bool safepoint_pc);
Hiroshi Yamauchibe1ca552014-01-15 11:46:48 -0800618 void CallRuntimeHelperRegMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc);
Hiroshi Yamauchibb8f0ab2014-01-27 16:50:29 -0800619 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset helper_offset, int arg0,
620 RegLocation arg2, bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700621 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700622 RegLocation arg0, RegLocation arg1,
623 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700624 void CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700625 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700626 void CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700627 int arg2, bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700628 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, int arg0,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700629 RegLocation arg2, bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700630 void CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, int arg2,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700631 bool safepoint_pc);
Ian Rogers468532e2013-08-05 10:56:33 -0700632 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700633 int arg0, RegLocation arg1, RegLocation arg2,
634 bool safepoint_pc);
Ian Rogersa9a82542013-10-04 11:17:26 -0700635 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset,
636 RegLocation arg0, RegLocation arg1,
637 RegLocation arg2,
638 bool safepoint_pc);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700639 void GenInvoke(CallInfo* info);
640 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method);
641 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel,
642 NextCallInsn next_call_insn,
643 const MethodReference& target_method,
644 uint32_t vtable_idx,
645 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
646 bool skip_this);
647 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel,
648 NextCallInsn next_call_insn,
649 const MethodReference& target_method,
650 uint32_t vtable_idx,
651 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
652 bool skip_this);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800653
654 /**
655 * @brief Used to determine the register location of destination.
656 * @details This is needed during generation of inline intrinsics because it finds destination of return,
657 * either the physical register or the target of move-result.
658 * @param info Information about the invoke.
659 * @return Returns the destination location.
660 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700661 RegLocation InlineTarget(CallInfo* info);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800662
663 /**
664 * @brief Used to determine the wide register location of destination.
665 * @see InlineTarget
666 * @param info Information about the invoke.
667 * @return Returns the destination location.
668 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700669 RegLocation InlineTargetWide(CallInfo* info);
670
671 bool GenInlinedCharAt(CallInfo* info);
672 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty);
Vladimir Marko6bdf1ff2013-10-29 17:40:46 +0000673 bool GenInlinedReverseBytes(CallInfo* info, OpSize size);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700674 bool GenInlinedAbsInt(CallInfo* info);
675 bool GenInlinedAbsLong(CallInfo* info);
Yixin Shoudbb17e32014-02-07 05:09:30 -0800676 bool GenInlinedAbsFloat(CallInfo* info);
677 bool GenInlinedAbsDouble(CallInfo* info);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700678 bool GenInlinedFloatCvt(CallInfo* info);
679 bool GenInlinedDoubleCvt(CallInfo* info);
Mark Mendell4028a6c2014-02-19 20:06:20 -0800680 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700681 bool GenInlinedStringCompareTo(CallInfo* info);
682 bool GenInlinedCurrentThread(CallInfo* info);
683 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile);
684 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object,
685 bool is_volatile, bool is_ordered);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700686 int LoadArgRegs(CallInfo* info, int call_state,
687 NextCallInsn next_call_insn,
688 const MethodReference& target_method,
689 uint32_t vtable_idx,
690 uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
691 bool skip_this);
692
693 // Shared by all targets - implemented in gen_loadstore.cc.
694 RegLocation LoadCurrMethod();
695 void LoadCurrMethodDirect(int r_tgt);
696 LIR* LoadConstant(int r_dest, int value);
697 LIR* LoadWordDisp(int rBase, int displacement, int r_dest);
698 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind);
699 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind);
700 void LoadValueDirect(RegLocation rl_src, int r_dest);
701 void LoadValueDirectFixed(RegLocation rl_src, int r_dest);
702 void LoadValueDirectWide(RegLocation rl_src, int reg_lo, int reg_hi);
703 void LoadValueDirectWideFixed(RegLocation rl_src, int reg_lo, int reg_hi);
704 LIR* StoreWordDisp(int rBase, int displacement, int r_src);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800705
706 /**
707 * @brief Used to do the final store in the destination as per bytecode semantics.
708 * @param rl_dest The destination dalvik register location.
709 * @param rl_src The source register location. Can be either physical register or dalvik register.
710 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700711 void StoreValue(RegLocation rl_dest, RegLocation rl_src);
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800712
713 /**
714 * @brief Used to do the final store in a wide destination as per bytecode semantics.
715 * @see StoreValue
716 * @param rl_dest The destination dalvik register location.
717 * @param rl_src The source register location. Can be either physical register or dalvik register.
718 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700719 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src);
720
Mark Mendelle02d48f2014-01-15 11:19:23 -0800721 /**
Mark Mendellfeb2b4e2014-01-28 12:59:49 -0800722 * @brief Used to do the final store to a destination as per bytecode semantics.
723 * @see StoreValue
724 * @param rl_dest The destination dalvik register location.
725 * @param rl_src The source register location. It must be kLocPhysReg
726 *
727 * This is used for x86 two operand computations, where we have computed the correct
728 * register value that now needs to be properly registered. This is used to avoid an
729 * extra register copy that would result if StoreValue was called.
730 */
731 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src);
732
733 /**
Mark Mendelle02d48f2014-01-15 11:19:23 -0800734 * @brief Used to do the final store in a wide destination as per bytecode semantics.
735 * @see StoreValueWide
736 * @param rl_dest The destination dalvik register location.
737 * @param rl_src The source register location. It must be kLocPhysReg
738 *
739 * This is used for x86 two operand computations, where we have computed the correct
740 * register values that now need to be properly registered. This is used to avoid an
741 * extra pair of register copies that would result if StoreValueWide was called.
742 */
743 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src);
744
Brian Carlstrom7940e442013-07-12 13:46:57 -0700745 // Shared by all targets - implemented in mir_to_lir.cc.
746 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list);
747 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir);
748 bool MethodBlockCodeGen(BasicBlock* bb);
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -0800749 bool SpecialMIR2LIR(const InlineMethod& special);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700750 void MethodMIR2LIR();
751
Mark Mendell55d0eac2014-02-06 11:02:52 -0800752 /*
753 * @brief Load the address of the dex method into the register.
Jeff Hao49161ce2014-03-12 11:05:25 -0700754 * @param target_method The MethodReference of the method to be invoked.
Mark Mendell55d0eac2014-02-06 11:02:52 -0800755 * @param type How the method will be invoked.
756 * @param register that will contain the code address.
757 * @note register will be passed to TargetReg to get physical register.
758 */
Jeff Hao49161ce2014-03-12 11:05:25 -0700759 void LoadCodeAddress(const MethodReference& target_method, InvokeType type,
Mark Mendell55d0eac2014-02-06 11:02:52 -0800760 SpecialTargetRegister symbolic_reg);
761
762 /*
763 * @brief Load the Method* of a dex method into the register.
Jeff Hao49161ce2014-03-12 11:05:25 -0700764 * @param target_method The MethodReference of the method to be invoked.
Mark Mendell55d0eac2014-02-06 11:02:52 -0800765 * @param type How the method will be invoked.
766 * @param register that will contain the code address.
767 * @note register will be passed to TargetReg to get physical register.
768 */
Jeff Hao49161ce2014-03-12 11:05:25 -0700769 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type,
Mark Mendell55d0eac2014-02-06 11:02:52 -0800770 SpecialTargetRegister symbolic_reg);
771
772 /*
773 * @brief Load the Class* of a Dex Class type into the register.
774 * @param type How the method will be invoked.
775 * @param register that will contain the code address.
776 * @note register will be passed to TargetReg to get physical register.
777 */
778 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg);
779
Mark Mendell766e9292014-01-27 07:55:47 -0800780 // Routines that work for the generic case, but may be overriden by target.
781 /*
782 * @brief Compare memory to immediate, and branch if condition true.
783 * @param cond The condition code that when true will branch to the target.
784 * @param temp_reg A temporary register that can be used if compare to memory is not
785 * supported by the architecture.
786 * @param base_reg The register holding the base address.
787 * @param offset The offset from the base.
788 * @param check_value The immediate to compare to.
789 * @returns The branch instruction that was generated.
790 */
791 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
792 int offset, int check_value, LIR* target);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700793
794 // Required for target - codegen helpers.
buzbee11b63d12013-08-27 07:34:17 -0700795 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700796 RegLocation rl_src, RegLocation rl_dest, int lit) = 0;
Ian Rogers468532e2013-08-05 10:56:33 -0700797 virtual int LoadHelper(ThreadOffset offset) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700798 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
799 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
800 int s_reg) = 0;
801 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
802 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
803 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0;
804 virtual LIR* LoadConstantNoClobber(int r_dest, int value) = 0;
805 virtual LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) = 0;
806 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0;
807 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0;
808 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0;
809 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
810 int r_src, int r_src_hi, OpSize size, int s_reg) = 0;
811 virtual void MarkGCCard(int val_reg, int tgt_addr_reg) = 0;
812
813 // Required for target - register utilities.
814 virtual bool IsFpReg(int reg) = 0;
815 virtual bool SameRegType(int reg1, int reg2) = 0;
816 virtual int AllocTypedTemp(bool fp_hint, int reg_class) = 0;
Bill Buzbee00e1ec62014-02-27 23:44:13 +0000817 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700818 virtual int S2d(int low_reg, int high_reg) = 0;
819 virtual int TargetReg(SpecialTargetRegister reg) = 0;
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -0800820 virtual int GetArgMappingToPhysicalReg(int arg_num) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700821 virtual RegLocation GetReturnAlt() = 0;
822 virtual RegLocation GetReturnWideAlt() = 0;
823 virtual RegLocation LocCReturn() = 0;
824 virtual RegLocation LocCReturnDouble() = 0;
825 virtual RegLocation LocCReturnFloat() = 0;
826 virtual RegLocation LocCReturnWide() = 0;
827 virtual uint32_t FpRegMask() = 0;
828 virtual uint64_t GetRegMaskCommon(int reg) = 0;
829 virtual void AdjustSpillMask() = 0;
Vladimir Marko31c2aac2013-12-09 16:31:19 +0000830 virtual void ClobberCallerSave() = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700831 virtual void FlushReg(int reg) = 0;
832 virtual void FlushRegWide(int reg1, int reg2) = 0;
833 virtual void FreeCallTemps() = 0;
834 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0;
835 virtual void LockCallTemps() = 0;
836 virtual void MarkPreservedSingle(int v_reg, int reg) = 0;
837 virtual void CompilerInitializeRegAlloc() = 0;
838
839 // Required for target - miscellaneous.
buzbeeb48819d2013-09-14 16:15:25 -0700840 virtual void AssembleLIR() = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700841 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0;
buzbeeb48819d2013-09-14 16:15:25 -0700842 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700843 virtual const char* GetTargetInstFmt(int opcode) = 0;
844 virtual const char* GetTargetInstName(int opcode) = 0;
845 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0;
846 virtual uint64_t GetPCUseDefEncoding() = 0;
847 virtual uint64_t GetTargetInstFlags(int opcode) = 0;
848 virtual int GetInsnSize(LIR* lir) = 0;
849 virtual bool IsUnconditionalBranch(LIR* lir) = 0;
850
851 // Required for target - Dalvik-level generators.
852 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
853 RegLocation rl_src1, RegLocation rl_src2) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800854 virtual void GenMulLong(Instruction::Code,
855 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700856 RegLocation rl_src2) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800857 virtual void GenAddLong(Instruction::Code,
858 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700859 RegLocation rl_src2) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800860 virtual void GenAndLong(Instruction::Code,
861 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700862 RegLocation rl_src2) = 0;
863 virtual void GenArithOpDouble(Instruction::Code opcode,
864 RegLocation rl_dest, RegLocation rl_src1,
865 RegLocation rl_src2) = 0;
866 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
867 RegLocation rl_src1, RegLocation rl_src2) = 0;
868 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest,
869 RegLocation rl_src1, RegLocation rl_src2) = 0;
870 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest,
871 RegLocation rl_src) = 0;
Vladimir Marko1c282e22013-11-21 14:49:47 +0000872 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800873
874 /**
875 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max.
876 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm
877 * that applies on integers. The generated code will write the smallest or largest value
878 * directly into the destination register as specified by the invoke information.
879 * @param info Information about the invoke.
880 * @param is_min If true generates code that computes minimum. Otherwise computes maximum.
881 * @return Returns true if successfully generated
882 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700883 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800884
Brian Carlstrom7940e442013-07-12 13:46:57 -0700885 virtual bool GenInlinedSqrt(CallInfo* info) = 0;
Vladimir Markoe508a202013-11-04 15:24:22 +0000886 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0;
887 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700888 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800889 virtual void GenOrLong(Instruction::Code,
890 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700891 RegLocation rl_src2) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800892 virtual void GenSubLong(Instruction::Code,
893 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700894 RegLocation rl_src2) = 0;
Mark Mendelle02d48f2014-01-15 11:19:23 -0800895 virtual void GenXorLong(Instruction::Code,
896 RegLocation rl_dest, RegLocation rl_src1,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700897 RegLocation rl_src2) = 0;
898 virtual LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base,
899 int offset, ThrowKind kind) = 0;
900 virtual RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi,
901 bool is_div) = 0;
902 virtual RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit,
903 bool is_div) = 0;
Mark Mendell2bf31e62014-01-23 12:13:40 -0800904 /*
905 * @brief Generate an integer div or rem operation by a literal.
906 * @param rl_dest Destination Location.
907 * @param rl_src1 Numerator Location.
908 * @param rl_src2 Divisor Location.
909 * @param is_div 'true' if this is a division, 'false' for a remainder.
910 * @param check_zero 'true' if an exception should be generated if the divisor is 0.
911 */
912 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
913 RegLocation rl_src2, bool is_div, bool check_zero) = 0;
914 /*
915 * @brief Generate an integer div or rem operation by a literal.
916 * @param rl_dest Destination Location.
917 * @param rl_src Numerator Location.
918 * @param lit Divisor.
919 * @param is_div 'true' if this is a division, 'false' for a remainder.
920 */
921 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1,
922 int lit, bool is_div) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700923 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
924 RegLocation rl_src2) = 0;
Razvan A Lupusoru090dd442013-12-20 14:35:03 -0800925
926 /**
927 * @brief Used for generating code that throws ArithmeticException if both registers are zero.
928 * @details This is used for generating DivideByZero checks when divisor is held in two separate registers.
929 * @param reg_lo The register holding the lower 32-bits.
930 * @param reg_hi The register holding the upper 32-bits.
931 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700932 virtual void GenDivZeroCheck(int reg_lo, int reg_hi) = 0;
Razvan A Lupusoru090dd442013-12-20 14:35:03 -0800933
Brian Carlstrom7940e442013-07-12 13:46:57 -0700934 virtual void GenEntrySequence(RegLocation* ArgLocs,
935 RegLocation rl_method) = 0;
936 virtual void GenExitSequence() = 0;
buzbee0d829482013-10-11 15:24:55 -0700937 virtual void GenFillArrayData(DexOffset table_offset,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700938 RegLocation rl_src) = 0;
939 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
940 bool is_double) = 0;
941 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0;
Razvan A Lupusorue27b3bf2014-01-23 09:41:45 -0800942
943 /**
944 * @brief Lowers the kMirOpSelect MIR into LIR.
945 * @param bb The basic block in which the MIR is from.
946 * @param mir The MIR whose opcode is kMirOpSelect.
947 */
Brian Carlstrom7940e442013-07-12 13:46:57 -0700948 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0;
Razvan A Lupusorue27b3bf2014-01-23 09:41:45 -0800949
Brian Carlstrom7940e442013-07-12 13:46:57 -0700950 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700951 virtual void GenMoveException(RegLocation rl_dest) = 0;
952 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
953 RegLocation rl_result, int lit, int first_bit,
954 int second_bit) = 0;
955 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0;
956 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0;
buzbee0d829482013-10-11 15:24:55 -0700957 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700958 RegLocation rl_src) = 0;
buzbee0d829482013-10-11 15:24:55 -0700959 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset,
Brian Carlstrom7940e442013-07-12 13:46:57 -0700960 RegLocation rl_src) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700961 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
962 RegLocation rl_index, RegLocation rl_dest, int scale) = 0;
963 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
Ian Rogersa9a82542013-10-04 11:17:26 -0700964 RegLocation rl_index, RegLocation rl_src, int scale,
965 bool card_mark) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700966 virtual void GenShiftImmOpLong(Instruction::Code opcode,
967 RegLocation rl_dest, RegLocation rl_src1,
968 RegLocation rl_shift) = 0;
969
970 // Required for target - single operation generators.
971 virtual LIR* OpUnconditionalBranch(LIR* target) = 0;
buzbee0d829482013-10-11 15:24:55 -0700972 virtual LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target) = 0;
973 virtual LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700974 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0;
buzbee0d829482013-10-11 15:24:55 -0700975 virtual LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700976 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0;
977 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0;
978 virtual LIR* OpMem(OpKind op, int rBase, int disp) = 0;
979 virtual LIR* OpPcRelLoad(int reg, LIR* target) = 0;
980 virtual LIR* OpReg(OpKind op, int r_dest_src) = 0;
981 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0;
982 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0;
983 virtual LIR* OpRegImm(OpKind op, int r_dest_src1, int value) = 0;
984 virtual LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset) = 0;
985 virtual LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2) = 0;
Razvan A Lupusorubd288c22013-12-20 17:27:23 -0800986
987 /**
Razvan A Lupusoru2c498d12014-01-29 16:02:57 -0800988 * @brief Used to generate an LIR that does a load from mem to reg.
989 * @param r_dest The destination physical register.
990 * @param r_base The base physical register for memory operand.
991 * @param offset The displacement for memory operand.
992 * @param move_type Specification on the move desired (size, alignment, register kind).
993 * @return Returns the generate move LIR.
994 */
995 virtual LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) = 0;
996
997 /**
998 * @brief Used to generate an LIR that does a store from reg to mem.
999 * @param r_base The base physical register for memory operand.
1000 * @param offset The displacement for memory operand.
1001 * @param r_src The destination physical register.
1002 * @param bytes_to_move The number of bytes to move.
1003 * @param is_aligned Whether the memory location is known to be aligned.
1004 * @return Returns the generate move LIR.
1005 */
1006 virtual LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) = 0;
1007
1008 /**
Razvan A Lupusorubd288c22013-12-20 17:27:23 -08001009 * @brief Used for generating a conditional register to register operation.
1010 * @param op The opcode kind.
1011 * @param cc The condition code that when true will perform the opcode.
1012 * @param r_dest The destination physical register.
1013 * @param r_src The source physical register.
1014 * @return Returns the newly created LIR or null in case of creation failure.
1015 */
1016 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) = 0;
1017
Brian Carlstrom7940e442013-07-12 13:46:57 -07001018 virtual LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) = 0;
buzbee0d829482013-10-11 15:24:55 -07001019 virtual LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001020 virtual LIR* OpTestSuspend(LIR* target) = 0;
Ian Rogers468532e2013-08-05 10:56:33 -07001021 virtual LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001022 virtual LIR* OpVldm(int rBase, int count) = 0;
1023 virtual LIR* OpVstm(int rBase, int count) = 0;
buzbee0d829482013-10-11 15:24:55 -07001024 virtual void OpLea(int rBase, int reg1, int reg2, int scale, int offset) = 0;
1025 virtual void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi) = 0;
Ian Rogers468532e2013-08-05 10:56:33 -07001026 virtual void OpTlsCmp(ThreadOffset offset, int val) = 0;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001027 virtual bool InexpensiveConstantInt(int32_t value) = 0;
1028 virtual bool InexpensiveConstantFloat(int32_t value) = 0;
1029 virtual bool InexpensiveConstantLong(int64_t value) = 0;
1030 virtual bool InexpensiveConstantDouble(int64_t value) = 0;
1031
Ian Rogersd9c4fc92013-10-01 19:45:43 -07001032 // May be optimized by targets.
1033 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src);
1034 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src);
1035
Brian Carlstrom7940e442013-07-12 13:46:57 -07001036 // Temp workaround
1037 void Workaround7250540(RegLocation rl_dest, int value);
1038
1039 protected:
1040 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
1041
1042 CompilationUnit* GetCompilationUnit() {
1043 return cu_;
1044 }
Mark Mendell4708dcd2014-01-22 09:05:18 -08001045 /*
1046 * @brief Returns the index of the lowest set bit in 'x'.
1047 * @param x Value to be examined.
1048 * @returns The bit number of the lowest bit set in the value.
1049 */
1050 int32_t LowestSetBit(uint64_t x);
1051 /*
1052 * @brief Is this value a power of two?
1053 * @param x Value to be examined.
1054 * @returns 'true' if only 1 bit is set in the value.
1055 */
1056 bool IsPowerOfTwo(uint64_t x);
1057 /*
1058 * @brief Do these SRs overlap?
1059 * @param rl_op1 One RegLocation
1060 * @param rl_op2 The other RegLocation
1061 * @return 'true' if the VR pairs overlap
1062 *
1063 * Check to see if a result pair has a misaligned overlap with an operand pair. This
1064 * is not usual for dx to generate, but it is legal (for now). In a future rev of
1065 * dex, we'll want to make this case illegal.
1066 */
1067 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001068
Mark Mendelle02d48f2014-01-15 11:19:23 -08001069 /*
1070 * @brief Force a location (in a register) into a temporary register
1071 * @param loc location of result
1072 * @returns update location
1073 */
1074 RegLocation ForceTemp(RegLocation loc);
1075
1076 /*
1077 * @brief Force a wide location (in registers) into temporary registers
1078 * @param loc location of result
1079 * @returns update location
1080 */
1081 RegLocation ForceTempWide(RegLocation loc);
1082
Mark Mendelldf8ee2e2014-01-27 16:37:47 -08001083 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx,
1084 RegLocation rl_dest, RegLocation rl_src);
1085
Dave Allisonbcec6fb2014-01-17 12:52:22 -08001086 void AddSlowPath(LIRSlowPath* slowpath);
1087
Mark Mendell6607d972014-02-10 06:54:18 -08001088 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final,
1089 bool type_known_abstract, bool use_declaring_class,
1090 bool can_assume_type_is_in_dex_cache,
1091 uint32_t type_idx, RegLocation rl_dest,
1092 RegLocation rl_src);
Mark Mendellae9fd932014-02-10 16:14:35 -08001093 /*
1094 * @brief Generate the debug_frame FDE information if possible.
1095 * @returns pointer to vector containg CFE information, or NULL.
1096 */
1097 virtual std::vector<uint8_t>* ReturnCallFrameInformation();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001098
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -08001099 /**
1100 * @brief Used to insert marker that can be used to associate MIR with LIR.
1101 * @details Only inserts marker if verbosity is enabled.
1102 * @param mir The mir that is currently being generated.
1103 */
1104 void GenPrintLabel(MIR* mir);
1105
1106 /**
1107 * @brief Used to generate return sequence when there is no frame.
1108 * @details Assumes that the return registers have already been populated.
1109 */
1110 virtual void GenSpecialExitSequence() = 0;
1111
1112 /**
1113 * @brief Used to generate code for special methods that are known to be
1114 * small enough to work in frameless mode.
1115 * @param bb The basic block of the first MIR.
1116 * @param mir The first MIR of the special method.
1117 * @param special Information about the special method.
1118 * @return Returns whether or not this was handled successfully. Returns false
1119 * if caller should punt to normal MIR2LIR conversion.
1120 */
1121 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
1122
Mark Mendell6607d972014-02-10 06:54:18 -08001123 private:
Brian Carlstrom7940e442013-07-12 13:46:57 -07001124 void ClobberBody(RegisterInfo* p);
1125 void ResetDefBody(RegisterInfo* p) {
1126 p->def_start = NULL;
1127 p->def_end = NULL;
1128 }
1129
Dave Allisonbcec6fb2014-01-17 12:52:22 -08001130 void SetCurrentDexPc(DexOffset dexpc) {
1131 current_dalvik_offset_ = dexpc;
1132 }
1133
Razvan A Lupusoru3bc01742014-02-06 13:18:43 -08001134 /**
1135 * @brief Used to lock register if argument at in_position was passed that way.
1136 * @details Does nothing if the argument is passed via stack.
1137 * @param in_position The argument number whose register to lock.
1138 * @param wide Whether the argument is wide.
1139 */
1140 void LockArg(int in_position, bool wide = false);
1141
1142 /**
1143 * @brief Used to load VR argument to a physical register.
1144 * @details The load is only done if the argument is not already in physical register.
1145 * LockArg must have been previously called.
1146 * @param in_position The argument number to load.
1147 * @param wide Whether the argument is 64-bit or not.
1148 * @return Returns the register (or register pair) for the loaded argument.
1149 */
1150 int LoadArg(int in_position, bool wide = false);
1151
1152 /**
1153 * @brief Used to load a VR argument directly to a specified register location.
1154 * @param in_position The argument number to place in register.
1155 * @param rl_dest The register location where to place argument.
1156 */
1157 void LoadArgDirect(int in_position, RegLocation rl_dest);
1158
1159 /**
1160 * @brief Used to generate LIR for special getter method.
1161 * @param mir The mir that represents the iget.
1162 * @param special Information about the special getter method.
1163 * @return Returns whether LIR was successfully generated.
1164 */
1165 bool GenSpecialIGet(MIR* mir, const InlineMethod& special);
1166
1167 /**
1168 * @brief Used to generate LIR for special setter method.
1169 * @param mir The mir that represents the iput.
1170 * @param special Information about the special setter method.
1171 * @return Returns whether LIR was successfully generated.
1172 */
1173 bool GenSpecialIPut(MIR* mir, const InlineMethod& special);
1174
1175 /**
1176 * @brief Used to generate LIR for special return-args method.
1177 * @param mir The mir that represents the return of argument.
1178 * @param special Information about the special return-args method.
1179 * @return Returns whether LIR was successfully generated.
1180 */
1181 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special);
1182
Dave Allisonbcec6fb2014-01-17 12:52:22 -08001183
Brian Carlstrom7940e442013-07-12 13:46:57 -07001184 public:
1185 // TODO: add accessors for these.
1186 LIR* literal_list_; // Constants.
1187 LIR* method_literal_list_; // Method literals requiring patching.
Hiroshi Yamauchibe1ca552014-01-15 11:46:48 -08001188 LIR* class_literal_list_; // Class literals requiring patching.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001189 LIR* code_literal_list_; // Code literals requiring patching.
buzbeeb48819d2013-09-14 16:15:25 -07001190 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001191
1192 protected:
1193 CompilationUnit* const cu_;
1194 MIRGraph* const mir_graph_;
1195 GrowableArray<SwitchTable*> switch_tables_;
1196 GrowableArray<FillArrayData*> fill_array_data_;
1197 GrowableArray<LIR*> throw_launchpads_;
1198 GrowableArray<LIR*> suspend_launchpads_;
1199 GrowableArray<LIR*> intrinsic_launchpads_;
buzbeebd663de2013-09-10 15:41:31 -07001200 GrowableArray<RegisterInfo*> tempreg_info_;
1201 GrowableArray<RegisterInfo*> reginfo_map_;
buzbee0d829482013-10-11 15:24:55 -07001202 GrowableArray<void*> pointer_storage_;
buzbee0d829482013-10-11 15:24:55 -07001203 CodeOffset current_code_offset_; // Working byte offset of machine instructons.
1204 CodeOffset data_offset_; // starting offset of literal pool.
1205 size_t total_size_; // header + code size.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001206 LIR* block_label_list_;
1207 PromotionMap* promotion_map_;
1208 /*
1209 * TODO: The code generation utilities don't have a built-in
1210 * mechanism to propagate the original Dalvik opcode address to the
1211 * associated generated instructions. For the trace compiler, this wasn't
1212 * necessary because the interpreter handled all throws and debugging
1213 * requests. For now we'll handle this by placing the Dalvik offset
1214 * in the CompilationUnit struct before codegen for each instruction.
1215 * The low-level LIR creation utilites will pull it from here. Rework this.
1216 */
buzbee0d829482013-10-11 15:24:55 -07001217 DexOffset current_dalvik_offset_;
1218 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001219 RegisterPool* reg_pool_;
1220 /*
1221 * Sanity checking for the register temp tracking. The same ssa
1222 * name should never be associated with one temp register per
1223 * instruction compilation.
1224 */
1225 int live_sreg_;
1226 CodeBuffer code_buffer_;
Ian Rogers96faf5b2013-08-09 22:05:32 -07001227 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix.
Vladimir Marko06606b92013-12-02 15:31:08 +00001228 std::vector<uint8_t> encoded_mapping_table_;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001229 std::vector<uint32_t> core_vmap_table_;
1230 std::vector<uint32_t> fp_vmap_table_;
1231 std::vector<uint8_t> native_gc_map_;
1232 int num_core_spills_;
1233 int num_fp_spills_;
1234 int frame_size_;
1235 unsigned int core_spill_mask_;
1236 unsigned int fp_spill_mask_;
1237 LIR* first_lir_insn_;
1238 LIR* last_lir_insn_;
Dave Allisonbcec6fb2014-01-17 12:52:22 -08001239
1240 GrowableArray<LIRSlowPath*> slow_paths_;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001241}; // Class Mir2Lir
1242
1243} // namespace art
1244
Brian Carlstromfc0e3212013-07-17 14:40:12 -07001245#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_