Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |
| 18 | #define ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |
| 19 | |
| 20 | #include "locations.h" |
| 21 | #include "nodes.h" |
| 22 | #include "utils/arm64/assembler_arm64.h" |
Serban Constantinescu | 82e52ce | 2015-03-26 16:50:57 +0000 | [diff] [blame] | 23 | #include "vixl/a64/disasm-a64.h" |
| 24 | #include "vixl/a64/macro-assembler-a64.h" |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 25 | |
| 26 | namespace art { |
| 27 | namespace arm64 { |
| 28 | namespace helpers { |
| 29 | |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 30 | // Convenience helpers to ease conversion to and from VIXL operands. |
| 31 | static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32), |
| 32 | "Unexpected values for register codes."); |
| 33 | |
| 34 | static inline int VIXLRegCodeFromART(int code) { |
| 35 | if (code == SP) { |
| 36 | return vixl::kSPRegInternalCode; |
| 37 | } |
| 38 | if (code == XZR) { |
| 39 | return vixl::kZeroRegCode; |
| 40 | } |
| 41 | return code; |
| 42 | } |
| 43 | |
| 44 | static inline int ARTRegCodeFromVIXL(int code) { |
| 45 | if (code == vixl::kSPRegInternalCode) { |
| 46 | return SP; |
| 47 | } |
| 48 | if (code == vixl::kZeroRegCode) { |
| 49 | return XZR; |
| 50 | } |
| 51 | return code; |
| 52 | } |
| 53 | |
| 54 | static inline vixl::Register XRegisterFrom(Location location) { |
| 55 | DCHECK(location.IsRegister()); |
| 56 | return vixl::Register::XRegFromCode(VIXLRegCodeFromART(location.reg())); |
| 57 | } |
| 58 | |
| 59 | static inline vixl::Register WRegisterFrom(Location location) { |
| 60 | DCHECK(location.IsRegister()); |
| 61 | return vixl::Register::WRegFromCode(VIXLRegCodeFromART(location.reg())); |
| 62 | } |
| 63 | |
| 64 | static inline vixl::Register RegisterFrom(Location location, Primitive::Type type) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 65 | DCHECK(type != Primitive::kPrimVoid && !Primitive::IsFloatingPointType(type)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 66 | return type == Primitive::kPrimLong ? XRegisterFrom(location) : WRegisterFrom(location); |
| 67 | } |
| 68 | |
| 69 | static inline vixl::Register OutputRegister(HInstruction* instr) { |
| 70 | return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); |
| 71 | } |
| 72 | |
| 73 | static inline vixl::Register InputRegisterAt(HInstruction* instr, int input_index) { |
| 74 | return RegisterFrom(instr->GetLocations()->InAt(input_index), |
| 75 | instr->InputAt(input_index)->GetType()); |
| 76 | } |
| 77 | |
| 78 | static inline vixl::FPRegister DRegisterFrom(Location location) { |
| 79 | DCHECK(location.IsFpuRegister()); |
| 80 | return vixl::FPRegister::DRegFromCode(location.reg()); |
| 81 | } |
| 82 | |
| 83 | static inline vixl::FPRegister SRegisterFrom(Location location) { |
| 84 | DCHECK(location.IsFpuRegister()); |
| 85 | return vixl::FPRegister::SRegFromCode(location.reg()); |
| 86 | } |
| 87 | |
| 88 | static inline vixl::FPRegister FPRegisterFrom(Location location, Primitive::Type type) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 89 | DCHECK(Primitive::IsFloatingPointType(type)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 90 | return type == Primitive::kPrimDouble ? DRegisterFrom(location) : SRegisterFrom(location); |
| 91 | } |
| 92 | |
| 93 | static inline vixl::FPRegister OutputFPRegister(HInstruction* instr) { |
| 94 | return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); |
| 95 | } |
| 96 | |
| 97 | static inline vixl::FPRegister InputFPRegisterAt(HInstruction* instr, int input_index) { |
| 98 | return FPRegisterFrom(instr->GetLocations()->InAt(input_index), |
| 99 | instr->InputAt(input_index)->GetType()); |
| 100 | } |
| 101 | |
| 102 | static inline vixl::CPURegister CPURegisterFrom(Location location, Primitive::Type type) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 103 | return Primitive::IsFloatingPointType(type) ? vixl::CPURegister(FPRegisterFrom(location, type)) |
| 104 | : vixl::CPURegister(RegisterFrom(location, type)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | static inline vixl::CPURegister OutputCPURegister(HInstruction* instr) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 108 | return Primitive::IsFloatingPointType(instr->GetType()) |
| 109 | ? static_cast<vixl::CPURegister>(OutputFPRegister(instr)) |
| 110 | : static_cast<vixl::CPURegister>(OutputRegister(instr)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static inline vixl::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 114 | return Primitive::IsFloatingPointType(instr->InputAt(index)->GetType()) |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 115 | ? static_cast<vixl::CPURegister>(InputFPRegisterAt(instr, index)) |
| 116 | : static_cast<vixl::CPURegister>(InputRegisterAt(instr, index)); |
| 117 | } |
| 118 | |
| 119 | static inline int64_t Int64ConstantFrom(Location location) { |
| 120 | HConstant* instr = location.GetConstant(); |
Nicolas Geoffray | de0eb6f | 2015-03-04 10:28:04 +0000 | [diff] [blame] | 121 | if (instr->IsIntConstant()) { |
| 122 | return instr->AsIntConstant()->GetValue(); |
| 123 | } else if (instr->IsNullConstant()) { |
| 124 | return 0; |
| 125 | } else { |
| 126 | DCHECK(instr->IsLongConstant()); |
| 127 | return instr->AsLongConstant()->GetValue(); |
| 128 | } |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static inline vixl::Operand OperandFrom(Location location, Primitive::Type type) { |
| 132 | if (location.IsRegister()) { |
| 133 | return vixl::Operand(RegisterFrom(location, type)); |
| 134 | } else { |
| 135 | return vixl::Operand(Int64ConstantFrom(location)); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | static inline vixl::Operand InputOperandAt(HInstruction* instr, int input_index) { |
| 140 | return OperandFrom(instr->GetLocations()->InAt(input_index), |
| 141 | instr->InputAt(input_index)->GetType()); |
| 142 | } |
| 143 | |
| 144 | static inline vixl::MemOperand StackOperandFrom(Location location) { |
| 145 | return vixl::MemOperand(vixl::sp, location.GetStackIndex()); |
| 146 | } |
| 147 | |
| 148 | static inline vixl::MemOperand HeapOperand(const vixl::Register& base, size_t offset = 0) { |
| 149 | // A heap reference must be 32bit, so fit in a W register. |
| 150 | DCHECK(base.IsW()); |
| 151 | return vixl::MemOperand(base.X(), offset); |
| 152 | } |
| 153 | |
Alexandre Rames | 82000b0 | 2015-07-07 11:34:16 +0100 | [diff] [blame] | 154 | static inline vixl::MemOperand HeapOperand(const vixl::Register& base, |
| 155 | const vixl::Register& regoffset, |
| 156 | vixl::Shift shift = vixl::LSL, |
| 157 | unsigned shift_amount = 0) { |
| 158 | // A heap reference must be 32bit, so fit in a W register. |
| 159 | DCHECK(base.IsW()); |
| 160 | return vixl::MemOperand(base.X(), regoffset, shift, shift_amount); |
| 161 | } |
| 162 | |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 163 | static inline vixl::MemOperand HeapOperand(const vixl::Register& base, Offset offset) { |
| 164 | return HeapOperand(base, offset.SizeValue()); |
| 165 | } |
| 166 | |
| 167 | static inline vixl::MemOperand HeapOperandFrom(Location location, Offset offset) { |
| 168 | return HeapOperand(RegisterFrom(location, Primitive::kPrimNot), offset); |
| 169 | } |
| 170 | |
| 171 | static inline Location LocationFrom(const vixl::Register& reg) { |
| 172 | return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.code())); |
| 173 | } |
| 174 | |
| 175 | static inline Location LocationFrom(const vixl::FPRegister& fpreg) { |
| 176 | return Location::FpuRegisterLocation(fpreg.code()); |
| 177 | } |
| 178 | |
| 179 | static inline vixl::Operand OperandFromMemOperand(const vixl::MemOperand& mem_op) { |
| 180 | if (mem_op.IsImmediateOffset()) { |
| 181 | return vixl::Operand(mem_op.offset()); |
| 182 | } else { |
| 183 | DCHECK(mem_op.IsRegisterOffset()); |
| 184 | if (mem_op.extend() != vixl::NO_EXTEND) { |
| 185 | return vixl::Operand(mem_op.regoffset(), mem_op.extend(), mem_op.shift_amount()); |
| 186 | } else if (mem_op.shift() != vixl::NO_SHIFT) { |
| 187 | return vixl::Operand(mem_op.regoffset(), mem_op.shift(), mem_op.shift_amount()); |
| 188 | } else { |
| 189 | LOG(FATAL) << "Should not reach here"; |
| 190 | UNREACHABLE(); |
| 191 | } |
| 192 | } |
| 193 | } |
| 194 | |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 195 | static bool CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { |
| 196 | DCHECK(constant->IsIntConstant() || constant->IsLongConstant() || constant->IsNullConstant()); |
| 197 | |
| 198 | // For single uses we let VIXL handle the constant generation since it will |
| 199 | // use registers that are not managed by the register allocator (wip0, wip1). |
| 200 | if (constant->GetUses().HasOnlyOneUse()) { |
| 201 | return true; |
| 202 | } |
| 203 | |
| 204 | int64_t value = CodeGenerator::GetInt64ValueOf(constant); |
| 205 | |
Serban Constantinescu | 760d8ef | 2015-03-28 18:09:56 +0000 | [diff] [blame] | 206 | if (instr->IsAdd() || instr->IsSub() || instr->IsCondition() || |
| 207 | instr->IsCompare() || instr->IsBoundsCheck()) { |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 208 | // Uses aliases of ADD/SUB instructions. |
| 209 | return vixl::Assembler::IsImmAddSub(value); |
| 210 | } else if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) { |
| 211 | // Uses logical operations. |
| 212 | return vixl::Assembler::IsImmLogical(value, vixl::kXRegSize); |
| 213 | } else { |
| 214 | DCHECK(instr->IsNeg()); |
| 215 | // Uses mov -immediate. |
| 216 | return vixl::Assembler::IsImmMovn(value, vixl::kXRegSize); |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | static inline Location ARM64EncodableConstantOrRegister(HInstruction* constant, |
| 221 | HInstruction* instr) { |
| 222 | if (constant->IsConstant() |
| 223 | && CanEncodeConstantAsImmediate(constant->AsConstant(), instr)) { |
| 224 | return Location::ConstantLocation(constant->AsConstant()); |
| 225 | } |
| 226 | |
| 227 | return Location::RequiresRegister(); |
| 228 | } |
| 229 | |
Zheng Xu | da40309 | 2015-04-24 17:35:39 +0800 | [diff] [blame] | 230 | // Check if registers in art register set have the same register code in vixl. If the register |
| 231 | // codes are same, we can initialize vixl register list simply by the register masks. Currently, |
| 232 | // only SP/WSP and ZXR/WZR codes are different between art and vixl. |
| 233 | // Note: This function is only used for debug checks. |
| 234 | static inline bool ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers, |
| 235 | size_t num_core, |
| 236 | uint32_t art_fpu_registers, |
| 237 | size_t num_fpu) { |
| 238 | // The register masks won't work if the number of register is larger than 32. |
| 239 | DCHECK_GE(sizeof(art_core_registers) * 8, num_core); |
| 240 | DCHECK_GE(sizeof(art_fpu_registers) * 8, num_fpu); |
| 241 | for (size_t art_reg_code = 0; art_reg_code < num_core; ++art_reg_code) { |
| 242 | if (RegisterSet::Contains(art_core_registers, art_reg_code)) { |
| 243 | if (art_reg_code != static_cast<size_t>(VIXLRegCodeFromART(art_reg_code))) { |
| 244 | return false; |
| 245 | } |
| 246 | } |
| 247 | } |
| 248 | // There is no register code translation for float registers. |
| 249 | return true; |
| 250 | } |
| 251 | |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 252 | } // namespace helpers |
| 253 | } // namespace arm64 |
| 254 | } // namespace art |
| 255 | |
| 256 | #endif // ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |