Chris Larsen | dbce0d7 | 2015-09-17 13:34:00 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "assembler_mips64.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | #include <map> |
| 21 | #include <random> |
| 22 | |
| 23 | #include "base/bit_utils.h" |
| 24 | #include "base/stl_util.h" |
| 25 | #include "utils/assembler_test.h" |
| 26 | |
| 27 | namespace art { |
| 28 | |
| 29 | struct MIPS64CpuRegisterCompare { |
| 30 | bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const { |
| 31 | return a < b; |
| 32 | } |
| 33 | }; |
| 34 | |
| 35 | class AssemblerMIPS64Test : public AssemblerTest<mips64::Mips64Assembler, |
| 36 | mips64::GpuRegister, |
| 37 | mips64::FpuRegister, |
| 38 | uint32_t> { |
| 39 | public: |
| 40 | typedef AssemblerTest<mips64::Mips64Assembler, |
| 41 | mips64::GpuRegister, |
| 42 | mips64::FpuRegister, |
| 43 | uint32_t> Base; |
| 44 | |
| 45 | protected: |
| 46 | // Get the typically used name for this architecture, e.g., aarch64, x86-64, ... |
| 47 | std::string GetArchitectureString() OVERRIDE { |
| 48 | return "mips64"; |
| 49 | } |
| 50 | |
| 51 | std::string GetAssemblerParameters() OVERRIDE { |
| 52 | return " --no-warn -march=mips64r6"; |
| 53 | } |
| 54 | |
| 55 | std::string GetDisassembleParameters() OVERRIDE { |
| 56 | return " -D -bbinary -mmips:isa64r6"; |
| 57 | } |
| 58 | |
| 59 | void SetUpHelpers() OVERRIDE { |
| 60 | if (registers_.size() == 0) { |
| 61 | registers_.push_back(new mips64::GpuRegister(mips64::ZERO)); |
| 62 | registers_.push_back(new mips64::GpuRegister(mips64::AT)); |
| 63 | registers_.push_back(new mips64::GpuRegister(mips64::V0)); |
| 64 | registers_.push_back(new mips64::GpuRegister(mips64::V1)); |
| 65 | registers_.push_back(new mips64::GpuRegister(mips64::A0)); |
| 66 | registers_.push_back(new mips64::GpuRegister(mips64::A1)); |
| 67 | registers_.push_back(new mips64::GpuRegister(mips64::A2)); |
| 68 | registers_.push_back(new mips64::GpuRegister(mips64::A3)); |
| 69 | registers_.push_back(new mips64::GpuRegister(mips64::A4)); |
| 70 | registers_.push_back(new mips64::GpuRegister(mips64::A5)); |
| 71 | registers_.push_back(new mips64::GpuRegister(mips64::A6)); |
| 72 | registers_.push_back(new mips64::GpuRegister(mips64::A7)); |
| 73 | registers_.push_back(new mips64::GpuRegister(mips64::T0)); |
| 74 | registers_.push_back(new mips64::GpuRegister(mips64::T1)); |
| 75 | registers_.push_back(new mips64::GpuRegister(mips64::T2)); |
| 76 | registers_.push_back(new mips64::GpuRegister(mips64::T3)); |
| 77 | registers_.push_back(new mips64::GpuRegister(mips64::S0)); |
| 78 | registers_.push_back(new mips64::GpuRegister(mips64::S1)); |
| 79 | registers_.push_back(new mips64::GpuRegister(mips64::S2)); |
| 80 | registers_.push_back(new mips64::GpuRegister(mips64::S3)); |
| 81 | registers_.push_back(new mips64::GpuRegister(mips64::S4)); |
| 82 | registers_.push_back(new mips64::GpuRegister(mips64::S5)); |
| 83 | registers_.push_back(new mips64::GpuRegister(mips64::S6)); |
| 84 | registers_.push_back(new mips64::GpuRegister(mips64::S7)); |
| 85 | registers_.push_back(new mips64::GpuRegister(mips64::T8)); |
| 86 | registers_.push_back(new mips64::GpuRegister(mips64::T9)); |
| 87 | registers_.push_back(new mips64::GpuRegister(mips64::K0)); |
| 88 | registers_.push_back(new mips64::GpuRegister(mips64::K1)); |
| 89 | registers_.push_back(new mips64::GpuRegister(mips64::GP)); |
| 90 | registers_.push_back(new mips64::GpuRegister(mips64::SP)); |
| 91 | registers_.push_back(new mips64::GpuRegister(mips64::S8)); |
| 92 | registers_.push_back(new mips64::GpuRegister(mips64::RA)); |
| 93 | |
| 94 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::ZERO), "zero"); |
| 95 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::AT), "at"); |
| 96 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::V0), "v0"); |
| 97 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::V1), "v1"); |
| 98 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A0), "a0"); |
| 99 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A1), "a1"); |
| 100 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A2), "a2"); |
| 101 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A3), "a3"); |
| 102 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A4), "a4"); |
| 103 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A5), "a5"); |
| 104 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A6), "a6"); |
| 105 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::A7), "a7"); |
| 106 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T0), "t0"); |
| 107 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T1), "t1"); |
| 108 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T2), "t2"); |
| 109 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T3), "t3"); |
| 110 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S0), "s0"); |
| 111 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1"); |
| 112 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S2), "s2"); |
| 113 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S3), "s3"); |
| 114 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S4), "s4"); |
| 115 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S5), "s5"); |
| 116 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S6), "s6"); |
| 117 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S7), "s7"); |
| 118 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T8), "t8"); |
| 119 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::T9), "t9"); |
| 120 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::K0), "k0"); |
| 121 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::K1), "k1"); |
| 122 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::GP), "gp"); |
| 123 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::SP), "sp"); |
| 124 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::S8), "s8"); |
| 125 | secondary_register_names_.emplace(mips64::GpuRegister(mips64::RA), "ra"); |
| 126 | |
| 127 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F0)); |
| 128 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F1)); |
| 129 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F2)); |
| 130 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F3)); |
| 131 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F4)); |
| 132 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F5)); |
| 133 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F6)); |
| 134 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F7)); |
| 135 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F8)); |
| 136 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F9)); |
| 137 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F10)); |
| 138 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F11)); |
| 139 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F12)); |
| 140 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F13)); |
| 141 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F14)); |
| 142 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F15)); |
| 143 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F16)); |
| 144 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F17)); |
| 145 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F18)); |
| 146 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F19)); |
| 147 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F20)); |
| 148 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F21)); |
| 149 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F22)); |
| 150 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F23)); |
| 151 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F24)); |
| 152 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F25)); |
| 153 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F26)); |
| 154 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F27)); |
| 155 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F28)); |
| 156 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F29)); |
| 157 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F30)); |
| 158 | fp_registers_.push_back(new mips64::FpuRegister(mips64::F31)); |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | void TearDown() OVERRIDE { |
| 163 | AssemblerTest::TearDown(); |
| 164 | STLDeleteElements(®isters_); |
| 165 | STLDeleteElements(&fp_registers_); |
| 166 | } |
| 167 | |
| 168 | std::vector<mips64::GpuRegister*> GetRegisters() OVERRIDE { |
| 169 | return registers_; |
| 170 | } |
| 171 | |
| 172 | std::vector<mips64::FpuRegister*> GetFPRegisters() OVERRIDE { |
| 173 | return fp_registers_; |
| 174 | } |
| 175 | |
| 176 | uint32_t CreateImmediate(int64_t imm_value) OVERRIDE { |
| 177 | return imm_value; |
| 178 | } |
| 179 | |
| 180 | std::string GetSecondaryRegisterName(const mips64::GpuRegister& reg) OVERRIDE { |
| 181 | CHECK(secondary_register_names_.find(reg) != secondary_register_names_.end()); |
| 182 | return secondary_register_names_[reg]; |
| 183 | } |
| 184 | |
| 185 | private: |
| 186 | std::vector<mips64::GpuRegister*> registers_; |
| 187 | std::map<mips64::GpuRegister, std::string, MIPS64CpuRegisterCompare> secondary_register_names_; |
| 188 | |
| 189 | std::vector<mips64::FpuRegister*> fp_registers_; |
| 190 | }; |
| 191 | |
| 192 | |
| 193 | TEST_F(AssemblerMIPS64Test, Toolchain) { |
| 194 | EXPECT_TRUE(CheckTools()); |
| 195 | } |
| 196 | |
| 197 | |
| 198 | /////////////////// |
| 199 | // FP Operations // |
| 200 | /////////////////// |
| 201 | |
| 202 | TEST_F(AssemblerMIPS64Test, SqrtS) { |
| 203 | DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtS, "sqrt.s ${reg1}, ${reg2}"), "sqrt.s"); |
| 204 | } |
| 205 | |
| 206 | TEST_F(AssemblerMIPS64Test, SqrtD) { |
| 207 | DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtD, "sqrt.d ${reg1}, ${reg2}"), "sqrt.d"); |
| 208 | } |
| 209 | |
| 210 | TEST_F(AssemblerMIPS64Test, AbsS) { |
| 211 | DriverStr(RepeatFF(&mips64::Mips64Assembler::AbsS, "abs.s ${reg1}, ${reg2}"), "abs.s"); |
| 212 | } |
| 213 | |
| 214 | TEST_F(AssemblerMIPS64Test, AbsD) { |
| 215 | DriverStr(RepeatFF(&mips64::Mips64Assembler::AbsD, "abs.d ${reg1}, ${reg2}"), "abs.d"); |
| 216 | } |
| 217 | |
| 218 | TEST_F(AssemblerMIPS64Test, RoundLS) { |
| 219 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundLS, "round.l.s ${reg1}, ${reg2}"), "round.l.s"); |
| 220 | } |
| 221 | |
| 222 | TEST_F(AssemblerMIPS64Test, RoundLD) { |
| 223 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundLD, "round.l.d ${reg1}, ${reg2}"), "round.l.d"); |
| 224 | } |
| 225 | |
| 226 | TEST_F(AssemblerMIPS64Test, RoundWS) { |
| 227 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundWS, "round.w.s ${reg1}, ${reg2}"), "round.w.s"); |
| 228 | } |
| 229 | |
| 230 | TEST_F(AssemblerMIPS64Test, RoundWD) { |
| 231 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundWD, "round.w.d ${reg1}, ${reg2}"), "round.w.d"); |
| 232 | } |
| 233 | |
| 234 | TEST_F(AssemblerMIPS64Test, CeilLS) { |
| 235 | DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilLS, "ceil.l.s ${reg1}, ${reg2}"), "ceil.l.s"); |
| 236 | } |
| 237 | |
| 238 | TEST_F(AssemblerMIPS64Test, CeilLD) { |
| 239 | DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilLD, "ceil.l.d ${reg1}, ${reg2}"), "ceil.l.d"); |
| 240 | } |
| 241 | |
| 242 | TEST_F(AssemblerMIPS64Test, CeilWS) { |
| 243 | DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilWS, "ceil.w.s ${reg1}, ${reg2}"), "ceil.w.s"); |
| 244 | } |
| 245 | |
| 246 | TEST_F(AssemblerMIPS64Test, CeilWD) { |
| 247 | DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilWD, "ceil.w.d ${reg1}, ${reg2}"), "ceil.w.d"); |
| 248 | } |
| 249 | |
| 250 | TEST_F(AssemblerMIPS64Test, FloorLS) { |
| 251 | DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorLS, "floor.l.s ${reg1}, ${reg2}"), "floor.l.s"); |
| 252 | } |
| 253 | |
| 254 | TEST_F(AssemblerMIPS64Test, FloorLD) { |
| 255 | DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorLD, "floor.l.d ${reg1}, ${reg2}"), "floor.l.d"); |
| 256 | } |
| 257 | |
| 258 | TEST_F(AssemblerMIPS64Test, FloorWS) { |
| 259 | DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorWS, "floor.w.s ${reg1}, ${reg2}"), "floor.w.s"); |
| 260 | } |
| 261 | |
| 262 | TEST_F(AssemblerMIPS64Test, FloorWD) { |
| 263 | DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorWD, "floor.w.d ${reg1}, ${reg2}"), "floor.w.d"); |
| 264 | } |
| 265 | |
| 266 | TEST_F(AssemblerMIPS64Test, SelS) { |
| 267 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelS, "sel.s ${reg1}, ${reg2}, ${reg3}"), "sel.s"); |
| 268 | } |
| 269 | |
| 270 | TEST_F(AssemblerMIPS64Test, SelD) { |
| 271 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelD, "sel.d ${reg1}, ${reg2}, ${reg3}"), "sel.d"); |
| 272 | } |
| 273 | |
| 274 | TEST_F(AssemblerMIPS64Test, RintS) { |
| 275 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RintS, "rint.s ${reg1}, ${reg2}"), "rint.s"); |
| 276 | } |
| 277 | |
| 278 | TEST_F(AssemblerMIPS64Test, RintD) { |
| 279 | DriverStr(RepeatFF(&mips64::Mips64Assembler::RintD, "rint.d ${reg1}, ${reg2}"), "rint.d"); |
| 280 | } |
| 281 | |
| 282 | TEST_F(AssemblerMIPS64Test, ClassS) { |
| 283 | DriverStr(RepeatFF(&mips64::Mips64Assembler::ClassS, "class.s ${reg1}, ${reg2}"), "class.s"); |
| 284 | } |
| 285 | |
| 286 | TEST_F(AssemblerMIPS64Test, ClassD) { |
| 287 | DriverStr(RepeatFF(&mips64::Mips64Assembler::ClassD, "class.d ${reg1}, ${reg2}"), "class.d"); |
| 288 | } |
| 289 | |
| 290 | TEST_F(AssemblerMIPS64Test, MinS) { |
| 291 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::MinS, "min.s ${reg1}, ${reg2}, ${reg3}"), "min.s"); |
| 292 | } |
| 293 | |
| 294 | TEST_F(AssemblerMIPS64Test, MinD) { |
| 295 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::MinD, "min.d ${reg1}, ${reg2}, ${reg3}"), "min.d"); |
| 296 | } |
| 297 | |
| 298 | TEST_F(AssemblerMIPS64Test, MaxS) { |
| 299 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::MaxS, "max.s ${reg1}, ${reg2}, ${reg3}"), "max.s"); |
| 300 | } |
| 301 | |
| 302 | TEST_F(AssemblerMIPS64Test, MaxD) { |
| 303 | DriverStr(RepeatFFF(&mips64::Mips64Assembler::MaxD, "max.d ${reg1}, ${reg2}, ${reg3}"), "max.d"); |
| 304 | } |
| 305 | |
| 306 | TEST_F(AssemblerMIPS64Test, CvtDL) { |
| 307 | DriverStr(RepeatFF(&mips64::Mips64Assembler::Cvtdl, "cvt.d.l ${reg1}, ${reg2}"), "cvt.d.l"); |
| 308 | } |
| 309 | |
| 310 | ////////// |
| 311 | // MISC // |
| 312 | ////////// |
| 313 | |
| 314 | TEST_F(AssemblerMIPS64Test, Bitswap) { |
| 315 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Bitswap, "bitswap ${reg1}, ${reg2}"), "bitswap"); |
| 316 | } |
| 317 | |
| 318 | TEST_F(AssemblerMIPS64Test, Dbitswap) { |
| 319 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Dbitswap, "dbitswap ${reg1}, ${reg2}"), "dbitswap"); |
| 320 | } |
| 321 | |
| 322 | TEST_F(AssemblerMIPS64Test, Dsbh) { |
| 323 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Dsbh, "dsbh ${reg1}, ${reg2}"), "dsbh"); |
| 324 | } |
| 325 | |
| 326 | TEST_F(AssemblerMIPS64Test, Dshd) { |
| 327 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Dshd, "dshd ${reg1}, ${reg2}"), "dshd"); |
| 328 | } |
| 329 | |
| 330 | TEST_F(AssemblerMIPS64Test, Wsbh) { |
| 331 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Wsbh, "wsbh ${reg1}, ${reg2}"), "wsbh"); |
| 332 | } |
| 333 | |
| 334 | TEST_F(AssemblerMIPS64Test, Sc) { |
| 335 | DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Sc, -9, "sc ${reg1}, {imm}(${reg2})"), "sc"); |
| 336 | } |
| 337 | |
| 338 | TEST_F(AssemblerMIPS64Test, Scd) { |
| 339 | DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Scd, -9, "scd ${reg1}, {imm}(${reg2})"), "scd"); |
| 340 | } |
| 341 | |
| 342 | TEST_F(AssemblerMIPS64Test, Ll) { |
| 343 | DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Ll, -9, "ll ${reg1}, {imm}(${reg2})"), "ll"); |
| 344 | } |
| 345 | |
| 346 | TEST_F(AssemblerMIPS64Test, Lld) { |
| 347 | DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Lld, -9, "lld ${reg1}, {imm}(${reg2})"), "lld"); |
| 348 | } |
| 349 | |
| 350 | TEST_F(AssemblerMIPS64Test, Rotr) { |
| 351 | DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Rotr, 5, "rotr ${reg1}, ${reg2}, {imm}"), "rotr"); |
| 352 | } |
| 353 | |
| 354 | TEST_F(AssemblerMIPS64Test, Seleqz) { |
| 355 | DriverStr(RepeatRRR(&mips64::Mips64Assembler::Seleqz, "seleqz ${reg1}, ${reg2}, ${reg3}"), |
| 356 | "seleqz"); |
| 357 | } |
| 358 | |
| 359 | TEST_F(AssemblerMIPS64Test, Selnez) { |
| 360 | DriverStr(RepeatRRR(&mips64::Mips64Assembler::Selnez, "selnez ${reg1}, ${reg2}, ${reg3}"), |
| 361 | "selnez"); |
| 362 | } |
| 363 | |
| 364 | TEST_F(AssemblerMIPS64Test, Clz) { |
| 365 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Clz, "clz ${reg1}, ${reg2}"), "clz"); |
| 366 | } |
| 367 | |
| 368 | TEST_F(AssemblerMIPS64Test, Clo) { |
| 369 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Clo, "clo ${reg1}, ${reg2}"), "clo"); |
| 370 | } |
| 371 | |
| 372 | TEST_F(AssemblerMIPS64Test, Dclz) { |
| 373 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Dclz, "dclz ${reg1}, ${reg2}"), "dclz"); |
| 374 | } |
| 375 | |
| 376 | TEST_F(AssemblerMIPS64Test, Dclo) { |
| 377 | DriverStr(RepeatRR(&mips64::Mips64Assembler::Dclo, "dclo ${reg1}, ${reg2}"), "dclo"); |
| 378 | } |
| 379 | |
| 380 | } // namespace art |