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gerrit-public.fairphone.software / platform / art / 581f4e9065b9b7f788315d3ea1a45e51ae168589 / . / compiler / dex / mir_dataflow.cc
blob: b4aec98e0102c7f49f6032571238edd082094dab [file] [log] [blame]
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]17#include "local_value_numbering.h"
Ian Rogers8d3a1172013-06-04 01:13:28 -0700[diff] [blame]18#include "dataflow_iterator-inl.h"
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]19
20namespace art {
21
22/*
23 * Main table containing data flow attributes for each bytecode. The
24 * first kNumPackedOpcodes entries are for Dalvik bytecode
25 * instructions, where extended opcode at the MIR level are appended
26 * afterwards.
27 *
28 * TODO - many optimization flags are incomplete - they will only limit the
29 * scope of optimizations but will not cause mis-optimizations.
30 */
buzbee1da1e2f2013-11-15 13:37:01 -0800[diff] [blame]31const uint64_t MIRGraph::oat_data_flow_attributes_[kMirOpLast] = {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]32 // 00 NOP
33 DF_NOP,
34
35 // 01 MOVE vA, vB
36 DF_DA | DF_UB | DF_IS_MOVE,
37
38 // 02 MOVE_FROM16 vAA, vBBBB
39 DF_DA | DF_UB | DF_IS_MOVE,
40
41 // 03 MOVE_16 vAAAA, vBBBB
42 DF_DA | DF_UB | DF_IS_MOVE,
43
44 // 04 MOVE_WIDE vA, vB
45 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
46
47 // 05 MOVE_WIDE_FROM16 vAA, vBBBB
48 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
49
50 // 06 MOVE_WIDE_16 vAAAA, vBBBB
51 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE,
52
53 // 07 MOVE_OBJECT vA, vB
54 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
55
56 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB
57 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
58
59 // 09 MOVE_OBJECT_16 vAAAA, vBBBB
60 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B,
61
62 // 0A MOVE_RESULT vAA
63 DF_DA,
64
65 // 0B MOVE_RESULT_WIDE vAA
66 DF_DA | DF_A_WIDE,
67
68 // 0C MOVE_RESULT_OBJECT vAA
69 DF_DA | DF_REF_A,
70
71 // 0D MOVE_EXCEPTION vAA
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]72 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]73
74 // 0E RETURN_VOID
75 DF_NOP,
76
77 // 0F RETURN vAA
78 DF_UA,
79
80 // 10 RETURN_WIDE vAA
81 DF_UA | DF_A_WIDE,
82
83 // 11 RETURN_OBJECT vAA
84 DF_UA | DF_REF_A,
85
86 // 12 CONST_4 vA, #+B
87 DF_DA | DF_SETS_CONST,
88
89 // 13 CONST_16 vAA, #+BBBB
90 DF_DA | DF_SETS_CONST,
91
92 // 14 CONST vAA, #+BBBBBBBB
93 DF_DA | DF_SETS_CONST,
94
95 // 15 CONST_HIGH16 VAA, #+BBBB0000
96 DF_DA | DF_SETS_CONST,
97
98 // 16 CONST_WIDE_16 vAA, #+BBBB
99 DF_DA | DF_A_WIDE | DF_SETS_CONST,
100
101 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB
102 DF_DA | DF_A_WIDE | DF_SETS_CONST,
103
104 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB
105 DF_DA | DF_A_WIDE | DF_SETS_CONST,
106
107 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000
108 DF_DA | DF_A_WIDE | DF_SETS_CONST,
109
110 // 1A CONST_STRING vAA, string@BBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]111 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]112
113 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]114 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]115
116 // 1C CONST_CLASS vAA, type@BBBB
Ian Rogersfa7809f2013-06-13 11:15:15 -0700[diff] [blame]117 DF_DA | DF_REF_A | DF_NON_NULL_DST,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]118
119 // 1D MONITOR_ENTER vAA
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]120 DF_UA | DF_NULL_CHK_A | DF_REF_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]121
122 // 1E MONITOR_EXIT vAA
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]123 DF_UA | DF_NULL_CHK_A | DF_REF_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]124
125 // 1F CHK_CAST vAA, type@BBBB
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]126 DF_UA | DF_REF_A | DF_CHK_CAST | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]127
128 // 20 INSTANCE_OF vA, vB, type@CCCC
129 DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS,
130
131 // 21 ARRAY_LENGTH vA, vB
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]132 DF_DA | DF_UB | DF_NULL_CHK_B | DF_CORE_A | DF_REF_B,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]133
134 // 22 NEW_INSTANCE vAA, type@BBBB
135 DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS,
136
137 // 23 NEW_ARRAY vA, vB, type@CCCC
138 DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS,
139
140 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA}
141 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS,
142
143 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB
144 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS,
145
146 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB
147 DF_UA | DF_REF_A | DF_UMS,
148
149 // 27 THROW vAA
150 DF_UA | DF_REF_A | DF_UMS,
151
152 // 28 GOTO
153 DF_NOP,
154
155 // 29 GOTO_16
156 DF_NOP,
157
158 // 2A GOTO_32
159 DF_NOP,
160
161 // 2B PACKED_SWITCH vAA, +BBBBBBBB
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]162 DF_UA | DF_CORE_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]163
164 // 2C SPARSE_SWITCH vAA, +BBBBBBBB
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]165 DF_UA | DF_CORE_A,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]166
167 // 2D CMPL_FLOAT vAA, vBB, vCC
168 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
169
170 // 2E CMPG_FLOAT vAA, vBB, vCC
171 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A,
172
173 // 2F CMPL_DOUBLE vAA, vBB, vCC
174 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
175
176 // 30 CMPG_DOUBLE vAA, vBB, vCC
177 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A,
178
179 // 31 CMP_LONG vAA, vBB, vCC
180 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
181
182 // 32 IF_EQ vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]183 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]184
185 // 33 IF_NE vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]186 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]187
188 // 34 IF_LT vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]189 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]190
191 // 35 IF_GE vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]192 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]193
194 // 36 IF_GT vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]195 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]196
197 // 37 IF_LE vA, vB, +CCCC
Vladimir Markoc91df2d2015-04-23 09:29:21 +0000[diff] [blame]198 DF_UA | DF_UB | DF_SAME_TYPE_AB,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]199
200 // 38 IF_EQZ vAA, +BBBB
201 DF_UA,
202
203 // 39 IF_NEZ vAA, +BBBB
204 DF_UA,
205
206 // 3A IF_LTZ vAA, +BBBB
207 DF_UA,
208
209 // 3B IF_GEZ vAA, +BBBB
210 DF_UA,
211
212 // 3C IF_GTZ vAA, +BBBB
213 DF_UA,
214
215 // 3D IF_LEZ vAA, +BBBB
216 DF_UA,
217
218 // 3E UNUSED_3E
219 DF_NOP,
220
221 // 3F UNUSED_3F
222 DF_NOP,
223
224 // 40 UNUSED_40
225 DF_NOP,
226
227 // 41 UNUSED_41
228 DF_NOP,
229
230 // 42 UNUSED_42
231 DF_NOP,
232
233 // 43 UNUSED_43
234 DF_NOP,
235
236 // 44 AGET vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]237 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]238
239 // 45 AGET_WIDE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]240 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]241
242 // 46 AGET_OBJECT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]243 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_A | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]244
245 // 47 AGET_BOOLEAN vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]246 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]247
248 // 48 AGET_BYTE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]249 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]250
251 // 49 AGET_CHAR vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]252 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]253
254 // 4A AGET_SHORT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]255 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]256
257 // 4B APUT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]258 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]259
260 // 4C APUT_WIDE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]261 DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]262
263 // 4D APUT_OBJECT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]264 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_A | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]265
266 // 4E APUT_BOOLEAN vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]267 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]268
269 // 4F APUT_BYTE vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]270 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]271
272 // 50 APUT_CHAR vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]273 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]274
275 // 51 APUT_SHORT vAA, vBB, vCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]276 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]277
278 // 52 IGET vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]279 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]280
281 // 53 IGET_WIDE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]282 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]283
284 // 54 IGET_OBJECT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]285 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]286
287 // 55 IGET_BOOLEAN vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]288 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]289
290 // 56 IGET_BYTE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]291 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]292
293 // 57 IGET_CHAR vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]294 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]295
296 // 58 IGET_SHORT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]297 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]298
299 // 59 IPUT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]300 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]301
302 // 5A IPUT_WIDE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]303 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]304
305 // 5B IPUT_OBJECT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]306 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]307
308 // 5C IPUT_BOOLEAN vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]309 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]310
311 // 5D IPUT_BYTE vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]312 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]313
314 // 5E IPUT_CHAR vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]315 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]316
317 // 5F IPUT_SHORT vA, vB, field@CCCC
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]318 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]319
320 // 60 SGET vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]321 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]322
323 // 61 SGET_WIDE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]324 DF_DA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]325
326 // 62 SGET_OBJECT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]327 DF_DA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]328
329 // 63 SGET_BOOLEAN vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]330 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]331
332 // 64 SGET_BYTE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]333 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]334
335 // 65 SGET_CHAR vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]336 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]337
338 // 66 SGET_SHORT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]339 DF_DA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]340
341 // 67 SPUT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]342 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]343
344 // 68 SPUT_WIDE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]345 DF_UA | DF_A_WIDE | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]346
347 // 69 SPUT_OBJECT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]348 DF_UA | DF_REF_A | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]349
350 // 6A SPUT_BOOLEAN vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]351 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]352
353 // 6B SPUT_BYTE vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]354 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]355
356 // 6C SPUT_CHAR vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]357 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]358
359 // 6D SPUT_SHORT vAA, field@BBBB
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]360 DF_UA | DF_SFIELD | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]361
362 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA}
363 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
364
365 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA}
366 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
367
368 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA}
369 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
370
371 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA}
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]372 DF_FORMAT_35C | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]373
374 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA}
Sebastien Hertz67ce9b02013-07-11 14:31:18 +0200[diff] [blame]375 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]376
Mathieu Chartierd7cbf8a2015-03-19 12:43:20 -0700[diff] [blame]377 // 73 RETURN_VOID_NO_BARRIER
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]378 DF_NOP,
379
380 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN}
381 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
382
383 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN}
384 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
385
386 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN}
387 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
388
389 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN}
Vladimir Marko66c6d7b2014-10-16 15:41:48 +0100[diff] [blame]390 DF_FORMAT_3RC | DF_CLINIT | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]391
392 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN}
Sebastien Hertz67ce9b02013-07-11 14:31:18 +0200[diff] [blame]393 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]394
395 // 79 UNUSED_79
396 DF_NOP,
397
398 // 7A UNUSED_7A
399 DF_NOP,
400
401 // 7B NEG_INT vA, vB
402 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
403
404 // 7C NOT_INT vA, vB
405 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
406
407 // 7D NEG_LONG vA, vB
408 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
409
410 // 7E NOT_LONG vA, vB
411 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
412
413 // 7F NEG_FLOAT vA, vB
414 DF_DA | DF_UB | DF_FP_A | DF_FP_B,
415
416 // 80 NEG_DOUBLE vA, vB
417 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
418
419 // 81 INT_TO_LONG vA, vB
420 DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B,
421
422 // 82 INT_TO_FLOAT vA, vB
423 DF_DA | DF_UB | DF_FP_A | DF_CORE_B,
424
425 // 83 INT_TO_DOUBLE vA, vB
426 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B,
427
428 // 84 LONG_TO_INT vA, vB
429 DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
430
431 // 85 LONG_TO_FLOAT vA, vB
432 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
433
434 // 86 LONG_TO_DOUBLE vA, vB
435 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B,
436
437 // 87 FLOAT_TO_INT vA, vB
438 DF_DA | DF_UB | DF_FP_B | DF_CORE_A,
439
440 // 88 FLOAT_TO_LONG vA, vB
441 DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A,
442
443 // 89 FLOAT_TO_DOUBLE vA, vB
444 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B,
445
446 // 8A DOUBLE_TO_INT vA, vB
447 DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
448
449 // 8B DOUBLE_TO_LONG vA, vB
450 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A,
451
452 // 8C DOUBLE_TO_FLOAT vA, vB
453 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
454
455 // 8D INT_TO_BYTE vA, vB
456 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
457
458 // 8E INT_TO_CHAR vA, vB
459 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
460
461 // 8F INT_TO_SHORT vA, vB
462 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
463
464 // 90 ADD_INT vAA, vBB, vCC
465 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
466
467 // 91 SUB_INT vAA, vBB, vCC
468 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
469
470 // 92 MUL_INT vAA, vBB, vCC
471 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
472
473 // 93 DIV_INT vAA, vBB, vCC
474 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
475
476 // 94 REM_INT vAA, vBB, vCC
477 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
478
479 // 95 AND_INT vAA, vBB, vCC
480 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
481
482 // 96 OR_INT vAA, vBB, vCC
483 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
484
485 // 97 XOR_INT vAA, vBB, vCC
486 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
487
488 // 98 SHL_INT vAA, vBB, vCC
489 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
490
491 // 99 SHR_INT vAA, vBB, vCC
492 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
493
494 // 9A USHR_INT vAA, vBB, vCC
495 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
496
497 // 9B ADD_LONG vAA, vBB, vCC
498 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
499
500 // 9C SUB_LONG vAA, vBB, vCC
501 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
502
503 // 9D MUL_LONG vAA, vBB, vCC
504 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
505
506 // 9E DIV_LONG vAA, vBB, vCC
507 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
508
509 // 9F REM_LONG vAA, vBB, vCC
510 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
511
512 // A0 AND_LONG vAA, vBB, vCC
513 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
514
515 // A1 OR_LONG vAA, vBB, vCC
516 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
517
518 // A2 XOR_LONG vAA, vBB, vCC
519 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C,
520
521 // A3 SHL_LONG vAA, vBB, vCC
522 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
523
524 // A4 SHR_LONG vAA, vBB, vCC
525 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
526
527 // A5 USHR_LONG vAA, vBB, vCC
528 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C,
529
530 // A6 ADD_FLOAT vAA, vBB, vCC
531 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
532
533 // A7 SUB_FLOAT vAA, vBB, vCC
534 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
535
536 // A8 MUL_FLOAT vAA, vBB, vCC
537 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
538
539 // A9 DIV_FLOAT vAA, vBB, vCC
540 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
541
542 // AA REM_FLOAT vAA, vBB, vCC
543 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C,
544
545 // AB ADD_DOUBLE vAA, vBB, vCC
546 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
547
548 // AC SUB_DOUBLE vAA, vBB, vCC
549 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
550
551 // AD MUL_DOUBLE vAA, vBB, vCC
552 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
553
554 // AE DIV_DOUBLE vAA, vBB, vCC
555 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
556
557 // AF REM_DOUBLE vAA, vBB, vCC
558 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C,
559
560 // B0 ADD_INT_2ADDR vA, vB
561 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
562
563 // B1 SUB_INT_2ADDR vA, vB
564 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
565
566 // B2 MUL_INT_2ADDR vA, vB
567 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
568
569 // B3 DIV_INT_2ADDR vA, vB
570 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
571
572 // B4 REM_INT_2ADDR vA, vB
573 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
574
575 // B5 AND_INT_2ADDR vA, vB
576 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
577
578 // B6 OR_INT_2ADDR vA, vB
579 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
580
581 // B7 XOR_INT_2ADDR vA, vB
582 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
583
584 // B8 SHL_INT_2ADDR vA, vB
585 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
586
587 // B9 SHR_INT_2ADDR vA, vB
588 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
589
590 // BA USHR_INT_2ADDR vA, vB
591 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
592
593 // BB ADD_LONG_2ADDR vA, vB
594 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
595
596 // BC SUB_LONG_2ADDR vA, vB
597 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
598
599 // BD MUL_LONG_2ADDR vA, vB
600 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
601
602 // BE DIV_LONG_2ADDR vA, vB
603 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
604
605 // BF REM_LONG_2ADDR vA, vB
606 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
607
608 // C0 AND_LONG_2ADDR vA, vB
609 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
610
611 // C1 OR_LONG_2ADDR vA, vB
612 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
613
614 // C2 XOR_LONG_2ADDR vA, vB
615 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
616
617 // C3 SHL_LONG_2ADDR vA, vB
618 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
619
620 // C4 SHR_LONG_2ADDR vA, vB
621 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
622
623 // C5 USHR_LONG_2ADDR vA, vB
624 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B,
625
626 // C6 ADD_FLOAT_2ADDR vA, vB
627 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
628
629 // C7 SUB_FLOAT_2ADDR vA, vB
630 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
631
632 // C8 MUL_FLOAT_2ADDR vA, vB
633 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
634
635 // C9 DIV_FLOAT_2ADDR vA, vB
636 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
637
638 // CA REM_FLOAT_2ADDR vA, vB
639 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B,
640
641 // CB ADD_DOUBLE_2ADDR vA, vB
642 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
643
644 // CC SUB_DOUBLE_2ADDR vA, vB
645 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
646
647 // CD MUL_DOUBLE_2ADDR vA, vB
648 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
649
650 // CE DIV_DOUBLE_2ADDR vA, vB
651 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
652
653 // CF REM_DOUBLE_2ADDR vA, vB
654 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
655
656 // D0 ADD_INT_LIT16 vA, vB, #+CCCC
657 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
658
659 // D1 RSUB_INT vA, vB, #+CCCC
660 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
661
662 // D2 MUL_INT_LIT16 vA, vB, #+CCCC
663 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
664
665 // D3 DIV_INT_LIT16 vA, vB, #+CCCC
666 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
667
668 // D4 REM_INT_LIT16 vA, vB, #+CCCC
669 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
670
671 // D5 AND_INT_LIT16 vA, vB, #+CCCC
672 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
673
674 // D6 OR_INT_LIT16 vA, vB, #+CCCC
675 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
676
677 // D7 XOR_INT_LIT16 vA, vB, #+CCCC
678 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
679
680 // D8 ADD_INT_LIT8 vAA, vBB, #+CC
681 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
682
683 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC
684 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
685
686 // DA MUL_INT_LIT8 vAA, vBB, #+CC
687 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
688
689 // DB DIV_INT_LIT8 vAA, vBB, #+CC
690 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
691
692 // DC REM_INT_LIT8 vAA, vBB, #+CC
693 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
694
695 // DD AND_INT_LIT8 vAA, vBB, #+CC
696 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
697
698 // DE OR_INT_LIT8 vAA, vBB, #+CC
699 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
700
701 // DF XOR_INT_LIT8 vAA, vBB, #+CC
702 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
703
704 // E0 SHL_INT_LIT8 vAA, vBB, #+CC
705 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
706
707 // E1 SHR_INT_LIT8 vAA, vBB, #+CC
708 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
709
710 // E2 USHR_INT_LIT8 vAA, vBB, #+CC
711 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B,
712
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]713 // E3 IGET_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]714 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]715
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]716 // E4 IGET_WIDE_QUICK
Nicolas Geoffraya5ca8882015-02-24 08:10:57 +0000[diff] [blame]717 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
Mathieu Chartier2535abe2015-02-17 10:38:49 -0800[diff] [blame]718
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]719 // E5 IGET_OBJECT_QUICK
720 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
721
722 // E6 IPUT_QUICK
723 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
724
725 // E7 IPUT_WIDE_QUICK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]726 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]727
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]728 // E8 IPUT_OBJECT_QUICK
Nicolas Geoffraya5ca8882015-02-24 08:10:57 +0000[diff] [blame]729 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_A | DF_REF_B | DF_IFIELD | DF_LVN,
Mathieu Chartier2535abe2015-02-17 10:38:49 -0800[diff] [blame]730
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]731 // E9 INVOKE_VIRTUAL_QUICK
732 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS,
Mathieu Chartier2535abe2015-02-17 10:38:49 -0800[diff] [blame]733
Mathieu Chartiere5f13e52015-02-24 09:37:21 -0800[diff] [blame]734 // EA INVOKE_VIRTUAL_RANGE_QUICK
735 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS,
736
737 // EB IPUT_BOOLEAN_QUICK vA, vB, index
738 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
739
740 // EC IPUT_BYTE_QUICK vA, vB, index
741 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
742
743 // ED IPUT_CHAR_QUICK vA, vB, index
744 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
745
746 // EE IPUT_SHORT_QUICK vA, vB, index
747 DF_UA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
748
749 // EF IGET_BOOLEAN_QUICK vA, vB, index
750 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
751
752 // F0 IGET_BYTE_QUICK vA, vB, index
753 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
754
755 // F1 IGET_CHAR_QUICK vA, vB, index
756 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
757
758 // F2 IGET_SHORT_QUICK vA, vB, index
759 DF_DA | DF_UB | DF_NULL_CHK_B | DF_REF_B | DF_IFIELD | DF_LVN,
760
761 // F3 UNUSED_F3
762 DF_NOP,
763
764 // F4 UNUSED_F4
765 DF_NOP,
766
767 // F5 UNUSED_F5
768 DF_NOP,
769
770 // F6 UNUSED_F6
771 DF_NOP,
772
773 // F7 UNUSED_F7
774 DF_NOP,
775
776 // F8 UNUSED_F8
777 DF_NOP,
778
779 // F9 UNUSED_F9
780 DF_NOP,
781
782 // FA UNUSED_FA
783 DF_NOP,
784
785 // FB UNUSED_FB
786 DF_NOP,
787
788 // FC UNUSED_FC
789 DF_NOP,
790
791 // FD UNUSED_FD
792 DF_NOP,
793
794 // FE UNUSED_FE
795 DF_NOP,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]796
797 // FF UNUSED_FF
798 DF_NOP,
799
800 // Beginning of extended MIR opcodes
801 // 100 MIR_PHI
802 DF_DA | DF_NULL_TRANSFER_N,
803
804 // 101 MIR_COPY
805 DF_DA | DF_UB | DF_IS_MOVE,
806
807 // 102 MIR_FUSED_CMPL_FLOAT
808 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
809
810 // 103 MIR_FUSED_CMPG_FLOAT
811 DF_UA | DF_UB | DF_FP_A | DF_FP_B,
812
813 // 104 MIR_FUSED_CMPL_DOUBLE
814 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
815
816 // 105 MIR_FUSED_CMPG_DOUBLE
817 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B,
818
819 // 106 MIR_FUSED_CMP_LONG
820 DF_UA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B,
821
822 // 107 MIR_NOP
823 DF_NOP,
824
825 // 108 MIR_NULL_CHECK
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]826 DF_UA | DF_REF_A | DF_NULL_CHK_A | DF_LVN,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]827
828 // 109 MIR_RANGE_CHECK
829 0,
830
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]831 // 10A MIR_DIV_ZERO_CHECK
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]832 0,
833
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]834 // 10B MIR_CHECK
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]835 0,
836
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]837 // 10C MIR_CHECKPART2
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]838 0,
839
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]840 // 10D MIR_SELECT
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]841 DF_DA | DF_UB,
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]842
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]843 // 10E MirOpConstVector
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]844 0,
845
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]846 // 10F MirOpMoveVector
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]847 0,
848
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]849 // 110 MirOpPackedMultiply
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]850 0,
851
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]852 // 111 MirOpPackedAddition
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]853 0,
854
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]855 // 112 MirOpPackedSubtract
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]856 0,
857
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]858 // 113 MirOpPackedShiftLeft
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]859 0,
860
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]861 // 114 MirOpPackedSignedShiftRight
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]862 0,
863
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]864 // 115 MirOpPackedUnsignedShiftRight
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]865 0,
866
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]867 // 116 MirOpPackedAnd
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]868 0,
869
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]870 // 117 MirOpPackedOr
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]871 0,
872
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]873 // 118 MirOpPackedXor
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]874 0,
875
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]876 // 119 MirOpPackedAddReduce
877 DF_FORMAT_EXTENDED,
878
879 // 11A MirOpPackedReduce
880 DF_FORMAT_EXTENDED,
881
882 // 11B MirOpPackedSet
883 DF_FORMAT_EXTENDED,
884
885 // 11C MirOpReserveVectorRegisters
Udayan Banerji60bfe7b2014-07-08 19:59:43 -0700[diff] [blame]886 0,
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700[diff] [blame]887
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]888 // 11D MirOpReturnVectorRegisters
Jean Christophe Beylerb5bce7c2014-07-25 12:32:18 -0700[diff] [blame]889 0,
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]890
891 // 11E MirOpMemBarrier
892 0,
893
894 // 11F MirOpPackedArrayGet
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]895 DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]896
897 // 120 MirOpPackedArrayPut
Vladimir Marko7baa6f82014-10-09 18:01:24 +0100[diff] [blame]898 DF_UB | DF_UC | DF_NULL_CHK_B | DF_RANGE_CHK_C | DF_REF_B | DF_CORE_C | DF_LVN,
Ningsheng Jiana262f772014-11-25 16:48:07 +0800[diff] [blame]899
900 // 121 MirOpMaddInt
901 DF_FORMAT_EXTENDED,
902
903 // 122 MirOpMsubInt
904 DF_FORMAT_EXTENDED,
905
906 // 123 MirOpMaddLong
907 DF_FORMAT_EXTENDED,
908
909 // 124 MirOpMsubLong
910 DF_FORMAT_EXTENDED,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]911};
912
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]913/* Any register that is used before being defined is considered live-in */
914void MIRGraph::HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
Ningsheng Jiana262f772014-11-25 16:48:07 +0800[diff] [blame]915 ArenaBitVector* live_in_v, int dalvik_reg_id) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]916 use_v->SetBit(dalvik_reg_id);
917 if (!def_v->IsBitSet(dalvik_reg_id)) {
918 live_in_v->SetBit(dalvik_reg_id);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]919 }
920}
921
922/* Mark a reg as being defined */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]923void MIRGraph::HandleDef(ArenaBitVector* def_v, int dalvik_reg_id) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]924 def_v->SetBit(dalvik_reg_id);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]925}
926
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]927void MIRGraph::HandleExtended(ArenaBitVector* use_v, ArenaBitVector* def_v,
Ningsheng Jiana262f772014-11-25 16:48:07 +0800[diff] [blame]928 ArenaBitVector* live_in_v,
929 const MIR::DecodedInstruction& d_insn) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]930 // For vector MIRs, vC contains type information
931 bool is_vector_type_wide = false;
932 int type_size = d_insn.vC >> 16;
933 if (type_size == k64 || type_size == kDouble) {
934 is_vector_type_wide = true;
935 }
936
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]937 switch (static_cast<int>(d_insn.opcode)) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]938 case kMirOpPackedAddReduce:
939 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vA);
940 if (is_vector_type_wide == true) {
941 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vA + 1);
942 }
943 HandleDef(def_v, d_insn.vA);
944 if (is_vector_type_wide == true) {
945 HandleDef(def_v, d_insn.vA + 1);
946 }
947 break;
948 case kMirOpPackedReduce:
949 HandleDef(def_v, d_insn.vA);
950 if (is_vector_type_wide == true) {
951 HandleDef(def_v, d_insn.vA + 1);
952 }
953 break;
954 case kMirOpPackedSet:
955 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB);
956 if (is_vector_type_wide == true) {
957 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB + 1);
958 }
959 break;
Ningsheng Jiana262f772014-11-25 16:48:07 +0800[diff] [blame]960 case kMirOpMaddInt:
961 case kMirOpMsubInt:
962 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB);
963 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC);
964 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.arg[0]);
965 HandleDef(def_v, d_insn.vA);
966 break;
967 case kMirOpMaddLong:
968 case kMirOpMsubLong:
969 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB);
970 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vB + 1);
971 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC);
972 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC + 1);
973 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.arg[0]);
974 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.arg[0] + 1);
975 HandleDef(def_v, d_insn.vA);
976 HandleDef(def_v, d_insn.vA + 1);
977 break;
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]978 default:
979 LOG(ERROR) << "Unexpected Extended Opcode " << d_insn.opcode;
980 break;
981 }
982}
983
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]984/*
985 * Find out live-in variables for natural loops. Variables that are live-in in
986 * the main loop body are considered to be defined in the entry block.
987 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]988bool MIRGraph::FindLocalLiveIn(BasicBlock* bb) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]989 MIR* mir;
990 ArenaBitVector *use_v, *def_v, *live_in_v;
991
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]992 if (bb->data_flow_info == nullptr) return false;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]993
994 use_v = bb->data_flow_info->use_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]995 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapUse);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]996 def_v = bb->data_flow_info->def_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]997 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapDef);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]998 live_in_v = bb->data_flow_info->live_in_v =
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]999 new (arena_) ArenaBitVector(arena_, GetNumOfCodeAndTempVRs(), false, kBitMapLiveIn);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1000
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]1001 for (mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) {
Jean Christophe Beylercc794c32014-05-02 09:34:13 -0700[diff] [blame]1002 uint64_t df_attributes = GetDataFlowAttributes(mir);
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1003 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1004
1005 if (df_attributes & DF_HAS_USES) {
1006 if (df_attributes & DF_UA) {
1007 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA);
1008 if (df_attributes & DF_A_WIDE) {
1009 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vA+1);
1010 }
1011 }
1012 if (df_attributes & DF_UB) {
1013 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB);
1014 if (df_attributes & DF_B_WIDE) {
1015 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vB+1);
1016 }
1017 }
1018 if (df_attributes & DF_UC) {
1019 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC);
1020 if (df_attributes & DF_C_WIDE) {
1021 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+1);
1022 }
1023 }
1024 }
1025 if (df_attributes & DF_FORMAT_35C) {
1026 for (unsigned int i = 0; i < d_insn->vA; i++) {
1027 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->arg[i]);
1028 }
1029 }
1030 if (df_attributes & DF_FORMAT_3RC) {
1031 for (unsigned int i = 0; i < d_insn->vA; i++) {
1032 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+i);
1033 }
1034 }
1035 if (df_attributes & DF_HAS_DEFS) {
1036 HandleDef(def_v, d_insn->vA);
1037 if (df_attributes & DF_A_WIDE) {
1038 HandleDef(def_v, d_insn->vA+1);
1039 }
1040 }
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1041 if (df_attributes & DF_FORMAT_EXTENDED) {
1042 HandleExtended(use_v, def_v, live_in_v, mir->dalvikInsn);
1043 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1044 }
1045 return true;
1046}
1047
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1048int MIRGraph::AddNewSReg(int v_reg) {
Vladimir Marko1c6ea442014-12-19 18:11:35 +0000[diff] [blame]1049 int subscript = ++ssa_last_defs_[v_reg];
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1050 uint32_t ssa_reg = GetNumSSARegs();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1051 SetNumSSARegs(ssa_reg + 1);
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1052 ssa_base_vregs_.push_back(v_reg);
1053 ssa_subscripts_.push_back(subscript);
1054 DCHECK_EQ(ssa_base_vregs_.size(), ssa_subscripts_.size());
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1055 // If we are expanding very late, update use counts too.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1056 if (ssa_reg > 0 && use_counts_.size() == ssa_reg) {
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1057 // Need to expand the counts.
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1058 use_counts_.push_back(0);
1059 raw_use_counts_.push_back(0);
Mark Mendell0add77a2014-05-05 22:28:55 -0400[diff] [blame]1060 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1061 return ssa_reg;
1062}
1063
1064/* Find out the latest SSA register for a given Dalvik register */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1065void MIRGraph::HandleSSAUse(int* uses, int dalvik_reg, int reg_index) {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1066 DCHECK((dalvik_reg >= 0) && (dalvik_reg < static_cast<int>(GetNumOfCodeAndTempVRs())));
Vladimir Marko1c6ea442014-12-19 18:11:35 +0000[diff] [blame]1067 uses[reg_index] = vreg_to_ssa_map_[dalvik_reg];
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1068}
1069
1070/* Setup a new SSA register for a given Dalvik register */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1071void MIRGraph::HandleSSADef(int* defs, int dalvik_reg, int reg_index) {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1072 DCHECK((dalvik_reg >= 0) && (dalvik_reg < static_cast<int>(GetNumOfCodeAndTempVRs())));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1073 int ssa_reg = AddNewSReg(dalvik_reg);
Vladimir Marko1c6ea442014-12-19 18:11:35 +0000[diff] [blame]1074 vreg_to_ssa_map_[dalvik_reg] = ssa_reg;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1075 defs[reg_index] = ssa_reg;
1076}
1077
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1078void MIRGraph::AllocateSSAUseData(MIR *mir, int num_uses) {
1079 mir->ssa_rep->num_uses = num_uses;
1080
1081 if (mir->ssa_rep->num_uses_allocated < num_uses) {
Vladimir Markoe4fcc5b2015-02-13 10:28:29 +0000[diff] [blame]1082 mir->ssa_rep->uses = arena_->AllocArray<int32_t>(num_uses, kArenaAllocDFInfo);
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1083 }
1084}
1085
1086void MIRGraph::AllocateSSADefData(MIR *mir, int num_defs) {
1087 mir->ssa_rep->num_defs = num_defs;
1088
1089 if (mir->ssa_rep->num_defs_allocated < num_defs) {
Vladimir Markoe4fcc5b2015-02-13 10:28:29 +0000[diff] [blame]1090 mir->ssa_rep->defs = arena_->AllocArray<int32_t>(num_defs, kArenaAllocDFInfo);
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1091 }
1092}
1093
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1094/* Look up new SSA names for format_35c instructions */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1095void MIRGraph::DataFlowSSAFormat35C(MIR* mir) {
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1096 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1097 int num_uses = d_insn->vA;
1098 int i;
1099
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1100 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1101
1102 for (i = 0; i < num_uses; i++) {
1103 HandleSSAUse(mir->ssa_rep->uses, d_insn->arg[i], i);
1104 }
1105}
1106
1107/* Look up new SSA names for format_3rc instructions */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1108void MIRGraph::DataFlowSSAFormat3RC(MIR* mir) {
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1109 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1110 int num_uses = d_insn->vA;
1111 int i;
1112
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1113 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1114
1115 for (i = 0; i < num_uses; i++) {
1116 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+i, i);
1117 }
1118}
1119
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1120void MIRGraph::DataFlowSSAFormatExtended(MIR* mir) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]1121 const MIR::DecodedInstruction& d_insn = mir->dalvikInsn;
1122 // For vector MIRs, vC contains type information
1123 bool is_vector_type_wide = false;
1124 int type_size = d_insn.vC >> 16;
1125 if (type_size == k64 || type_size == kDouble) {
1126 is_vector_type_wide = true;
1127 }
1128
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1129 switch (static_cast<int>(mir->dalvikInsn.opcode)) {
Lupusoru, Razvan Ab3a84e22014-07-28 14:11:01 -0700[diff] [blame]1130 case kMirOpPackedAddReduce:
1131 // We have one use, plus one more for wide
1132 AllocateSSAUseData(mir, is_vector_type_wide ? 2 : 1);
1133 HandleSSAUse(mir->ssa_rep->uses, d_insn.vA, 0);
1134 if (is_vector_type_wide == true) {
1135 HandleSSAUse(mir->ssa_rep->uses, d_insn.vA + 1, 1);
1136 }
1137
1138 // We have a def, plus one more for wide
1139 AllocateSSADefData(mir, is_vector_type_wide ? 2 : 1);
1140 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1141 if (is_vector_type_wide == true) {
1142 HandleSSADef(mir->ssa_rep->defs, d_insn.vA + 1, 1);
1143 }
1144 break;
1145 case kMirOpPackedReduce:
1146 // We have a def, plus one more for wide
1147 AllocateSSADefData(mir, is_vector_type_wide ? 2 : 1);
1148 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1149 if (is_vector_type_wide == true) {
1150 HandleSSADef(mir->ssa_rep->defs, d_insn.vA + 1, 1);
1151 }
1152 break;
1153 case kMirOpPackedSet:
1154 // We have one use, plus one more for wide
1155 AllocateSSAUseData(mir, is_vector_type_wide ? 2 : 1);
1156 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB, 0);
1157 if (is_vector_type_wide == true) {
1158 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB + 1, 1);
1159 }
1160 break;
Ningsheng Jiana262f772014-11-25 16:48:07 +0800[diff] [blame]1161 case kMirOpMaddInt:
1162 case kMirOpMsubInt:
1163 AllocateSSAUseData(mir, 3);
1164 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB, 0);
1165 HandleSSAUse(mir->ssa_rep->uses, d_insn.vC, 1);
1166 HandleSSAUse(mir->ssa_rep->uses, d_insn.arg[0], 2);
1167 AllocateSSADefData(mir, 1);
1168 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1169 break;
1170 case kMirOpMaddLong:
1171 case kMirOpMsubLong:
1172 AllocateSSAUseData(mir, 6);
1173 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB, 0);
1174 HandleSSAUse(mir->ssa_rep->uses, d_insn.vB + 1, 1);
1175 HandleSSAUse(mir->ssa_rep->uses, d_insn.vC, 2);
1176 HandleSSAUse(mir->ssa_rep->uses, d_insn.vC + 1, 3);
1177 HandleSSAUse(mir->ssa_rep->uses, d_insn.arg[0], 4);
1178 HandleSSAUse(mir->ssa_rep->uses, d_insn.arg[0] + 1, 5);
1179 AllocateSSADefData(mir, 2);
1180 HandleSSADef(mir->ssa_rep->defs, d_insn.vA, 0);
1181 HandleSSADef(mir->ssa_rep->defs, d_insn.vA + 1, 1);
1182 break;
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1183 default:
1184 LOG(ERROR) << "Missing case for extended MIR: " << mir->dalvikInsn.opcode;
1185 break;
1186 }
1187}
1188
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1189/* Entry function to convert a block into SSA representation */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1190bool MIRGraph::DoSSAConversion(BasicBlock* bb) {
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]1191 if (bb->data_flow_info == nullptr) return false;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1192
Vladimir Marko6a8946b2015-02-09 12:35:05 +0000[diff] [blame]1193 /*
1194 * Pruned SSA form: Insert phi nodes for each dalvik register marked in phi_node_blocks
1195 * only if the dalvik register is in the live-in set.
1196 */
1197 BasicBlockId bb_id = bb->id;
1198 for (int dalvik_reg = GetNumOfCodeAndTempVRs() - 1; dalvik_reg >= 0; dalvik_reg--) {
1199 if (temp_.ssa.phi_node_blocks[dalvik_reg]->IsBitSet(bb_id)) {
1200 if (!bb->data_flow_info->live_in_v->IsBitSet(dalvik_reg)) {
1201 /* Variable will be clobbered before being used - no need for phi */
1202 vreg_to_ssa_map_[dalvik_reg] = INVALID_SREG;
1203 continue;
1204 }
1205 MIR *phi = NewMIR();
1206 phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpPhi);
1207 phi->dalvikInsn.vA = dalvik_reg;
1208 phi->offset = bb->start_offset;
1209 phi->m_unit_index = 0; // Arbitrarily assign all Phi nodes to outermost method.
1210 bb->PrependMIR(phi);
1211 }
1212 }
1213
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]1214 for (MIR* mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) {
buzbee862a7602013-04-05 10:58:54 -0700[diff] [blame]1215 mir->ssa_rep =
Mathieu Chartierf6c4b3b2013-08-24 16:11:37 -0700[diff] [blame]1216 static_cast<struct SSARepresentation *>(arena_->Alloc(sizeof(SSARepresentation),
Vladimir Marko83cc7ae2014-02-12 18:02:05 +0000[diff] [blame]1217 kArenaAllocDFInfo));
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1218 memset(mir->ssa_rep, 0, sizeof(*mir->ssa_rep));
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1219
Jean Christophe Beylercc794c32014-05-02 09:34:13 -0700[diff] [blame]1220 uint64_t df_attributes = GetDataFlowAttributes(mir);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1221
1222 // If not a pseudo-op, note non-leaf or can throw
Jean Christophe Beyler2ab40eb2014-06-02 09:03:14 -0700[diff] [blame]1223 if (!MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) {
Jean Christophe Beylerfb0ea2d2014-07-29 13:20:42 -0700[diff] [blame]1224 int flags = mir->dalvikInsn.FlagsOf();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1225
Vladimir Markoff0ac472014-10-02 17:24:53 +0100[diff] [blame]1226 if ((flags & Instruction::kInvoke) != 0) {
buzbee1fd33462013-03-25 13:40:45 -0700[diff] [blame]1227 attributes_ &= ~METHOD_IS_LEAF;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1228 }
1229 }
1230
1231 int num_uses = 0;
1232
1233 if (df_attributes & DF_FORMAT_35C) {
1234 DataFlowSSAFormat35C(mir);
1235 continue;
1236 }
1237
1238 if (df_attributes & DF_FORMAT_3RC) {
1239 DataFlowSSAFormat3RC(mir);
1240 continue;
1241 }
1242
Udayan Banerjif2466a72014-07-09 19:14:53 -0700[diff] [blame]1243 if (df_attributes & DF_FORMAT_EXTENDED) {
1244 DataFlowSSAFormatExtended(mir);
1245 continue;
1246 }
1247
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1248 if (df_attributes & DF_HAS_USES) {
1249 if (df_attributes & DF_UA) {
1250 num_uses++;
1251 if (df_attributes & DF_A_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1252 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1253 }
1254 }
1255 if (df_attributes & DF_UB) {
1256 num_uses++;
1257 if (df_attributes & DF_B_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1258 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1259 }
1260 }
1261 if (df_attributes & DF_UC) {
1262 num_uses++;
1263 if (df_attributes & DF_C_WIDE) {
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700[diff] [blame]1264 num_uses++;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1265 }
1266 }
1267 }
1268
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1269 AllocateSSAUseData(mir, num_uses);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1270
1271 int num_defs = 0;
1272
1273 if (df_attributes & DF_HAS_DEFS) {
1274 num_defs++;
1275 if (df_attributes & DF_A_WIDE) {
1276 num_defs++;
1277 }
1278 }
1279
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1280 AllocateSSADefData(mir, num_defs);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1281
Ian Rogers29a26482014-05-02 15:27:29 -0700[diff] [blame]1282 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1283
1284 if (df_attributes & DF_HAS_USES) {
1285 num_uses = 0;
1286 if (df_attributes & DF_UA) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1287 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA, num_uses++);
1288 if (df_attributes & DF_A_WIDE) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1289 HandleSSAUse(mir->ssa_rep->uses, d_insn->vA+1, num_uses++);
1290 }
1291 }
1292 if (df_attributes & DF_UB) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1293 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB, num_uses++);
1294 if (df_attributes & DF_B_WIDE) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1295 HandleSSAUse(mir->ssa_rep->uses, d_insn->vB+1, num_uses++);
1296 }
1297 }
1298 if (df_attributes & DF_UC) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1299 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC, num_uses++);
1300 if (df_attributes & DF_C_WIDE) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1301 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+1, num_uses++);
1302 }
1303 }
1304 }
1305 if (df_attributes & DF_HAS_DEFS) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1306 HandleSSADef(mir->ssa_rep->defs, d_insn->vA, 0);
1307 if (df_attributes & DF_A_WIDE) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1308 HandleSSADef(mir->ssa_rep->defs, d_insn->vA+1, 1);
1309 }
1310 }
1311 }
1312
buzbee1fd33462013-03-25 13:40:45 -0700[diff] [blame]1313 /*
1314 * Take a snapshot of Dalvik->SSA mapping at the end of each block. The
1315 * input to PHI nodes can be derived from the snapshot of all
1316 * predecessor blocks.
1317 */
Jean Christophe Beyler4896d7b2014-05-01 15:36:22 -0700[diff] [blame]1318 bb->data_flow_info->vreg_to_ssa_map_exit =
Vladimir Markoe4fcc5b2015-02-13 10:28:29 +0000[diff] [blame]1319 arena_->AllocArray<int32_t>(GetNumOfCodeAndTempVRs(), kArenaAllocDFInfo);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1320
Vladimir Marko1c6ea442014-12-19 18:11:35 +0000[diff] [blame]1321 memcpy(bb->data_flow_info->vreg_to_ssa_map_exit, vreg_to_ssa_map_,
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1322 sizeof(int) * GetNumOfCodeAndTempVRs());
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1323 return true;
1324}
1325
Razvan A Lupusoru6f4dcae2014-09-29 11:59:12 -0700[diff] [blame]1326void MIRGraph::InitializeBasicBlockDataFlow() {
1327 /*
1328 * Allocate the BasicBlockDataFlow structure for the entry and code blocks.
1329 */
1330 for (BasicBlock* bb : block_list_) {
1331 if (bb->hidden == true) continue;
1332 if (bb->block_type == kDalvikByteCode ||
1333 bb->block_type == kEntryBlock ||
1334 bb->block_type == kExitBlock) {
1335 bb->data_flow_info =
1336 static_cast<BasicBlockDataFlow*>(arena_->Alloc(sizeof(BasicBlockDataFlow),
1337 kArenaAllocDFInfo));
1338 }
1339 }
1340}
1341
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1342/* Setup the basic data structures for SSA conversion */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1343void MIRGraph::CompilerInitializeSSAConversion() {
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1344 size_t num_reg = GetNumOfCodeAndTempVRs();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1345
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1346 ssa_base_vregs_.clear();
1347 ssa_base_vregs_.reserve(num_reg + GetDefCount() + 128);
1348 ssa_subscripts_.clear();
1349 ssa_subscripts_.reserve(num_reg + GetDefCount() + 128);
1350
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1351 /*
1352 * Initial number of SSA registers is equal to the number of Dalvik
1353 * registers.
1354 */
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1355 SetNumSSARegs(num_reg);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1356
1357 /*
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1358 * Initialize the SSA2Dalvik map list. For the first num_reg elements,
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1359 * the subscript is 0 so we use the ENCODE_REG_SUB macro to encode the value
1360 * into "(0 << 16) | i"
1361 */
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1362 for (unsigned int i = 0; i < num_reg; i++) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1363 ssa_base_vregs_.push_back(i);
1364 ssa_subscripts_.push_back(0);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1365 }
1366
1367 /*
1368 * Initialize the DalvikToSSAMap map. There is one entry for each
1369 * Dalvik register, and the SSA names for those are the same.
1370 */
Vladimir Markoe4fcc5b2015-02-13 10:28:29 +0000[diff] [blame]1371 vreg_to_ssa_map_ = arena_->AllocArray<int32_t>(num_reg, kArenaAllocDFInfo);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1372 /* Keep track of the higest def for each dalvik reg */
Vladimir Markoe4fcc5b2015-02-13 10:28:29 +0000[diff] [blame]1373 ssa_last_defs_ = arena_->AllocArray<int>(num_reg, kArenaAllocDFInfo);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1374
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1375 for (unsigned int i = 0; i < num_reg; i++) {
Vladimir Marko1c6ea442014-12-19 18:11:35 +0000[diff] [blame]1376 vreg_to_ssa_map_[i] = i;
1377 ssa_last_defs_[i] = 0;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1378 }
1379
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -0800[diff] [blame]1380 // Create a compiler temporary for Method*. This is done after SSA initialization.
Razvan A Lupusoru8d0d03e2014-06-06 17:04:52 -0700[diff] [blame]1381 CompilerTemp* method_temp = GetNewCompilerTemp(kCompilerTempSpecialMethodPtr, false);
1382 // The MIR graph keeps track of the sreg for method pointer specially, so record that now.
1383 method_sreg_ = method_temp->s_reg_low;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1384
Razvan A Lupusoru6f4dcae2014-09-29 11:59:12 -0700[diff] [blame]1385 InitializeBasicBlockDataFlow();
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1386}
1387
Vladimir Markocc234812015-04-07 09:36:09 +0100[diff] [blame]1388uint32_t MIRGraph::GetUseCountWeight(BasicBlock* bb) const {
1389 // Each level of nesting adds *100 to count, up to 3 levels deep.
1390 uint32_t depth = std::min(3U, static_cast<uint32_t>(bb->nesting_depth));
1391 uint32_t weight = std::max(1U, depth * 100);
1392 return weight;
1393}
1394
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1395/*
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1396 * Count uses, weighting by loop nesting depth. This code only
1397 * counts explicitly used s_regs. A later phase will add implicit
1398 * counts for things such as Method*, null-checked references, etc.
1399 */
Vladimir Marko8b858e12014-11-27 14:52:37 +0000[diff] [blame]1400void MIRGraph::CountUses(BasicBlock* bb) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1401 if (bb->block_type != kDalvikByteCode) {
Jean Christophe Beyler4e97c532014-01-07 10:07:18 -0800[diff] [blame]1402 return;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1403 }
Vladimir Markocc234812015-04-07 09:36:09 +0100[diff] [blame]1404 uint32_t weight = GetUseCountWeight(bb);
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]1405 for (MIR* mir = bb->first_mir_insn; (mir != nullptr); mir = mir->next) {
1406 if (mir->ssa_rep == nullptr) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1407 continue;
1408 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1409 for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
1410 int s_reg = mir->ssa_rep->uses[i];
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1411 raw_use_counts_[s_reg] += 1u;
1412 use_counts_[s_reg] += weight;
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1413 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1414 }
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1415}
1416
1417/* Verify if all the successor is connected with all the claimed predecessors */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1418bool MIRGraph::VerifyPredInfo(BasicBlock* bb) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1419 for (BasicBlockId pred_id : bb->predecessors) {
1420 BasicBlock* pred_bb = GetBasicBlock(pred_id);
1421 DCHECK(pred_bb != nullptr);
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1422 bool found = false;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1423 if (pred_bb->taken == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1424 found = true;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1425 } else if (pred_bb->fall_through == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1426 found = true;
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1427 } else if (pred_bb->successor_block_list_type != kNotUsed) {
Vladimir Markoe39c54e2014-09-22 14:50:02 +0100[diff] [blame]1428 for (SuccessorBlockInfo* successor_block_info : pred_bb->successor_blocks) {
buzbee0d829482013-10-11 15:24:55 -0700[diff] [blame]1429 BasicBlockId succ_bb = successor_block_info->block;
1430 if (succ_bb == bb->id) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1431 found = true;
1432 break;
1433 }
1434 }
1435 }
1436 if (found == false) {
1437 char block_name1[BLOCK_NAME_LEN], block_name2[BLOCK_NAME_LEN];
1438 GetBlockName(bb, block_name1);
1439 GetBlockName(pred_bb, block_name2);
1440 DumpCFG("/sdcard/cfg/", false);
Vladimir Marko312eb252014-10-07 15:01:57 +0100[diff] [blame]1441 LOG(FATAL) << "Successor " << block_name1 << " not found from "
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1442 << block_name2;
1443 }
1444 }
1445 return true;
1446}
1447
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700[diff] [blame]1448void MIRGraph::VerifyDataflow() {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1449 /* Verify if all blocks are connected as claimed */
buzbee56c71782013-09-05 17:13:19 -0700[diff] [blame]1450 AllNodesIterator iter(this);
Mathieu Chartier2cebb242015-04-21 16:50:40 -0700[diff] [blame]1451 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) {
buzbee311ca162013-02-28 15:56:43 -0800[diff] [blame]1452 VerifyPredInfo(bb);
1453 }
1454}
1455
1456} // namespace art