Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
| 19 | #include "stringprintf.h" |
| 20 | |
| 21 | #include <iostream> |
| 22 | |
| 23 | namespace art { |
| 24 | namespace arm { |
| 25 | |
| 26 | DisassemblerArm::DisassemblerArm() { |
| 27 | } |
| 28 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 29 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 30 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 31 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 32 | DumpArm(os, cur); |
| 33 | } |
| 34 | } else { |
| 35 | // remove thumb specifier bits |
| 36 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 37 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 38 | for (const uint8_t* cur = begin; cur < end;) { |
| 39 | cur += DumpThumb16(os, cur); |
| 40 | } |
| 41 | } |
| 42 | } |
| 43 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 44 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 45 | "eq", // 0000 - equal |
| 46 | "ne", // 0001 - not-equal |
| 47 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 48 | "cc", // 0011 - carry-clear, less than |
| 49 | "mi", // 0100 - minus, negative |
| 50 | "pl", // 0101 - plus, positive or zero |
| 51 | "vs", // 0110 - overflow |
| 52 | "vc", // 0111 - no overflow |
| 53 | "hi", // 1000 - unsigned higher |
| 54 | "ls", // 1001 - unsigned lower or same |
| 55 | "ge", // 1010 - signed greater than or equal |
| 56 | "lt", // 1011 - signed less than |
| 57 | "gt", // 1100 - signed greater than |
| 58 | "le", // 1101 - signed less than or equal |
| 59 | "", // 1110 - always |
| 60 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 64 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 65 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 66 | } else { |
| 67 | os << "Unexpected condition: " << cond; |
| 68 | } |
| 69 | } |
| 70 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 71 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
| 72 | os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 76 | return ptr[0] | (ptr[1] << 8); |
| 77 | } |
| 78 | |
| 79 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 80 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 81 | } |
| 82 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 83 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 84 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 85 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 86 | }; |
| 87 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 88 | static const char* kThumbDataProcessingOperations[] = { |
| 89 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 90 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 91 | }; |
| 92 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 93 | struct ArmRegister { |
| 94 | ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 95 | ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 96 | uint32_t r; |
| 97 | }; |
| 98 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 99 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 100 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 101 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 102 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 103 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 104 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 105 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 106 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 107 | } |
| 108 | return os; |
| 109 | } |
| 110 | |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 111 | struct ThumbRegister : ArmRegister { |
| 112 | ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | struct Rm { |
| 116 | Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
| 117 | uint32_t shift; |
| 118 | ArmRegister rm; |
| 119 | }; |
| 120 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 121 | os << r.rm; |
| 122 | if (r.shift != 0) { |
| 123 | os << "-shift-" << r.shift; // TODO |
| 124 | } |
| 125 | return os; |
| 126 | } |
| 127 | |
| 128 | struct Imm12 { |
| 129 | Imm12(uint32_t instruction) : rotate((instruction >> 8) & 0xf), imm(instruction & 0xff) {} |
| 130 | uint32_t rotate; |
| 131 | uint32_t imm; |
| 132 | }; |
| 133 | std::ostream& operator<<(std::ostream& os, const Imm12& rhs) { |
| 134 | uint32_t imm = (rhs.imm >> (2 * rhs.rotate)) | (rhs.imm << (32 - (2 * rhs.rotate))); |
| 135 | os << "#" << imm; |
| 136 | return os; |
| 137 | } |
| 138 | |
| 139 | struct RegisterList { |
| 140 | RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
| 141 | uint32_t register_list; |
| 142 | }; |
| 143 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 144 | if (rhs.register_list == 0) { |
| 145 | os << "<no register list?>"; |
| 146 | return os; |
| 147 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 148 | os << "{"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 149 | bool first = true; |
| 150 | for (size_t i = 0; i < 16; i++) { |
| 151 | if ((rhs.register_list & (1 << i)) != 0) { |
| 152 | if (first) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 153 | first = false; |
| 154 | } else { |
| 155 | os << ", "; |
| 156 | } |
| 157 | os << ArmRegister(i); |
| 158 | } |
| 159 | } |
| 160 | os << "}"; |
| 161 | return os; |
| 162 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 163 | |
| 164 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 165 | uint32_t instruction = ReadU32(instr_ptr); |
| 166 | uint32_t cond = (instruction >> 28) & 0xf; |
| 167 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 168 | std::ostringstream opcode; |
| 169 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 170 | switch (op1) { |
| 171 | case 0: |
| 172 | case 1: // Data processing instructions. |
| 173 | { |
| 174 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 175 | opcode << (((instruction >> 5) & 1) ? "blx" : "bx"); |
| 176 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 177 | break; |
| 178 | } |
| 179 | bool i = (instruction & (1 << 25)) != 0; |
| 180 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 181 | opcode << kDataProcessingOperations[(instruction >> 21) & 0xf] |
| 182 | << kConditionCodeNames[cond] |
| 183 | << (s ? "s" : ""); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 184 | args << ArmRegister(instruction, 12) << ", "; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 185 | if (i) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 186 | args << ArmRegister(instruction, 16) << ", " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 187 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 188 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 189 | } |
| 190 | } |
| 191 | break; |
| 192 | case 2: // Load/store word and unsigned byte. |
| 193 | { |
| 194 | bool p = (instruction & (1 << 24)) != 0; |
| 195 | bool b = (instruction & (1 << 22)) != 0; |
| 196 | bool w = (instruction & (1 << 21)) != 0; |
| 197 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 198 | opcode << (l ? "ldr" : "str") << (b ? "b" : "") << kConditionCodeNames[cond]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 199 | args << ArmRegister(instruction, 12) << ", "; |
| 200 | ArmRegister rn(instruction, 16); |
| 201 | if (rn.r == 0xf) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 202 | UNIMPLEMENTED(FATAL) << "literals"; |
| 203 | } else { |
| 204 | bool wback = !p || w; |
| 205 | if (p && !wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 206 | args << "[" << rn << ", " << Imm12(instruction) << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 207 | } else if (p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 208 | args << "[" << rn << ", " << Imm12(instruction) << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 209 | } else if (!p && wback) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 210 | args << "[" << rn << "], " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 211 | } else { |
| 212 | LOG(FATAL) << p << " " << w; |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | break; |
| 217 | case 4: // Load/store multiple. |
| 218 | { |
| 219 | bool p = (instruction & (1 << 24)) != 0; |
| 220 | bool u = (instruction & (1 << 23)) != 0; |
| 221 | bool w = (instruction & (1 << 21)) != 0; |
| 222 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 223 | opcode << (l ? "ldm" : "stm") |
| 224 | << (u ? 'i' : 'd') |
| 225 | << (p ? 'b' : 'a') |
| 226 | << kConditionCodeNames[cond]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 227 | args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 228 | } |
| 229 | break; |
| 230 | default: |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 231 | opcode << "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 232 | break; |
| 233 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 234 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
| 235 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instruction, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 239 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 240 | // |111|1 1|1000000|0000|1111110000000000| |
| 241 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 242 | // |---|---|-------|----|----------------| |
| 243 | // |332|2 2|2222222|1111|1111110000000000| |
| 244 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 245 | // |---|---|-------|----|----------------| |
| 246 | // |111|op1| op2 | | | |
| 247 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 248 | if (op1 == 0) { |
| 249 | return DumpThumb16(os, instr_ptr); |
| 250 | } |
| 251 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 252 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 253 | std::ostringstream opcode; |
| 254 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 255 | switch (op1) { |
| 256 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 257 | break; |
| 258 | case 1: |
| 259 | switch (op2) { |
| 260 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 261 | case 0x10: case 0x11: case 0x12: case 0x13: case 0x18: case 0x19: case 0x1A: case 0x1B: { |
| 262 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 263 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 264 | // |---|--|--|--|-|--|----|----------------| |
| 265 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 266 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 267 | // |---|--|--|--|-|--|----|----------------| |
| 268 | // |111|01|00|op|0|WL| Rn | | |
| 269 | // |111|01| op2 | | | |
| 270 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 271 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 272 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 273 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 274 | uint32_t op = (instr >> 23) & 3; |
| 275 | uint32_t W = (instr >> 21) & 1; |
| 276 | uint32_t L = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 277 | ArmRegister Rn(instr, 16); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 278 | if (op == 1 || op == 2) { |
| 279 | if (op == 1) { |
| 280 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 281 | opcode << "stm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 282 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 283 | } else { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 284 | if (Rn.r != 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 285 | opcode << "ldm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 286 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 287 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 288 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 289 | } |
| 290 | } |
| 291 | } else { |
| 292 | if (L == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 293 | if (Rn.r != 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 294 | opcode << "stmdb"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 295 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 296 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 297 | opcode << "push"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 298 | } |
| 299 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 300 | opcode << "ldmdb"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 301 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 302 | } |
| 303 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 304 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 305 | } |
| 306 | break; |
| 307 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 308 | case 0x20: case 0x21: case 0x22: case 0x23: // 01xxxxx |
| 309 | case 0x24: case 0x25: case 0x26: case 0x27: |
| 310 | case 0x28: case 0x29: case 0x2A: case 0x2B: |
| 311 | case 0x2C: case 0x2D: case 0x2E: case 0x2F: |
| 312 | case 0x30: case 0x31: case 0x32: case 0x33: |
| 313 | case 0x34: case 0x35: case 0x36: case 0x37: |
| 314 | case 0x38: case 0x39: case 0x3A: case 0x3B: |
| 315 | case 0x3C: case 0x3D: case 0x3E: case 0x3F: { |
| 316 | // Data-processing (shifted register) |
| 317 | // |111|1110|0000|0|0000|1111|1100|0000|0000| |
| 318 | // |5 3|2109|8765|4|3 0|5 |10 8|7 5 |3 0| |
| 319 | // |---|----|----|-|----|----|----|----|----| |
| 320 | // |332|2222|2222|2|1111|1111|1100|0000|0000| |
| 321 | // |1 9|8765|4321|0|9 6|5 |10 8|7 5 |3 0| |
| 322 | // |---|----|----|-|----|----|----|----|----| |
| 323 | // |111|0101| op3|S| Rn | | Rd | | Rm | |
| 324 | uint32_t op3 = (instr >> 21) & 0xF; |
| 325 | uint32_t S = (instr >> 20) & 1; |
| 326 | uint32_t Rn = (instr >> 16) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 327 | ArmRegister Rd(instr, 8); |
| 328 | ArmRegister Rm(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 329 | switch (op3) { |
| 330 | case 0x0: |
| 331 | if (Rn != 0xF) { |
| 332 | opcode << "and"; |
| 333 | } else { |
| 334 | opcode << "tst"; |
| 335 | S = 0; // don't print 's' |
| 336 | } |
| 337 | break; |
| 338 | case 0x1: opcode << "bic"; break; |
| 339 | case 0x2: |
| 340 | if (Rn != 0xF) { |
| 341 | opcode << "orr"; |
| 342 | } else { |
| 343 | opcode << "mov"; |
| 344 | } |
| 345 | break; |
| 346 | case 0x3: |
| 347 | if (Rn != 0xF) { |
| 348 | opcode << "orn"; |
| 349 | } else { |
| 350 | opcode << "mvn"; |
| 351 | } |
| 352 | break; |
| 353 | case 0x4: |
| 354 | if (Rn != 0xF) { |
| 355 | opcode << "eor"; |
| 356 | } else { |
| 357 | opcode << "teq"; |
| 358 | S = 0; // don't print 's' |
| 359 | } |
| 360 | break; |
| 361 | case 0x6: opcode << "pkh"; break; |
| 362 | case 0x8: |
| 363 | if (Rn != 0xF) { |
| 364 | opcode << "add"; |
| 365 | } else { |
| 366 | opcode << "cmn"; |
| 367 | S = 0; // don't print 's' |
| 368 | } |
| 369 | break; |
| 370 | case 0xA: opcode << "adc"; break; |
| 371 | case 0xB: opcode << "sbc"; break; |
| 372 | } |
| 373 | |
| 374 | if (S == 1) { |
| 375 | opcode << "s"; |
| 376 | } |
| 377 | opcode << ".w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 378 | args << Rd << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 379 | break; |
| 380 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 381 | default: |
| 382 | break; |
| 383 | } |
| 384 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 385 | case 2: |
| 386 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 387 | // Data-processing (modified immediate) |
| 388 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 389 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 390 | // |---|--|--|----|-|----|-|---|----|--------| |
| 391 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 392 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 393 | // |---|--|--|----|-|----|-|---|----|--------| |
| 394 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 395 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
| 396 | // 111 10 00 0110 0 0000 1 000 0000 10101101 - f0c080ad |
| 397 | uint32_t i = (instr >> 26) & 1; |
| 398 | uint32_t op3 = (instr >> 21) & 0xF; |
| 399 | uint32_t S = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 400 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 401 | uint32_t imm3 = (instr >> 12) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 402 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 403 | uint32_t imm8 = instr & 0xFF; |
| 404 | int32_t imm32 = (i << 12) | (imm3 << 8) | imm8; |
| 405 | switch (op3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 406 | case 0x0: opcode << "and"; break; |
| 407 | case 0x1: opcode << "bic"; break; |
| 408 | case 0x2: opcode << "orr"; break; |
| 409 | case 0x3: opcode << "orn"; break; |
| 410 | case 0x4: opcode << "eor"; break; |
| 411 | case 0x8: opcode << "add"; break; |
| 412 | case 0xA: opcode << "adc"; break; |
| 413 | case 0xB: opcode << "sbc"; break; |
| 414 | case 0xD: opcode << "sub"; break; |
| 415 | case 0xE: opcode << "rsb"; break; |
| 416 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 417 | } |
| 418 | if (S == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 419 | opcode << "s"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 420 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 421 | args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 422 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 423 | // Data-processing (plain binary immediate) |
| 424 | // |111|11|10|00000|0000|1|111110000000000| |
| 425 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 426 | // |---|--|--|-----|----|-|---------------| |
| 427 | // |332|22|22|22222|1111|1|111110000000000| |
| 428 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 429 | // |---|--|--|-----|----|-|---------------| |
| 430 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 431 | uint32_t op3 = (instr >> 20) & 0x1F; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 432 | switch (op3) { |
| 433 | case 0x04: { |
| 434 | // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 435 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 436 | uint32_t i = (instr >> 26) & 1; |
| 437 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 438 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 439 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 440 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 441 | opcode << "movw"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 442 | args << Rd << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 443 | break; |
| 444 | } |
| 445 | case 0x0A: { |
| 446 | // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 447 | ArmRegister Rd(instr, 8); |
| 448 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 449 | uint32_t i = (instr >> 26) & 1; |
| 450 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 451 | uint32_t imm8 = instr & 0xFF; |
| 452 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 453 | opcode << "sub.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 454 | args << Rd << ", " << Rn << ", #" << imm12; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 455 | break; |
| 456 | } |
| 457 | default: |
| 458 | break; |
| 459 | } |
| 460 | } else { |
| 461 | // Branches and miscellaneous control |
| 462 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 463 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 464 | // |---|--|-------|----|-|---|----|--------| |
| 465 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 466 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 467 | // |---|--|-------|----|-|---|----|--------| |
| 468 | // |111|10| op2 | |1|op3|op4 | | |
| 469 | |
| 470 | uint32_t op3 = (instr >> 12) & 7; |
| 471 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 472 | switch (op3) { |
| 473 | case 0: |
| 474 | if ((op2 & 0x38) != 0x38) { |
| 475 | // Conditional branch |
| 476 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 477 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 478 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 479 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 480 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 481 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 482 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 483 | uint32_t S = (instr >> 26) & 1; |
| 484 | uint32_t J2 = (instr >> 11) & 1; |
| 485 | uint32_t J1 = (instr >> 13) & 1; |
| 486 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 487 | uint32_t imm11 = instr & 0x7FF; |
| 488 | uint32_t cond = (instr >> 22) & 0xF; |
| 489 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 490 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 491 | opcode << "b"; |
| 492 | DumpCond(opcode, cond); |
| 493 | opcode << ".w"; |
| 494 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 495 | } |
| 496 | break; |
| 497 | case 2: |
| 498 | case 1: case 3: |
| 499 | break; |
| 500 | case 4: case 6: case 5: case 7: { |
| 501 | // BL, BLX (immediate) |
| 502 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 503 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 504 | // |---|--|-|----------|--|--|-|--|-----------| |
| 505 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 506 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 507 | // |---|--|-|----------|--|--|-|--|-----------| |
| 508 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 509 | uint32_t S = (instr >> 26) & 1; |
| 510 | uint32_t J2 = (instr >> 11) & 1; |
| 511 | uint32_t L = (instr >> 12) & 1; |
| 512 | uint32_t J1 = (instr >> 13) & 1; |
| 513 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 514 | uint32_t imm11 = instr & 0x7FF; |
| 515 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 516 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 517 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 518 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 519 | } |
| 520 | uint32_t I1 = ~(J1 ^ S); |
| 521 | uint32_t I2 = ~(J2 ^ S); |
| 522 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 523 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 524 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 525 | break; |
| 526 | } |
| 527 | } |
| 528 | } |
| 529 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 530 | case 3: |
| 531 | switch (op2) { |
| 532 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 533 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 534 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 535 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 536 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 537 | // |---|--|---|---|-|----|----|------|------| |
| 538 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 539 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 540 | // |---|--|---|---|-|----|----|------|------| |
| 541 | // |111|11|000|op3|0| | | op4 | | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 542 | uint32_t op3 = (instr >> 21) & 7; |
| 543 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 544 | switch (op3) { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 545 | case 0x0: case 0x4: { |
| 546 | // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii |
| 547 | // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 548 | ArmRegister Rn(instr, 16); |
| 549 | ArmRegister Rt(instr, 12); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 550 | opcode << "strb"; |
| 551 | if ((instr & 0x800) != 0) { |
| 552 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 553 | args << Rt << ", [" << Rn << ",#" << imm8 << "]"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 554 | } else { |
| 555 | uint32_t imm2 = (instr >> 4) & 3; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 556 | ArmRegister Rm(instr, 0); |
| 557 | args << Rt << ", [" << Rn << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 558 | if (imm2 != 0) { |
| 559 | args << ", " << "lsl #" << imm2; |
| 560 | } |
| 561 | args << "]"; |
| 562 | } |
| 563 | break; |
| 564 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 565 | case 0x2: case 0x6: { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 566 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
| 567 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 568 | ArmRegister Rn(instr, 16); |
| 569 | ArmRegister Rt(instr, 12); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 570 | if (op3 == 2) { |
| 571 | uint32_t P = (instr >> 10) & 1; |
| 572 | uint32_t U = (instr >> 9) & 1; |
| 573 | uint32_t W = (instr >> 8) & 1; |
| 574 | uint32_t imm8 = instr & 0xFF; |
| 575 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 576 | if (Rn.r == 13 && P == 1 && U == 0 && W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 577 | opcode << "push"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 578 | args << Rt; |
| 579 | } else if (Rn.r == 15 || (P == 0 && W == 0)) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 580 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 581 | } else { |
| 582 | if (P == 1 && U == 1 && W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 583 | opcode << "strt"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 584 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 585 | opcode << "str"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 586 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 587 | args << Rt << ", [" << Rn; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 588 | if (P == 0 && W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 589 | args << "], #" << imm32; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 590 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 591 | args << ", #" << imm32 << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 592 | if (W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 593 | args << "!"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 594 | } |
| 595 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 596 | } |
| 597 | } else if (op3 == 6) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 598 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 599 | opcode << "str.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 600 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 601 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 602 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 603 | } |
| 604 | } |
| 605 | |
| 606 | break; |
| 607 | } |
| 608 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 609 | // Load word |
| 610 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 611 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 612 | // |---|--|--|---|--|-|----|----|------|------| |
| 613 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 614 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 615 | // |---|--|--|---|--|-|----|----|------|------| |
| 616 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 617 | // |111|11| op2 | | | imm12 | |
| 618 | uint32_t op3 = (instr >> 23) & 3; |
| 619 | uint32_t op4 = (instr >> 6) & 0x3F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 620 | ArmRegister Rn(instr, 16); |
| 621 | ArmRegister Rt(instr, 12); |
| 622 | if (op3 == 1 || Rn.r == 15) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 623 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 624 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 625 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 626 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 627 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 628 | } else if (op4 == 0) { |
| 629 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 630 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 631 | ArmRegister rm(instr, 0); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 632 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 633 | args << Rt << ", [" << Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 634 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 635 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 636 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 637 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 638 | } else { |
| 639 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 640 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 641 | opcode << "ldrt"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 642 | args << Rt << ", [" << Rn << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 643 | } |
| 644 | break; |
| 645 | } |
| 646 | } |
| 647 | default: |
| 648 | break; |
| 649 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 650 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 651 | return 4; |
| 652 | } |
| 653 | |
| 654 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 655 | uint16_t instr = ReadU16(instr_ptr); |
| 656 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 657 | if (is_32bit) { |
| 658 | return DumpThumb32(os, instr_ptr); |
| 659 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 660 | std::ostringstream opcode; |
| 661 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 662 | uint16_t opcode1 = instr >> 10; |
| 663 | if (opcode1 < 0x10) { |
| 664 | // shift (immediate), add, subtract, move, and compare |
| 665 | uint16_t opcode2 = instr >> 9; |
| 666 | switch (opcode2) { |
| 667 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 668 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 669 | // Logical shift left - 00 000xx xxxxxxxxx |
| 670 | // Logical shift right - 00 001xx xxxxxxxxx |
| 671 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 672 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 673 | ThumbRegister rm(instr, 3); |
| 674 | ThumbRegister Rd(instr, 7); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 675 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 676 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 677 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 678 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 679 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 680 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 681 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 682 | args << Rd << ", " << rm << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 683 | break; |
| 684 | } |
| 685 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 686 | // Add register - 00 01100 mmm nnn ddd |
| 687 | // Sub register - 00 01101 mmm nnn ddd |
| 688 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 689 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 690 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 691 | ThumbRegister Rn(instr, 3); |
| 692 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 693 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 694 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 695 | } else { |
| 696 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 697 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 698 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 699 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 700 | } |
| 701 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 702 | args << Rd << ", " << Rn; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 703 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 704 | ArmRegister Rm(imm3_or_Rm); |
| 705 | args << ", " << Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 706 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 707 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 708 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 709 | break; |
| 710 | } |
| 711 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 712 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 713 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 714 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 715 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 716 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 717 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 718 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 719 | ThumbRegister Rn(instr, 8); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 720 | uint16_t imm8 = instr & 0xFF; |
| 721 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 722 | case 4: opcode << "movs"; break; |
| 723 | case 5: opcode << "cmp"; break; |
| 724 | case 6: opcode << "adds"; break; |
| 725 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 726 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 727 | args << Rn << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 728 | break; |
| 729 | } |
| 730 | default: |
| 731 | break; |
| 732 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 733 | } else if (opcode1 == 0x10) { |
| 734 | // Data-processing |
| 735 | uint16_t opcode2 = (instr >> 6) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 736 | ThumbRegister rm(instr, 3); |
| 737 | ThumbRegister rdn(instr, 0); |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 738 | opcode << kThumbDataProcessingOperations[opcode2]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 739 | args << rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 740 | } else if (opcode1 == 0x11) { |
| 741 | // Special data instructions and branch and exchange |
| 742 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 743 | switch (opcode2) { |
| 744 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 745 | // Add low registers - 010001 0000 xxxxxx |
| 746 | // Add high registers - 010001 0001/001x xxxxxx |
| 747 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 748 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 749 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 750 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 751 | opcode << "add"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 752 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 753 | break; |
| 754 | } |
| 755 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 756 | // Move low registers - 010001 1000 xxxxxx |
| 757 | // Move high registers - 010001 1001/101x xxxxxx |
| 758 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 759 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 760 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 761 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 762 | opcode << "mov"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 763 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 764 | break; |
| 765 | } |
| 766 | case 0x5: case 0x6: case 0x7: { |
| 767 | // Compare high registers - 010001 0101/011x xxxxxx |
| 768 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 769 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 770 | uint16_t Rn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 771 | ArmRegister N_Rn((N << 3) | Rn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 772 | opcode << "cmp"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 773 | args << N_Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 774 | break; |
| 775 | } |
| 776 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 777 | // Branch and exchange - 010001 110x xxxxxx |
| 778 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 779 | ArmRegister rm(instr, 3); |
| 780 | opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); |
| 781 | args << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 782 | break; |
| 783 | } |
| 784 | default: |
| 785 | break; |
| 786 | } |
| 787 | } else if ((instr & 0xF000) == 0xB000) { |
| 788 | // Miscellaneous 16-bit instructions |
| 789 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 790 | switch (opcode2) { |
| 791 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 792 | // Add immediate to SP - 1011 00000 ii iiiii |
| 793 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 794 | int imm7 = instr & 0x7F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 795 | opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 796 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 797 | break; |
| 798 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 799 | case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx |
| 800 | case 0x0C: case 0x0D: case 0x0E: case 0x0F: { |
| 801 | // CBNZ, CBZ |
| 802 | uint16_t op = (instr >> 11) & 1; |
| 803 | uint16_t i = (instr >> 9) & 1; |
| 804 | uint16_t imm5 = (instr >> 3) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 805 | ThumbRegister Rn(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 806 | opcode << (op != 0 ? "cbnz" : "cbz"); |
| 807 | uint32_t imm32 = (i << 7) | (imm5 << 1); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 808 | args << Rn << ", "; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 809 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
| 810 | break; |
| 811 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 812 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 813 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 814 | // If-Then, and hints |
| 815 | uint16_t opA = (instr >> 4) & 0xF; |
| 816 | uint16_t opB = instr & 0xF; |
| 817 | if (opB == 0) { |
| 818 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 819 | case 0: opcode << "nop"; break; |
| 820 | case 1: opcode << "yield"; break; |
| 821 | case 2: opcode << "wfe"; break; |
| 822 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 823 | default: break; |
| 824 | } |
| 825 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 826 | opcode << "it"; |
| 827 | args << reinterpret_cast<void*>(opB) << " "; |
| 828 | DumpCond(args, opA); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 829 | } |
| 830 | break; |
| 831 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 832 | default: |
| 833 | break; |
| 834 | } |
| 835 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 836 | ((instr & 0xE000) == 0x8000)) { |
| 837 | // Load/store single data item |
| 838 | uint16_t opA = instr >> 12; |
| 839 | //uint16_t opB = (instr >> 9) & 7; |
| 840 | switch (opA) { |
| 841 | case 0x6: { |
| 842 | // STR Rt, Rn, #imm - 01100 iiiii nnn ttt |
| 843 | // LDR Rt, Rn, #imm - 01101 iiiii nnn ttt |
| 844 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 845 | ThumbRegister Rn(instr, 3); |
| 846 | ThumbRegister Rt(instr, 7); |
| 847 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 848 | args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 849 | break; |
| 850 | } |
| 851 | case 0x9: { |
| 852 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 853 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 854 | uint16_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame^] | 855 | ThumbRegister Rt(instr, 8); |
| 856 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 857 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 858 | break; |
| 859 | } |
| 860 | default: |
| 861 | break; |
| 862 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 863 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 864 | uint16_t imm11 = instr & 0x7FFF; |
| 865 | int32_t imm32 = imm11 << 1; |
| 866 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 867 | opcode << "b"; |
| 868 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 869 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 870 | os << StringPrintf("\t\t\t%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 871 | } |
| 872 | return 2; |
| 873 | } |
| 874 | |
| 875 | } // namespace arm |
| 876 | } // namespace art |