Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "x86_lir.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 25 | class X86Mir2Lir FINAL : public Mir2Lir { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 26 | public: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
| 28 | |
| 29 | // Required for target - codegen helpers. |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 30 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 31 | RegLocation rl_dest, int lit); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 32 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 33 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 34 | RegStorage LoadHelper(ThreadOffset<4> offset); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 35 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, |
| 36 | int s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 37 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
| 38 | OpSize size); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 39 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 40 | RegStorage r_dest, OpSize size, int s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 41 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 42 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
| 43 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 44 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 45 | OpSize size); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 46 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 47 | RegStorage r_src, OpSize size, int s_reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 48 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | |
| 50 | // Required for target - register utilities. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 51 | RegStorage AllocTypedTemp(bool fp_hint, int reg_class); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 52 | RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 53 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 54 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 55 | RegLocation GetReturnAlt(); |
| 56 | RegLocation GetReturnWideAlt(); |
| 57 | RegLocation LocCReturn(); |
| 58 | RegLocation LocCReturnDouble(); |
| 59 | RegLocation LocCReturnFloat(); |
| 60 | RegLocation LocCReturnWide(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 61 | uint64_t GetRegMaskCommon(RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | void AdjustSpillMask(); |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 63 | void ClobberCallerSave(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 64 | void FreeCallTemps(); |
| 65 | void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); |
| 66 | void LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 67 | void MarkPreservedSingle(int v_reg, RegStorage reg); |
| 68 | void MarkPreservedDouble(int v_reg, RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 69 | void CompilerInitializeRegAlloc(); |
| 70 | |
| 71 | // Required for target - miscellaneous. |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 72 | void AssembleLIR(); |
| 73 | int AssignInsnOffsets(); |
| 74 | void AssignOffsets(); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 75 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 76 | void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 77 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 78 | const char* GetTargetInstFmt(int opcode); |
| 79 | const char* GetTargetInstName(int opcode); |
| 80 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
| 81 | uint64_t GetPCUseDefEncoding(); |
| 82 | uint64_t GetTargetInstFlags(int opcode); |
| 83 | int GetInsnSize(LIR* lir); |
| 84 | bool IsUnconditionalBranch(LIR* lir); |
| 85 | |
| 86 | // Required for target - Dalvik-level generators. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 87 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 88 | RegLocation rl_src2); |
| 89 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 90 | RegLocation rl_dest, int scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 91 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 92 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 93 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 94 | RegLocation rl_src1, RegLocation rl_shift); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 95 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 96 | RegLocation rl_src2); |
| 97 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 98 | RegLocation rl_src2); |
| 99 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 100 | RegLocation rl_src2); |
| 101 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 102 | RegLocation rl_src2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 103 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 104 | RegLocation rl_src2); |
| 105 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 106 | RegLocation rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 108 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 109 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 110 | bool GenInlinedSqrt(CallInfo* info); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 111 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 112 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 113 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 114 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 115 | RegLocation rl_src2); |
| 116 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 117 | RegLocation rl_src2); |
| 118 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 119 | RegLocation rl_src2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 120 | // TODO: collapse reg_lo, reg_hi |
| 121 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 122 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 123 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 124 | void GenDivZeroCheckWide(RegStorage reg); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 125 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 126 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 128 | void GenExitSequence(); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 129 | void GenSpecialExitSequence(); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 130 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 131 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 132 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 133 | void GenSelect(BasicBlock* bb, MIR* mir); |
| 134 | void GenMemBarrier(MemBarrierKind barrier_kind); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 135 | void GenMoveException(RegLocation rl_dest); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 136 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 137 | int first_bit, int second_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 138 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 139 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 140 | void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 141 | void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 142 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 143 | /* |
| 144 | * @brief Generate a two address long operation with a constant value |
| 145 | * @param rl_dest location of result |
| 146 | * @param rl_src constant source operand |
| 147 | * @param op Opcode to be generated |
| 148 | */ |
| 149 | void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
| 150 | /* |
| 151 | * @brief Generate a three address long operation with a constant value |
| 152 | * @param rl_dest location of result |
| 153 | * @param rl_src1 source operand |
| 154 | * @param rl_src2 constant source operand |
| 155 | * @param op Opcode to be generated |
| 156 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 157 | void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 158 | Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 159 | |
| 160 | /** |
| 161 | * @brief Generate a long arithmetic operation. |
| 162 | * @param rl_dest The destination. |
| 163 | * @param rl_src1 First operand. |
| 164 | * @param rl_src2 Second operand. |
| 165 | * @param op The DEX opcode for the operation. |
| 166 | * @param is_commutative The sources can be swapped if needed. |
| 167 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 168 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 169 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 170 | |
| 171 | /** |
| 172 | * @brief Generate a two operand long arithmetic operation. |
| 173 | * @param rl_dest The destination. |
| 174 | * @param rl_src Second operand. |
| 175 | * @param op The DEX opcode for the operation. |
| 176 | */ |
| 177 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
| 178 | |
| 179 | /** |
| 180 | * @brief Generate a long operation. |
| 181 | * @param rl_dest The destination. Must be in a register |
| 182 | * @param rl_src The other operand. May be in a register or in memory. |
| 183 | * @param op The DEX opcode for the operation. |
| 184 | */ |
| 185 | void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 186 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 187 | /** |
| 188 | * @brief Implement instanceof a final class with x86 specific code. |
| 189 | * @param use_declaring_class 'true' if we can use the class itself. |
| 190 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 191 | * @param rl_dest Result to be set to 0 or 1. |
| 192 | * @param rl_src Object to be tested. |
| 193 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 194 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
| 195 | RegLocation rl_src); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 196 | /* |
| 197 | * |
| 198 | * @brief Implement Set up instanceof a class with x86 specific code. |
| 199 | * @param needs_access_check 'true' if we must check the access. |
| 200 | * @param type_known_final 'true' if the type is known to be a final class. |
| 201 | * @param type_known_abstract 'true' if the type is known to be an abstract class. |
| 202 | * @param use_declaring_class 'true' if the type can be loaded off the current Method*. |
| 203 | * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. |
| 204 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 205 | * @param rl_dest Result to be set to 0 or 1. |
| 206 | * @param rl_src Object to be tested. |
| 207 | */ |
| 208 | void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, |
| 209 | bool type_known_abstract, bool use_declaring_class, |
| 210 | bool can_assume_type_is_in_dex_cache, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 211 | uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 212 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 213 | // Single operation generators. |
| 214 | LIR* OpUnconditionalBranch(LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 215 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 216 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 217 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 218 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 219 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 220 | LIR* OpIT(ConditionCode cond, const char* guide); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 221 | void OpEndIT(LIR* it); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 222 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 223 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 224 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 225 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 226 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
| 227 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 228 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 229 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 230 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 231 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 232 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 233 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 234 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 235 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 236 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 237 | LIR* OpTestSuspend(LIR* target); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 238 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 239 | LIR* OpVldm(RegStorage r_base, int count); |
| 240 | LIR* OpVstm(RegStorage r_base, int count); |
| 241 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 242 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 243 | void OpTlsCmp(ThreadOffset<4> offset, int val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 244 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 245 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 246 | void SpillCoreRegs(); |
| 247 | void UnSpillCoreRegs(); |
| 248 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 249 | bool InexpensiveConstantInt(int32_t value); |
| 250 | bool InexpensiveConstantFloat(int32_t value); |
| 251 | bool InexpensiveConstantLong(int64_t value); |
| 252 | bool InexpensiveConstantDouble(int64_t value); |
| 253 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 254 | /* |
| 255 | * @brief x86 specific codegen for int operations. |
| 256 | * @param opcode Operation to perform. |
| 257 | * @param rl_dest Destination for the result. |
| 258 | * @param rl_lhs Left hand operand. |
| 259 | * @param rl_rhs Right hand operand. |
| 260 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 261 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
| 262 | RegLocation rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 263 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 264 | /* |
| 265 | * @brief Dump a RegLocation using printf |
| 266 | * @param loc Register location to dump |
| 267 | */ |
| 268 | static void DumpRegLocation(RegLocation loc); |
| 269 | |
| 270 | /* |
| 271 | * @brief Load the Method* of a dex method into the register. |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 272 | * @param target_method The MethodReference of the method to be invoked. |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 273 | * @param type How the method will be invoked. |
| 274 | * @param register that will contain the code address. |
| 275 | * @note register will be passed to TargetReg to get physical register. |
| 276 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 277 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 278 | SpecialTargetRegister symbolic_reg); |
| 279 | |
| 280 | /* |
| 281 | * @brief Load the Class* of a Dex Class type into the register. |
| 282 | * @param type How the method will be invoked. |
| 283 | * @param register that will contain the code address. |
| 284 | * @note register will be passed to TargetReg to get physical register. |
| 285 | */ |
| 286 | void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); |
| 287 | |
| 288 | /* |
| 289 | * @brief Generate a relative call to the method that will be patched at link time. |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 290 | * @param target_method The MethodReference of the method to be invoked. |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 291 | * @param type How the method will be invoked. |
| 292 | * @returns Call instruction |
| 293 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 294 | LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 295 | |
| 296 | /* |
| 297 | * @brief Handle x86 specific literals |
| 298 | */ |
| 299 | void InstallLiteralPools(); |
| 300 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 301 | /* |
| 302 | * @brief Generate the debug_frame CFI information. |
| 303 | * @returns pointer to vector containing CFE information |
| 304 | */ |
| 305 | static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); |
| 306 | |
| 307 | /* |
| 308 | * @brief Generate the debug_frame FDE information. |
| 309 | * @returns pointer to vector containing CFE information |
| 310 | */ |
| 311 | std::vector<uint8_t>* ReturnCallFrameInformation(); |
| 312 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 313 | private: |
Vladimir Marko | 057c74a | 2013-12-03 15:20:45 +0000 | [diff] [blame] | 314 | void EmitPrefix(const X86EncodingMap* entry); |
| 315 | void EmitOpcode(const X86EncodingMap* entry); |
| 316 | void EmitPrefixAndOpcode(const X86EncodingMap* entry); |
| 317 | void EmitDisp(uint8_t base, int disp); |
| 318 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); |
| 319 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); |
| 320 | void EmitImm(const X86EncodingMap* entry, int imm); |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 321 | void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 322 | void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); |
| 323 | void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 324 | void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 325 | void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 326 | void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 327 | void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); |
| 328 | void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, |
| 329 | int scale, int disp); |
| 330 | void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, |
| 331 | uint8_t reg); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 332 | void EmitArrayImm(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, |
| 333 | int32_t imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 334 | void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); |
| 335 | void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); |
| 336 | void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 337 | void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 338 | void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, |
| 339 | int32_t imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 340 | void EmitMemRegImm(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg1, int32_t imm); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 341 | void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); |
| 342 | void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); |
| 343 | void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); |
| 344 | void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 345 | void EmitShiftMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int imm); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 346 | void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 347 | void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); |
| 348 | void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 349 | void EmitMemCond(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t condition); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 350 | |
| 351 | /** |
| 352 | * @brief Used for encoding conditional register to register operation. |
| 353 | * @param entry The entry in the encoding map for the opcode. |
| 354 | * @param reg1 The first physical register. |
| 355 | * @param reg2 The second physical register. |
| 356 | * @param condition The condition code for operation. |
| 357 | */ |
| 358 | void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); |
| 359 | |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 360 | /** |
| 361 | * @brief Used for encoding conditional register to memory operation. |
| 362 | * @param entry The entry in the encoding map for the opcode. |
| 363 | * @param reg1 The first physical register. |
| 364 | * @param base The memory base register. |
| 365 | * @param displacement The memory displacement. |
| 366 | * @param condition The condition code for operation. |
| 367 | */ |
| 368 | void EmitRegMemCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int displacement, uint8_t condition); |
| 369 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 370 | void EmitJmp(const X86EncodingMap* entry, int rel); |
| 371 | void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); |
| 372 | void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 373 | void EmitCallImmediate(const X86EncodingMap* entry, int disp); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 374 | void EmitCallThread(const X86EncodingMap* entry, int disp); |
| 375 | void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, |
| 376 | int scale, int table_or_disp); |
| 377 | void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); |
| 378 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 379 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 380 | int64_t val, ConditionCode ccode); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 381 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 382 | |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 383 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
| 384 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 385 | /* |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 386 | * @brief generate inline code for fast case of Strng.indexOf. |
| 387 | * @param info Call parameters |
| 388 | * @param zero_based 'true' if the index into the string is 0. |
| 389 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 390 | * generated. |
| 391 | */ |
| 392 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
| 393 | |
| 394 | /* |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 395 | * @brief Return the correct x86 opcode for the Dex operation |
| 396 | * @param op Dex opcode for the operation |
| 397 | * @param loc Register location of the operand |
| 398 | * @param is_high_op 'true' if this is an operation on the high word |
| 399 | * @param value Immediate value for the operation. Used for byte variants |
| 400 | * @returns the correct x86 opcode to perform the operation |
| 401 | */ |
| 402 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
| 403 | |
| 404 | /* |
| 405 | * @brief Return the correct x86 opcode for the Dex operation |
| 406 | * @param op Dex opcode for the operation |
| 407 | * @param dest location of the destination. May be register or memory. |
| 408 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 409 | * @param is_high_op 'true' if this is an operation on the high word |
| 410 | * @returns the correct x86 opcode to perform the operation |
| 411 | * @note at most one location may refer to memory |
| 412 | */ |
| 413 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 414 | bool is_high_op); |
| 415 | |
| 416 | /* |
| 417 | * @brief Is this operation a no-op for this opcode and value |
| 418 | * @param op Dex opcode for the operation |
| 419 | * @param value Immediate value for the operation. |
| 420 | * @returns 'true' if the operation will have no effect |
| 421 | */ |
| 422 | bool IsNoOp(Instruction::Code op, int32_t value); |
| 423 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 424 | /** |
| 425 | * @brief Calculate magic number and shift for a given divisor |
| 426 | * @param divisor divisor number for calculation |
| 427 | * @param magic hold calculated magic number |
| 428 | * @param shift hold calculated shift |
| 429 | */ |
| 430 | void CalculateMagicAndShift(int divisor, int& magic, int& shift); |
| 431 | |
| 432 | /* |
| 433 | * @brief Generate an integer div or rem operation. |
| 434 | * @param rl_dest Destination Location. |
| 435 | * @param rl_src1 Numerator Location. |
| 436 | * @param rl_src2 Divisor Location. |
| 437 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 438 | * @param check_zero 'true' if an exception should be generated if the divisor is 0. |
| 439 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 440 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 441 | bool is_div, bool check_zero); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 442 | |
| 443 | /* |
| 444 | * @brief Generate an integer div or rem operation by a literal. |
| 445 | * @param rl_dest Destination Location. |
| 446 | * @param rl_src Numerator Location. |
| 447 | * @param lit Divisor. |
| 448 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 449 | */ |
| 450 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 451 | |
| 452 | /* |
| 453 | * Generate code to implement long shift operations. |
| 454 | * @param opcode The DEX opcode to specify the shift type. |
| 455 | * @param rl_dest The destination. |
| 456 | * @param rl_src The value to be shifted. |
| 457 | * @param shift_amount How much to shift. |
| 458 | * @returns the RegLocation of the result. |
| 459 | */ |
| 460 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 461 | RegLocation rl_src, int shift_amount); |
| 462 | /* |
| 463 | * Generate an imul of a register by a constant or a better sequence. |
| 464 | * @param dest Destination Register. |
| 465 | * @param src Source Register. |
| 466 | * @param val Constant multiplier. |
| 467 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 468 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 469 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 470 | /* |
| 471 | * Generate an imul of a memory location by a constant or a better sequence. |
| 472 | * @param dest Destination Register. |
| 473 | * @param sreg Symbolic register. |
| 474 | * @param displacement Displacement on stack of Symbolic Register. |
| 475 | * @param val Constant multiplier. |
| 476 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 477 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 478 | |
| 479 | /* |
| 480 | * @brief Compare memory to immediate, and branch if condition true. |
| 481 | * @param cond The condition code that when true will branch to the target. |
| 482 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 483 | * supported by the architecture. |
| 484 | * @param base_reg The register holding the base address. |
| 485 | * @param offset The offset from the base. |
| 486 | * @param check_value The immediate to compare to. |
| 487 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 488 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 489 | int offset, int check_value, LIR* target); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 490 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 491 | /* |
| 492 | * Can this operation be using core registers without temporaries? |
| 493 | * @param rl_lhs Left hand operand. |
| 494 | * @param rl_rhs Right hand operand. |
| 495 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 496 | */ |
| 497 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 498 | |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 499 | /** |
| 500 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 501 | * @param rl_dest The destination of the FP. |
| 502 | * @param rl_src The source of the long. |
| 503 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 504 | */ |
| 505 | void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
| 506 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 507 | /* |
| 508 | * @brief Perform MIR analysis before compiling method. |
| 509 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 510 | */ |
| 511 | void Materialize(); |
| 512 | |
| 513 | /* |
| 514 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 515 | */ |
| 516 | void AnalyzeMIR(); |
| 517 | |
| 518 | /* |
| 519 | * @brief Analyze one basic block. |
| 520 | * @param bb Basic block to analyze. |
| 521 | */ |
| 522 | void AnalyzeBB(BasicBlock * bb); |
| 523 | |
| 524 | /* |
| 525 | * @brief Analyze one extended MIR instruction |
| 526 | * @param opcode MIR instruction opcode. |
| 527 | * @param bb Basic block containing instruction. |
| 528 | * @param mir Extended instruction to analyze. |
| 529 | */ |
| 530 | void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); |
| 531 | |
| 532 | /* |
| 533 | * @brief Analyze one MIR instruction |
| 534 | * @param opcode MIR instruction opcode. |
| 535 | * @param bb Basic block containing instruction. |
| 536 | * @param mir Instruction to analyze. |
| 537 | */ |
| 538 | void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); |
| 539 | |
| 540 | /* |
| 541 | * @brief Analyze one MIR float/double instruction |
| 542 | * @param opcode MIR instruction opcode. |
| 543 | * @param bb Basic block containing instruction. |
| 544 | * @param mir Instruction to analyze. |
| 545 | */ |
| 546 | void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); |
| 547 | |
| 548 | /* |
| 549 | * @brief Analyze one use of a double operand. |
| 550 | * @param rl_use Double RegLocation for the operand. |
| 551 | */ |
| 552 | void AnalyzeDoubleUse(RegLocation rl_use); |
| 553 | |
| 554 | // Information derived from analysis of MIR |
| 555 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 556 | // The compiler temporary for the code address of the method. |
| 557 | CompilerTemp *base_of_code_; |
| 558 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 559 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 560 | bool store_method_addr_; |
| 561 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 562 | // Have we used the stored method address? |
| 563 | bool store_method_addr_used_; |
| 564 | |
| 565 | // Instructions to remove if we didn't use the stored method address. |
| 566 | LIR* setup_method_address_[2]; |
| 567 | |
| 568 | // Instructions needing patching with Method* values. |
| 569 | GrowableArray<LIR*> method_address_insns_; |
| 570 | |
| 571 | // Instructions needing patching with Class Type* values. |
| 572 | GrowableArray<LIR*> class_type_address_insns_; |
| 573 | |
| 574 | // Instructions needing patching with PC relative code addresses. |
| 575 | GrowableArray<LIR*> call_method_insns_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 576 | |
| 577 | // Prologue decrement of stack pointer. |
| 578 | LIR* stack_decrement_; |
| 579 | |
| 580 | // Epilogue increment of stack pointer. |
| 581 | LIR* stack_increment_; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | } // namespace art |
| 585 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 586 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |