Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/quick/mir_to_lir-inl.h" |
| 19 | #include "x86_lir.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
| 23 | /* This file contains codegen for the X86 ISA */ |
| 24 | |
| 25 | LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) |
| 26 | { |
| 27 | int opcode; |
| 28 | /* must be both DOUBLE or both not DOUBLE */ |
| 29 | DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src)); |
| 30 | if (X86_DOUBLEREG(r_dest)) { |
| 31 | opcode = kX86MovsdRR; |
| 32 | } else { |
| 33 | if (X86_SINGLEREG(r_dest)) { |
| 34 | if (X86_SINGLEREG(r_src)) { |
| 35 | opcode = kX86MovssRR; |
| 36 | } else { // Fpr <- Gpr |
| 37 | opcode = kX86MovdxrRR; |
| 38 | } |
| 39 | } else { // Gpr <- Fpr |
| 40 | DCHECK(X86_SINGLEREG(r_src)); |
| 41 | opcode = kX86MovdrxRR; |
| 42 | } |
| 43 | } |
| 44 | DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); |
| 45 | LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); |
| 46 | if (r_dest == r_src) { |
| 47 | res->flags.is_nop = true; |
| 48 | } |
| 49 | return res; |
| 50 | } |
| 51 | |
| 52 | bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) |
| 53 | { |
| 54 | return true; |
| 55 | } |
| 56 | |
| 57 | bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) |
| 58 | { |
| 59 | return false; |
| 60 | } |
| 61 | |
| 62 | bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) |
| 63 | { |
| 64 | return true; |
| 65 | } |
| 66 | |
| 67 | bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) |
| 68 | { |
| 69 | return false; // TUNING |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * Load a immediate using a shortcut if possible; otherwise |
| 74 | * grab from the per-translation literal pool. If target is |
| 75 | * a high register, build constant into a low register and copy. |
| 76 | * |
| 77 | * No additional register clobbering operation performed. Use this version when |
| 78 | * 1) r_dest is freshly returned from AllocTemp or |
| 79 | * 2) The codegen is under fixed register usage |
| 80 | */ |
| 81 | LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) |
| 82 | { |
| 83 | int r_dest_save = r_dest; |
| 84 | if (X86_FPREG(r_dest)) { |
| 85 | if (value == 0) { |
| 86 | return NewLIR2(kX86XorpsRR, r_dest, r_dest); |
| 87 | } |
| 88 | DCHECK(X86_SINGLEREG(r_dest)); |
| 89 | r_dest = AllocTemp(); |
| 90 | } |
| 91 | |
| 92 | LIR *res; |
| 93 | if (value == 0) { |
| 94 | res = NewLIR2(kX86Xor32RR, r_dest, r_dest); |
| 95 | } else { |
| 96 | // Note, there is no byte immediate form of a 32 bit immediate move. |
| 97 | res = NewLIR2(kX86Mov32RI, r_dest, value); |
| 98 | } |
| 99 | |
| 100 | if (X86_FPREG(r_dest_save)) { |
| 101 | NewLIR2(kX86MovdxrRR, r_dest_save, r_dest); |
| 102 | FreeTemp(r_dest); |
| 103 | } |
| 104 | |
| 105 | return res; |
| 106 | } |
| 107 | |
| 108 | LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) |
| 109 | { |
| 110 | LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/ ); |
| 111 | res->target = target; |
| 112 | return res; |
| 113 | } |
| 114 | |
| 115 | LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) |
| 116 | { |
| 117 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, |
| 118 | X86ConditionEncoding(cc)); |
| 119 | branch->target = target; |
| 120 | return branch; |
| 121 | } |
| 122 | |
| 123 | LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) |
| 124 | { |
| 125 | X86OpCode opcode = kX86Bkpt; |
| 126 | switch (op) { |
| 127 | case kOpNeg: opcode = kX86Neg32R; break; |
| 128 | case kOpNot: opcode = kX86Not32R; break; |
| 129 | case kOpBlx: opcode = kX86CallR; break; |
| 130 | default: |
| 131 | LOG(FATAL) << "Bad case in OpReg " << op; |
| 132 | } |
| 133 | return NewLIR1(opcode, r_dest_src); |
| 134 | } |
| 135 | |
| 136 | LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) |
| 137 | { |
| 138 | X86OpCode opcode = kX86Bkpt; |
| 139 | bool byte_imm = IS_SIMM8(value); |
| 140 | DCHECK(!X86_FPREG(r_dest_src1)); |
| 141 | switch (op) { |
| 142 | case kOpLsl: opcode = kX86Sal32RI; break; |
| 143 | case kOpLsr: opcode = kX86Shr32RI; break; |
| 144 | case kOpAsr: opcode = kX86Sar32RI; break; |
| 145 | case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; |
| 146 | case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; |
| 147 | case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; |
| 148 | //case kOpSbb: opcode = kX86Sbb32RI; break; |
| 149 | case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; |
| 150 | case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; |
| 151 | case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; |
| 152 | case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; |
| 153 | case kOpMov: return LoadConstantNoClobber(r_dest_src1, value); |
| 154 | case kOpMul: |
| 155 | opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; |
| 156 | return NewLIR3(opcode, r_dest_src1, r_dest_src1, value); |
| 157 | default: |
| 158 | LOG(FATAL) << "Bad case in OpRegImm " << op; |
| 159 | } |
| 160 | return NewLIR2(opcode, r_dest_src1, value); |
| 161 | } |
| 162 | |
| 163 | LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) |
| 164 | { |
| 165 | X86OpCode opcode = kX86Nop; |
| 166 | bool src2_must_be_cx = false; |
| 167 | switch (op) { |
| 168 | // X86 unary opcodes |
| 169 | case kOpMvn: |
| 170 | OpRegCopy(r_dest_src1, r_src2); |
| 171 | return OpReg(kOpNot, r_dest_src1); |
| 172 | case kOpNeg: |
| 173 | OpRegCopy(r_dest_src1, r_src2); |
| 174 | return OpReg(kOpNeg, r_dest_src1); |
| 175 | // X86 binary opcodes |
| 176 | case kOpSub: opcode = kX86Sub32RR; break; |
| 177 | case kOpSbc: opcode = kX86Sbb32RR; break; |
| 178 | case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break; |
| 179 | case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break; |
| 180 | case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break; |
| 181 | case kOpMov: opcode = kX86Mov32RR; break; |
| 182 | case kOpCmp: opcode = kX86Cmp32RR; break; |
| 183 | case kOpAdd: opcode = kX86Add32RR; break; |
| 184 | case kOpAdc: opcode = kX86Adc32RR; break; |
| 185 | case kOpAnd: opcode = kX86And32RR; break; |
| 186 | case kOpOr: opcode = kX86Or32RR; break; |
| 187 | case kOpXor: opcode = kX86Xor32RR; break; |
| 188 | case kOp2Byte: |
| 189 | // Use shifts instead of a byte operand if the source can't be byte accessed. |
| 190 | if (r_src2 >= 4) { |
| 191 | NewLIR2(kX86Mov32RR, r_dest_src1, r_src2); |
| 192 | NewLIR2(kX86Sal32RI, r_dest_src1, 24); |
| 193 | return NewLIR2(kX86Sar32RI, r_dest_src1, 24); |
| 194 | } else { |
| 195 | opcode = kX86Movsx8RR; |
| 196 | } |
| 197 | break; |
| 198 | case kOp2Short: opcode = kX86Movsx16RR; break; |
| 199 | case kOp2Char: opcode = kX86Movzx16RR; break; |
| 200 | case kOpMul: opcode = kX86Imul32RR; break; |
| 201 | default: |
| 202 | LOG(FATAL) << "Bad case in OpRegReg " << op; |
| 203 | break; |
| 204 | } |
| 205 | CHECK(!src2_must_be_cx || r_src2 == rCX); |
| 206 | return NewLIR2(opcode, r_dest_src1, r_src2); |
| 207 | } |
| 208 | |
| 209 | LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, |
| 210 | int offset) |
| 211 | { |
| 212 | X86OpCode opcode = kX86Nop; |
| 213 | switch (op) { |
| 214 | // X86 binary opcodes |
| 215 | case kOpSub: opcode = kX86Sub32RM; break; |
| 216 | case kOpMov: opcode = kX86Mov32RM; break; |
| 217 | case kOpCmp: opcode = kX86Cmp32RM; break; |
| 218 | case kOpAdd: opcode = kX86Add32RM; break; |
| 219 | case kOpAnd: opcode = kX86And32RM; break; |
| 220 | case kOpOr: opcode = kX86Or32RM; break; |
| 221 | case kOpXor: opcode = kX86Xor32RM; break; |
| 222 | case kOp2Byte: opcode = kX86Movsx8RM; break; |
| 223 | case kOp2Short: opcode = kX86Movsx16RM; break; |
| 224 | case kOp2Char: opcode = kX86Movzx16RM; break; |
| 225 | case kOpMul: |
| 226 | default: |
| 227 | LOG(FATAL) << "Bad case in OpRegMem " << op; |
| 228 | break; |
| 229 | } |
| 230 | return NewLIR3(opcode, r_dest, rBase, offset); |
| 231 | } |
| 232 | |
| 233 | LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, |
| 234 | int r_src2) |
| 235 | { |
| 236 | if (r_dest != r_src1 && r_dest != r_src2) { |
| 237 | if (op == kOpAdd) { // lea special case, except can't encode rbp as base |
| 238 | if (r_src1 == r_src2) { |
| 239 | OpRegCopy(r_dest, r_src1); |
| 240 | return OpRegImm(kOpLsl, r_dest, 1); |
| 241 | } else if (r_src1 != rBP) { |
| 242 | return NewLIR5(kX86Lea32RA, r_dest, r_src1 /* base */, |
| 243 | r_src2 /* index */, 0 /* scale */, 0 /* disp */); |
| 244 | } else { |
| 245 | return NewLIR5(kX86Lea32RA, r_dest, r_src2 /* base */, |
| 246 | r_src1 /* index */, 0 /* scale */, 0 /* disp */); |
| 247 | } |
| 248 | } else { |
| 249 | OpRegCopy(r_dest, r_src1); |
| 250 | return OpRegReg(op, r_dest, r_src2); |
| 251 | } |
| 252 | } else if (r_dest == r_src1) { |
| 253 | return OpRegReg(op, r_dest, r_src2); |
| 254 | } else { // r_dest == r_src2 |
| 255 | switch (op) { |
| 256 | case kOpSub: // non-commutative |
| 257 | OpReg(kOpNeg, r_dest); |
| 258 | op = kOpAdd; |
| 259 | break; |
| 260 | case kOpSbc: |
| 261 | case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { |
| 262 | int t_reg = AllocTemp(); |
| 263 | OpRegCopy(t_reg, r_src1); |
| 264 | OpRegReg(op, t_reg, r_src2); |
| 265 | LIR* res = OpRegCopy(r_dest, t_reg); |
| 266 | FreeTemp(t_reg); |
| 267 | return res; |
| 268 | } |
| 269 | case kOpAdd: // commutative |
| 270 | case kOpOr: |
| 271 | case kOpAdc: |
| 272 | case kOpAnd: |
| 273 | case kOpXor: |
| 274 | break; |
| 275 | default: |
| 276 | LOG(FATAL) << "Bad case in OpRegRegReg " << op; |
| 277 | } |
| 278 | return OpRegReg(op, r_dest, r_src1); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src, |
| 283 | int value) |
| 284 | { |
| 285 | if (op == kOpMul) { |
| 286 | X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; |
| 287 | return NewLIR3(opcode, r_dest, r_src, value); |
| 288 | } else if (op == kOpAnd) { |
| 289 | if (value == 0xFF && r_src < 4) { |
| 290 | return NewLIR2(kX86Movzx8RR, r_dest, r_src); |
| 291 | } else if (value == 0xFFFF) { |
| 292 | return NewLIR2(kX86Movzx16RR, r_dest, r_src); |
| 293 | } |
| 294 | } |
| 295 | if (r_dest != r_src) { |
| 296 | if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case |
| 297 | // TODO: fix bug in LEA encoding when disp == 0 |
| 298 | return NewLIR5(kX86Lea32RA, r_dest, r5sib_no_base /* base */, |
| 299 | r_src /* index */, value /* scale */, 0 /* disp */); |
| 300 | } else if (op == kOpAdd) { // lea add special case |
| 301 | return NewLIR5(kX86Lea32RA, r_dest, r_src /* base */, |
| 302 | r4sib_no_index /* index */, 0 /* scale */, value /* disp */); |
| 303 | } |
| 304 | OpRegCopy(r_dest, r_src); |
| 305 | } |
| 306 | return OpRegImm(op, r_dest, value); |
| 307 | } |
| 308 | |
| 309 | LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset) |
| 310 | { |
| 311 | X86OpCode opcode = kX86Bkpt; |
| 312 | switch (op) { |
| 313 | case kOpBlx: opcode = kX86CallT; break; |
| 314 | default: |
| 315 | LOG(FATAL) << "Bad opcode: " << op; |
| 316 | break; |
| 317 | } |
| 318 | return NewLIR1(opcode, thread_offset); |
| 319 | } |
| 320 | |
| 321 | LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) |
| 322 | { |
| 323 | X86OpCode opcode = kX86Bkpt; |
| 324 | switch (op) { |
| 325 | case kOpBlx: opcode = kX86CallM; break; |
| 326 | default: |
| 327 | LOG(FATAL) << "Bad opcode: " << op; |
| 328 | break; |
| 329 | } |
| 330 | return NewLIR2(opcode, rBase, disp); |
| 331 | } |
| 332 | |
| 333 | LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) |
| 334 | { |
| 335 | int32_t val_lo = Low32Bits(value); |
| 336 | int32_t val_hi = High32Bits(value); |
| 337 | LIR *res; |
| 338 | if (X86_FPREG(r_dest_lo)) { |
| 339 | DCHECK(X86_FPREG(r_dest_hi)); // ignore r_dest_hi |
| 340 | if (value == 0) { |
| 341 | return NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo); |
| 342 | } else { |
| 343 | if (val_lo == 0) { |
| 344 | res = NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo); |
| 345 | } else { |
| 346 | res = LoadConstantNoClobber(r_dest_lo, val_lo); |
| 347 | } |
| 348 | if (val_hi != 0) { |
| 349 | LoadConstantNoClobber(r_dest_hi, val_hi); |
| 350 | NewLIR2(kX86PsllqRI, r_dest_hi, 32); |
| 351 | NewLIR2(kX86OrpsRR, r_dest_lo, r_dest_hi); |
| 352 | } |
| 353 | } |
| 354 | } else { |
| 355 | res = LoadConstantNoClobber(r_dest_lo, val_lo); |
| 356 | LoadConstantNoClobber(r_dest_hi, val_hi); |
| 357 | } |
| 358 | return res; |
| 359 | } |
| 360 | |
| 361 | LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, |
| 362 | int displacement, int r_dest, int r_dest_hi, OpSize size, |
| 363 | int s_reg) { |
| 364 | LIR *load = NULL; |
| 365 | LIR *load2 = NULL; |
| 366 | bool is_array = r_index != INVALID_REG; |
| 367 | bool pair = false; |
| 368 | bool is64bit = false; |
| 369 | X86OpCode opcode = kX86Nop; |
| 370 | switch (size) { |
| 371 | case kLong: |
| 372 | case kDouble: |
| 373 | is64bit = true; |
| 374 | if (X86_FPREG(r_dest)) { |
| 375 | opcode = is_array ? kX86MovsdRA : kX86MovsdRM; |
| 376 | if (X86_SINGLEREG(r_dest)) { |
| 377 | DCHECK(X86_FPREG(r_dest_hi)); |
| 378 | DCHECK_EQ(r_dest, (r_dest_hi - 1)); |
| 379 | r_dest = S2d(r_dest, r_dest_hi); |
| 380 | } |
| 381 | r_dest_hi = r_dest + 1; |
| 382 | } else { |
| 383 | pair = true; |
| 384 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
| 385 | } |
| 386 | // TODO: double store is to unaligned address |
| 387 | DCHECK_EQ((displacement & 0x3), 0); |
| 388 | break; |
| 389 | case kWord: |
| 390 | case kSingle: |
| 391 | opcode = is_array ? kX86Mov32RA : kX86Mov32RM; |
| 392 | if (X86_FPREG(r_dest)) { |
| 393 | opcode = is_array ? kX86MovssRA : kX86MovssRM; |
| 394 | DCHECK(X86_SINGLEREG(r_dest)); |
| 395 | } |
| 396 | DCHECK_EQ((displacement & 0x3), 0); |
| 397 | break; |
| 398 | case kUnsignedHalf: |
| 399 | opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; |
| 400 | DCHECK_EQ((displacement & 0x1), 0); |
| 401 | break; |
| 402 | case kSignedHalf: |
| 403 | opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; |
| 404 | DCHECK_EQ((displacement & 0x1), 0); |
| 405 | break; |
| 406 | case kUnsignedByte: |
| 407 | opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; |
| 408 | break; |
| 409 | case kSignedByte: |
| 410 | opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; |
| 411 | break; |
| 412 | default: |
| 413 | LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; |
| 414 | } |
| 415 | |
| 416 | if (!is_array) { |
| 417 | if (!pair) { |
| 418 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 419 | } else { |
| 420 | if (rBase == r_dest) { |
| 421 | load2 = NewLIR3(opcode, r_dest_hi, rBase, |
| 422 | displacement + HIWORD_OFFSET); |
| 423 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 424 | } else { |
| 425 | load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); |
| 426 | load2 = NewLIR3(opcode, r_dest_hi, rBase, |
| 427 | displacement + HIWORD_OFFSET); |
| 428 | } |
| 429 | } |
| 430 | if (rBase == rX86_SP) { |
| 431 | AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 432 | true /* is_load */, is64bit); |
| 433 | if (pair) { |
| 434 | AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, |
| 435 | true /* is_load */, is64bit); |
| 436 | } |
| 437 | } |
| 438 | } else { |
| 439 | if (!pair) { |
| 440 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 441 | displacement + LOWORD_OFFSET); |
| 442 | } else { |
| 443 | if (rBase == r_dest) { |
| 444 | load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale, |
| 445 | displacement + HIWORD_OFFSET); |
| 446 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 447 | displacement + LOWORD_OFFSET); |
| 448 | } else { |
| 449 | load = NewLIR5(opcode, r_dest, rBase, r_index, scale, |
| 450 | displacement + LOWORD_OFFSET); |
| 451 | load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale, |
| 452 | displacement + HIWORD_OFFSET); |
| 453 | } |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | return load; |
| 458 | } |
| 459 | |
| 460 | /* Load value from base + scaled index. */ |
| 461 | LIR* X86Mir2Lir::LoadBaseIndexed(int rBase, |
| 462 | int r_index, int r_dest, int scale, OpSize size) { |
| 463 | return LoadBaseIndexedDisp(rBase, r_index, scale, 0, |
| 464 | r_dest, INVALID_REG, size, INVALID_SREG); |
| 465 | } |
| 466 | |
| 467 | LIR* X86Mir2Lir::LoadBaseDisp(int rBase, int displacement, |
| 468 | int r_dest, OpSize size, int s_reg) { |
| 469 | return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 470 | r_dest, INVALID_REG, size, s_reg); |
| 471 | } |
| 472 | |
| 473 | LIR* X86Mir2Lir::LoadBaseDispWide(int rBase, int displacement, |
| 474 | int r_dest_lo, int r_dest_hi, int s_reg) { |
| 475 | return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 476 | r_dest_lo, r_dest_hi, kLong, s_reg); |
| 477 | } |
| 478 | |
| 479 | LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, |
| 480 | int displacement, int r_src, int r_src_hi, OpSize size, |
| 481 | int s_reg) { |
| 482 | LIR *store = NULL; |
| 483 | LIR *store2 = NULL; |
| 484 | bool is_array = r_index != INVALID_REG; |
| 485 | bool pair = false; |
| 486 | bool is64bit = false; |
| 487 | X86OpCode opcode = kX86Nop; |
| 488 | switch (size) { |
| 489 | case kLong: |
| 490 | case kDouble: |
| 491 | is64bit = true; |
| 492 | if (X86_FPREG(r_src)) { |
| 493 | opcode = is_array ? kX86MovsdAR : kX86MovsdMR; |
| 494 | if (X86_SINGLEREG(r_src)) { |
| 495 | DCHECK(X86_FPREG(r_src_hi)); |
| 496 | DCHECK_EQ(r_src, (r_src_hi - 1)); |
| 497 | r_src = S2d(r_src, r_src_hi); |
| 498 | } |
| 499 | r_src_hi = r_src + 1; |
| 500 | } else { |
| 501 | pair = true; |
| 502 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
| 503 | } |
| 504 | // TODO: double store is to unaligned address |
| 505 | DCHECK_EQ((displacement & 0x3), 0); |
| 506 | break; |
| 507 | case kWord: |
| 508 | case kSingle: |
| 509 | opcode = is_array ? kX86Mov32AR : kX86Mov32MR; |
| 510 | if (X86_FPREG(r_src)) { |
| 511 | opcode = is_array ? kX86MovssAR : kX86MovssMR; |
| 512 | DCHECK(X86_SINGLEREG(r_src)); |
| 513 | } |
| 514 | DCHECK_EQ((displacement & 0x3), 0); |
| 515 | break; |
| 516 | case kUnsignedHalf: |
| 517 | case kSignedHalf: |
| 518 | opcode = is_array ? kX86Mov16AR : kX86Mov16MR; |
| 519 | DCHECK_EQ((displacement & 0x1), 0); |
| 520 | break; |
| 521 | case kUnsignedByte: |
| 522 | case kSignedByte: |
| 523 | opcode = is_array ? kX86Mov8AR : kX86Mov8MR; |
| 524 | break; |
| 525 | default: |
| 526 | LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; |
| 527 | } |
| 528 | |
| 529 | if (!is_array) { |
| 530 | if (!pair) { |
| 531 | store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src); |
| 532 | } else { |
| 533 | store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src); |
| 534 | store2 = NewLIR3(opcode, rBase, displacement + HIWORD_OFFSET, r_src_hi); |
| 535 | } |
| 536 | if (rBase == rX86_SP) { |
| 537 | AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, |
| 538 | false /* is_load */, is64bit); |
| 539 | if (pair) { |
| 540 | AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, |
| 541 | false /* is_load */, is64bit); |
| 542 | } |
| 543 | } |
| 544 | } else { |
| 545 | if (!pair) { |
| 546 | store = NewLIR5(opcode, rBase, r_index, scale, |
| 547 | displacement + LOWORD_OFFSET, r_src); |
| 548 | } else { |
| 549 | store = NewLIR5(opcode, rBase, r_index, scale, |
| 550 | displacement + LOWORD_OFFSET, r_src); |
| 551 | store2 = NewLIR5(opcode, rBase, r_index, scale, |
| 552 | displacement + HIWORD_OFFSET, r_src_hi); |
| 553 | } |
| 554 | } |
| 555 | |
| 556 | return store; |
| 557 | } |
| 558 | |
| 559 | /* store value base base + scaled index. */ |
| 560 | LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, |
| 561 | int scale, OpSize size) |
| 562 | { |
| 563 | return StoreBaseIndexedDisp(rBase, r_index, scale, 0, |
| 564 | r_src, INVALID_REG, size, INVALID_SREG); |
| 565 | } |
| 566 | |
| 567 | LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement, |
| 568 | int r_src, OpSize size) |
| 569 | { |
| 570 | return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, |
| 571 | displacement, r_src, INVALID_REG, size, |
| 572 | INVALID_SREG); |
| 573 | } |
| 574 | |
| 575 | LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement, |
| 576 | int r_src_lo, int r_src_hi) |
| 577 | { |
| 578 | return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement, |
| 579 | r_src_lo, r_src_hi, kLong, INVALID_SREG); |
| 580 | } |
| 581 | |
| 582 | } // namespace art |