Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_arm64.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
| 21 | #include <string> |
| 22 | |
| 23 | #include "dex/compiler_internals.h" |
| 24 | #include "dex/quick/mir_to_lir-inl.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | // TODO: rework this when c++11 support allows. |
| 29 | static const RegStorage core_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 30 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, |
| 31 | rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, |
| 32 | rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, |
| 33 | rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 34 | static const RegStorage sp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 35 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
| 36 | rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, |
| 37 | rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, |
| 38 | rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 39 | static const RegStorage dp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 40 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, |
| 41 | rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 42 | static const RegStorage reserved_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 43 | {rs_rA64_SUSPEND, rs_rA64_SELF, rs_rA64_SP, rs_rA64_LR}; |
| 44 | static const RegStorage core_temps_arr[] = |
| 45 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x12}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 46 | static const RegStorage sp_temps_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 47 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
| 48 | rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 49 | static const RegStorage dp_temps_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 50 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 51 | |
| 52 | static const std::vector<RegStorage> core_regs(core_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 53 | core_regs_arr + arraysize(core_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 54 | static const std::vector<RegStorage> sp_regs(sp_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 55 | sp_regs_arr + arraysize(sp_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 56 | static const std::vector<RegStorage> dp_regs(dp_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 57 | dp_regs_arr + arraysize(dp_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 58 | static const std::vector<RegStorage> reserved_regs(reserved_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 59 | reserved_regs_arr + arraysize(reserved_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 60 | static const std::vector<RegStorage> core_temps(core_temps_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 61 | core_temps_arr + arraysize(core_temps_arr)); |
| 62 | static const std::vector<RegStorage> sp_temps(sp_temps_arr, sp_temps_arr + arraysize(sp_temps_arr)); |
| 63 | static const std::vector<RegStorage> dp_temps(dp_temps_arr, dp_temps_arr + arraysize(dp_temps_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 64 | |
| 65 | RegLocation Arm64Mir2Lir::LocCReturn() { |
| 66 | return arm_loc_c_return; |
| 67 | } |
| 68 | |
| 69 | RegLocation Arm64Mir2Lir::LocCReturnWide() { |
| 70 | return arm_loc_c_return_wide; |
| 71 | } |
| 72 | |
| 73 | RegLocation Arm64Mir2Lir::LocCReturnFloat() { |
| 74 | return arm_loc_c_return_float; |
| 75 | } |
| 76 | |
| 77 | RegLocation Arm64Mir2Lir::LocCReturnDouble() { |
| 78 | return arm_loc_c_return_double; |
| 79 | } |
| 80 | |
| 81 | // Return a target-dependent special register. |
| 82 | RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 83 | // TODO(Arm64): this function doesn't work for hard-float ABI. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 84 | RegStorage res_reg = RegStorage::InvalidReg(); |
| 85 | switch (reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 86 | case kSelf: res_reg = rs_rA64_SELF; break; |
| 87 | case kSuspend: res_reg = rs_rA64_SUSPEND; break; |
| 88 | case kLr: res_reg = rs_rA64_LR; break; |
| 89 | case kPc: res_reg = RegStorage::InvalidReg(); break; |
| 90 | case kSp: res_reg = rs_rA64_SP; break; |
| 91 | case kArg0: res_reg = rs_x0; break; |
| 92 | case kArg1: res_reg = rs_x1; break; |
| 93 | case kArg2: res_reg = rs_x2; break; |
| 94 | case kArg3: res_reg = rs_x3; break; |
| 95 | case kFArg0: res_reg = rs_f0; break; |
| 96 | case kFArg1: res_reg = rs_f1; break; |
| 97 | case kFArg2: res_reg = rs_f2; break; |
| 98 | case kFArg3: res_reg = rs_f3; break; |
| 99 | case kRet0: res_reg = rs_x0; break; |
| 100 | case kRet1: res_reg = rs_x0; break; |
| 101 | case kInvokeTgt: res_reg = rs_rA64_LR; break; |
| 102 | case kHiddenArg: res_reg = rs_x12; break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 103 | case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; |
| 104 | case kCount: res_reg = RegStorage::InvalidReg(); break; |
| 105 | } |
| 106 | return res_reg; |
| 107 | } |
| 108 | |
| 109 | RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 110 | return RegStorage::InvalidReg(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 114 | * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 115 | */ |
| 116 | uint64_t Arm64Mir2Lir::GetRegMaskCommon(RegStorage reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 117 | // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. |
| 118 | |
| 119 | int reg_raw = reg.GetRawBits(); |
| 120 | // Check if the shape mask is zero (i.e. invalid). |
| 121 | if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { |
| 122 | // The zero register is not a true register. It is just an immediate zero. |
| 123 | return 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 124 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 125 | |
| 126 | return UINT64_C(1) << (reg_raw & RegStorage::kRegTypeMask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | uint64_t Arm64Mir2Lir::GetPCUseDefEncoding() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 130 | LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for Arm64"; |
| 131 | return 0ULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 132 | } |
| 133 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 134 | // Arm64 specific setup. TODO: inline?: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 135 | void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 136 | DCHECK_EQ(cu_->instruction_set, kArm64); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 137 | DCHECK(!lir->flags.use_def_invalid); |
| 138 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 139 | // These flags are somewhat uncommon - bypass if we can. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 140 | if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 141 | if (flags & REG_DEF_SP) { |
| 142 | lir->u.m.def_mask |= ENCODE_ARM_REG_SP; |
| 143 | } |
| 144 | |
| 145 | if (flags & REG_USE_SP) { |
| 146 | lir->u.m.use_mask |= ENCODE_ARM_REG_SP; |
| 147 | } |
| 148 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 149 | if (flags & REG_DEF_LR) { |
| 150 | lir->u.m.def_mask |= ENCODE_ARM_REG_LR; |
| 151 | } |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { |
| 156 | ArmConditionCode res; |
| 157 | switch (ccode) { |
| 158 | case kCondEq: res = kArmCondEq; break; |
| 159 | case kCondNe: res = kArmCondNe; break; |
| 160 | case kCondCs: res = kArmCondCs; break; |
| 161 | case kCondCc: res = kArmCondCc; break; |
| 162 | case kCondUlt: res = kArmCondCc; break; |
| 163 | case kCondUge: res = kArmCondCs; break; |
| 164 | case kCondMi: res = kArmCondMi; break; |
| 165 | case kCondPl: res = kArmCondPl; break; |
| 166 | case kCondVs: res = kArmCondVs; break; |
| 167 | case kCondVc: res = kArmCondVc; break; |
| 168 | case kCondHi: res = kArmCondHi; break; |
| 169 | case kCondLs: res = kArmCondLs; break; |
| 170 | case kCondGe: res = kArmCondGe; break; |
| 171 | case kCondLt: res = kArmCondLt; break; |
| 172 | case kCondGt: res = kArmCondGt; break; |
| 173 | case kCondLe: res = kArmCondLe; break; |
| 174 | case kCondAl: res = kArmCondAl; break; |
| 175 | case kCondNv: res = kArmCondNv; break; |
| 176 | default: |
| 177 | LOG(FATAL) << "Bad condition code " << ccode; |
| 178 | res = static_cast<ArmConditionCode>(0); // Quiet gcc |
| 179 | } |
| 180 | return res; |
| 181 | } |
| 182 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 183 | static const char *shift_names[4] = { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 184 | "lsl", |
| 185 | "lsr", |
| 186 | "asr", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 187 | "ror" |
| 188 | }; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 189 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 190 | static const char* extend_names[8] = { |
| 191 | "uxtb", |
| 192 | "uxth", |
| 193 | "uxtw", |
| 194 | "uxtx", |
| 195 | "sxtb", |
| 196 | "sxth", |
| 197 | "sxtw", |
| 198 | "sxtx", |
| 199 | }; |
| 200 | |
| 201 | /* Decode and print a register extension (e.g. ", uxtb #1") */ |
| 202 | static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { |
| 203 | if ((operand & (1 << 6)) == 0) { |
| 204 | const char *shift_name = shift_names[(operand >> 7) & 0x3]; |
| 205 | int amount = operand & 0x3f; |
| 206 | snprintf(buf, buf_size, ", %s #%d", shift_name, amount); |
| 207 | } else { |
| 208 | const char *extend_name = extend_names[(operand >> 3) & 0x7]; |
| 209 | int amount = operand & 0x7; |
| 210 | if (amount == 0) { |
| 211 | snprintf(buf, buf_size, ", %s", extend_name); |
| 212 | } else { |
| 213 | snprintf(buf, buf_size, ", %s #%d", extend_name, amount); |
| 214 | } |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | #define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1)) |
| 219 | |
| 220 | static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { |
| 221 | DCHECK_LE(width, 64U); |
| 222 | rotate &= 63; |
| 223 | value = value & BIT_MASK(width); |
| 224 | return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate); |
| 225 | } |
| 226 | |
| 227 | static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { |
| 228 | unsigned i; |
| 229 | unsigned reg_size = (is_wide) ? 64 : 32; |
| 230 | uint64_t result = value & BIT_MASK(width); |
| 231 | DCHECK_NE(width, reg_size); |
| 232 | for (i = width; i < reg_size; i *= 2) { |
| 233 | result |= (result << i); |
| 234 | } |
| 235 | DCHECK_EQ(i, reg_size); |
| 236 | return result; |
| 237 | } |
| 238 | |
| 239 | /** |
| 240 | * @brief Decode an immediate in the form required by logical instructions. |
| 241 | * |
| 242 | * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. |
| 243 | * @param value The encoded logical immediates that is to be decoded. |
| 244 | * @return The decoded logical immediate. |
| 245 | * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). |
| 246 | */ |
| 247 | uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { |
| 248 | unsigned n = (value >> 12) & 0x01; |
| 249 | unsigned imm_r = (value >> 6) & 0x3f; |
| 250 | unsigned imm_s = (value >> 0) & 0x3f; |
| 251 | |
| 252 | // An integer is constructed from the n, imm_s and imm_r bits according to |
| 253 | // the following table: |
| 254 | // |
| 255 | // N imms immr size S R |
| 256 | // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 257 | // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
| 258 | // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) |
| 259 | // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) |
| 260 | // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) |
| 261 | // 0 11110s xxxxxr 2 UInt(s) UInt(r) |
| 262 | // (s bits must not be all set) |
| 263 | // |
| 264 | // A pattern is constructed of size bits, where the least significant S+1 |
| 265 | // bits are set. The pattern is rotated right by R, and repeated across a |
| 266 | // 32 or 64-bit value, depending on destination register width. |
| 267 | |
| 268 | if (n == 1) { |
| 269 | DCHECK_NE(imm_s, 0x3fU); |
| 270 | uint64_t bits = BIT_MASK(imm_s + 1); |
| 271 | return RotateRight(bits, imm_r, 64); |
| 272 | } else { |
| 273 | DCHECK_NE((imm_s >> 1), 0x1fU); |
| 274 | for (unsigned width = 0x20; width >= 0x2; width >>= 1) { |
| 275 | if ((imm_s & width) == 0) { |
| 276 | unsigned mask = (unsigned)(width - 1); |
| 277 | DCHECK_NE((imm_s & mask), mask); |
| 278 | uint64_t bits = BIT_MASK((imm_s & mask) + 1); |
| 279 | return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 280 | } |
| 281 | } |
| 282 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 283 | return 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 284 | } |
| 285 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 286 | /** |
| 287 | * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). |
| 288 | */ |
| 289 | static float DecodeImmSingle(uint8_t small_float) { |
| 290 | int mantissa = (small_float & 0x0f) + 0x10; |
| 291 | int sign = ((small_float & 0x80) == 0) ? 1 : -1; |
| 292 | float signed_mantissa = static_cast<float>(sign*mantissa); |
| 293 | int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; |
| 294 | return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 295 | } |
| 296 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 297 | static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
| 298 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 299 | /* |
| 300 | * Interpret a format string and build a string no longer than size |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 301 | * See format key in assemble_arm64.cc. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 302 | */ |
| 303 | std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { |
| 304 | std::string buf; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 305 | const char* fmt_end = &fmt[strlen(fmt)]; |
| 306 | char tbuf[256]; |
| 307 | const char* name; |
| 308 | char nc; |
| 309 | while (fmt < fmt_end) { |
| 310 | int operand; |
| 311 | if (*fmt == '!') { |
| 312 | fmt++; |
| 313 | DCHECK_LT(fmt, fmt_end); |
| 314 | nc = *fmt++; |
| 315 | if (nc == '!') { |
| 316 | strcpy(tbuf, "!"); |
| 317 | } else { |
| 318 | DCHECK_LT(fmt, fmt_end); |
| 319 | DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); |
| 320 | operand = lir->operands[nc-'0']; |
| 321 | switch (*fmt++) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 322 | case 'e': { |
| 323 | // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and |
| 324 | // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" |
| 325 | int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : |
| 326 | EncodeExtend(kA64Uxtw, 0)); |
| 327 | if (LIKELY(operand == omittable)) { |
| 328 | strcpy(tbuf, ""); |
| 329 | } else { |
| 330 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
| 331 | } |
| 332 | } |
| 333 | break; |
| 334 | case 'o': |
| 335 | // Omit ", lsl #0" |
| 336 | if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 337 | strcpy(tbuf, ""); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 338 | } else { |
| 339 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 340 | } |
| 341 | break; |
| 342 | case 'B': |
| 343 | switch (operand) { |
| 344 | case kSY: |
| 345 | name = "sy"; |
| 346 | break; |
| 347 | case kST: |
| 348 | name = "st"; |
| 349 | break; |
| 350 | case kISH: |
| 351 | name = "ish"; |
| 352 | break; |
| 353 | case kISHST: |
| 354 | name = "ishst"; |
| 355 | break; |
| 356 | case kNSH: |
| 357 | name = "nsh"; |
| 358 | break; |
| 359 | case kNSHST: |
| 360 | name = "shst"; |
| 361 | break; |
| 362 | default: |
| 363 | name = "DecodeError2"; |
| 364 | break; |
| 365 | } |
| 366 | strcpy(tbuf, name); |
| 367 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 368 | case 's': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 369 | snprintf(tbuf, arraysize(tbuf), "s%d", operand & ARM_FP_REG_MASK); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 370 | break; |
| 371 | case 'S': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 372 | snprintf(tbuf, arraysize(tbuf), "d%d", operand & ARM_FP_REG_MASK); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 373 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 374 | case 'f': |
| 375 | snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', |
| 376 | operand & ARM_FP_REG_MASK); |
| 377 | break; |
| 378 | case 'l': { |
| 379 | bool is_wide = IS_WIDE(lir->opcode); |
| 380 | uint64_t imm = DecodeLogicalImmediate(is_wide, operand); |
| 381 | snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); |
| 382 | } |
| 383 | break; |
| 384 | case 'I': |
| 385 | snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 386 | break; |
| 387 | case 'M': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 388 | if (LIKELY(operand == 0)) |
| 389 | strcpy(tbuf, ""); |
| 390 | else |
| 391 | snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); |
| 392 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 393 | case 'd': |
| 394 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
| 395 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 396 | case 'w': |
| 397 | if (LIKELY(operand != rwzr)) |
| 398 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 399 | else |
| 400 | strcpy(tbuf, "wzr"); |
| 401 | break; |
| 402 | case 'W': |
| 403 | if (LIKELY(operand != rwsp)) |
| 404 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 405 | else |
| 406 | strcpy(tbuf, "wsp"); |
| 407 | break; |
| 408 | case 'x': |
| 409 | if (LIKELY(operand != rxzr)) |
| 410 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 411 | else |
| 412 | strcpy(tbuf, "xzr"); |
| 413 | break; |
| 414 | case 'X': |
| 415 | if (LIKELY(operand != rsp)) |
| 416 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 417 | else |
| 418 | strcpy(tbuf, "sp"); |
| 419 | break; |
| 420 | case 'D': |
| 421 | snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 422 | break; |
| 423 | case 'E': |
| 424 | snprintf(tbuf, arraysize(tbuf), "%d", operand*4); |
| 425 | break; |
| 426 | case 'F': |
| 427 | snprintf(tbuf, arraysize(tbuf), "%d", operand*2); |
| 428 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 429 | case 'G': |
| 430 | if (LIKELY(operand == 0)) |
| 431 | strcpy(tbuf, ""); |
| 432 | else |
| 433 | strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); |
| 434 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 435 | case 'c': |
| 436 | strcpy(tbuf, cc_names[operand]); |
| 437 | break; |
| 438 | case 't': |
| 439 | snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 440 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 441 | lir->target); |
| 442 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 443 | case 'r': { |
| 444 | bool is_wide = IS_WIDE(lir->opcode); |
| 445 | if (LIKELY(operand != rwzr && operand != rxzr)) { |
| 446 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 447 | operand & RegStorage::kRegNumMask); |
| 448 | } else { |
| 449 | strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); |
| 450 | } |
| 451 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 452 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 453 | case 'R': { |
| 454 | bool is_wide = IS_WIDE(lir->opcode); |
| 455 | if (LIKELY(operand != rwsp || operand != rsp)) { |
| 456 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 457 | operand & RegStorage::kRegNumMask); |
| 458 | } else { |
| 459 | strcpy(tbuf, (is_wide) ? "sp" : "wsp"); |
| 460 | } |
| 461 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 462 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 463 | case 'p': |
| 464 | snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, |
| 465 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 466 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 467 | case 'T': |
| 468 | if (LIKELY(operand == 0)) |
| 469 | strcpy(tbuf, ""); |
| 470 | else if (operand == 1) |
| 471 | strcpy(tbuf, ", lsl #12"); |
| 472 | else |
| 473 | strcpy(tbuf, ", DecodeError3"); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 474 | break; |
| 475 | default: |
| 476 | strcpy(tbuf, "DecodeError1"); |
| 477 | break; |
| 478 | } |
| 479 | buf += tbuf; |
| 480 | } |
| 481 | } else { |
| 482 | buf += *fmt++; |
| 483 | } |
| 484 | } |
| 485 | return buf; |
| 486 | } |
| 487 | |
| 488 | void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) { |
| 489 | char buf[256]; |
| 490 | buf[0] = 0; |
| 491 | |
| 492 | if (mask == ENCODE_ALL) { |
| 493 | strcpy(buf, "all"); |
| 494 | } else { |
| 495 | char num[8]; |
| 496 | int i; |
| 497 | |
| 498 | for (i = 0; i < kArmRegEnd; i++) { |
| 499 | if (mask & (1ULL << i)) { |
| 500 | snprintf(num, arraysize(num), "%d ", i); |
| 501 | strcat(buf, num); |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | if (mask & ENCODE_CCODE) { |
| 506 | strcat(buf, "cc "); |
| 507 | } |
| 508 | if (mask & ENCODE_FP_STATUS) { |
| 509 | strcat(buf, "fpcc "); |
| 510 | } |
| 511 | |
| 512 | /* Memory bits */ |
| 513 | if (arm_lir && (mask & ENCODE_DALVIK_REG)) { |
| 514 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 515 | DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), |
| 516 | DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); |
| 517 | } |
| 518 | if (mask & ENCODE_LITERAL) { |
| 519 | strcat(buf, "lit "); |
| 520 | } |
| 521 | |
| 522 | if (mask & ENCODE_HEAP_REF) { |
| 523 | strcat(buf, "heap "); |
| 524 | } |
| 525 | if (mask & ENCODE_MUST_NOT_ALIAS) { |
| 526 | strcat(buf, "noalias "); |
| 527 | } |
| 528 | } |
| 529 | if (buf[0]) { |
| 530 | LOG(INFO) << prefix << ": " << buf; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 535 | return (lir->opcode == kA64B1t); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
| 539 | : Mir2Lir(cu, mir_graph, arena) { |
| 540 | // Sanity check - make sure encoding map lines up. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 541 | for (int i = 0; i < kA64Last; i++) { |
| 542 | if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 543 | LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name |
| 544 | << " is wrong: expecting " << i << ", seeing " |
| 545 | << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); |
| 546 | } |
| 547 | } |
| 548 | } |
| 549 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 550 | Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 551 | ArenaAllocator* const arena) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 552 | return new Arm64Mir2Lir(cu, mir_graph, arena); |
| 553 | } |
| 554 | |
| 555 | // Alloc a pair of core registers, or a double. |
| 556 | RegStorage Arm64Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { |
| 557 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { |
| 558 | return AllocTempDouble(); |
| 559 | } else { |
| 560 | RegStorage low_reg = AllocTemp(); |
| 561 | RegStorage high_reg = AllocTemp(); |
| 562 | return RegStorage::MakeRegPair(low_reg, high_reg); |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | RegStorage Arm64Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { |
| 567 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) |
| 568 | return AllocTempSingle(); |
| 569 | return AllocTemp(); |
| 570 | } |
| 571 | |
| 572 | void Arm64Mir2Lir::CompilerInitializeRegAlloc() { |
| 573 | reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, sp_regs, dp_regs, reserved_regs, |
| 574 | core_temps, sp_temps, dp_temps); |
| 575 | |
| 576 | // Target-specific adjustments. |
| 577 | |
| 578 | // Alias single precision floats to appropriate half of overlapping double. |
| 579 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); |
| 580 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 581 | int sp_reg_num = info->GetReg().GetRegNum(); |
| 582 | int dp_reg_num = sp_reg_num >> 1; |
| 583 | RegStorage dp_reg = RegStorage::Solo64(RegStorage::kFloatingPoint | dp_reg_num); |
| 584 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
| 585 | // Double precision register's master storage should refer to itself. |
| 586 | DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); |
| 587 | // Redirect single precision's master storage to master. |
| 588 | info->SetMaster(dp_reg_info); |
| 589 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 590 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 591 | if (sp_reg_num & 1) { |
| 592 | // For odd singles, change to user the high word of the backing double. |
| 593 | info->SetStorageMask(0x2); |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | // TODO: re-enable this when we can safely save r4 over the suspension code path. |
| 598 | bool no_suspend = NO_SUSPEND; // || !Runtime::Current()->ExplicitSuspendChecks(); |
| 599 | if (no_suspend) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 600 | GetRegInfo(rs_rA64_SUSPEND)->MarkFree(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 601 | } |
| 602 | |
| 603 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 604 | // TODO: adjust when we roll to hard float calling convention. |
| 605 | reg_pool_->next_core_reg_ = 2; |
| 606 | reg_pool_->next_sp_reg_ = 0; |
| 607 | reg_pool_->next_dp_reg_ = 0; |
| 608 | } |
| 609 | |
| 610 | void Arm64Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 611 | LOG(FATAL) << "Unexpected call to FreeRegLocTemps for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | /* |
| 615 | * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some |
| 616 | * instructions might call out to C/assembly helper functions. Until |
| 617 | * machinery is in place, always spill lr. |
| 618 | */ |
| 619 | |
| 620 | void Arm64Mir2Lir::AdjustSpillMask() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 621 | core_spill_mask_ |= (1 << rs_rA64_LR.GetRegNum()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 622 | num_core_spills_++; |
| 623 | } |
| 624 | |
| 625 | /* |
| 626 | * Mark a callee-save fp register as promoted. Note that |
| 627 | * vpush/vpop uses contiguous register lists so we must |
| 628 | * include any holes in the mask. Associate holes with |
| 629 | * Dalvik register INVALID_VREG (0xFFFFU). |
| 630 | */ |
| 631 | void Arm64Mir2Lir::MarkPreservedSingle(int v_reg, RegStorage reg) { |
| 632 | DCHECK_GE(reg.GetRegNum(), ARM_FP_CALLEE_SAVE_BASE); |
| 633 | int adjusted_reg_num = reg.GetRegNum() - ARM_FP_CALLEE_SAVE_BASE; |
| 634 | // Ensure fp_vmap_table is large enough |
| 635 | int table_size = fp_vmap_table_.size(); |
| 636 | for (int i = table_size; i < (adjusted_reg_num + 1); i++) { |
| 637 | fp_vmap_table_.push_back(INVALID_VREG); |
| 638 | } |
| 639 | // Add the current mapping |
| 640 | fp_vmap_table_[adjusted_reg_num] = v_reg; |
| 641 | // Size of fp_vmap_table is high-water mark, use to set mask |
| 642 | num_fp_spills_ = fp_vmap_table_.size(); |
| 643 | fp_spill_mask_ = ((1 << num_fp_spills_) - 1) << ARM_FP_CALLEE_SAVE_BASE; |
| 644 | } |
| 645 | |
| 646 | void Arm64Mir2Lir::MarkPreservedDouble(int v_reg, RegStorage reg) { |
| 647 | // TEMP: perform as 2 singles. |
| 648 | int reg_num = reg.GetRegNum() << 1; |
| 649 | RegStorage lo = RegStorage::Solo32(RegStorage::kFloatingPoint | reg_num); |
| 650 | RegStorage hi = RegStorage::Solo32(RegStorage::kFloatingPoint | reg_num | 1); |
| 651 | MarkPreservedSingle(v_reg, lo); |
| 652 | MarkPreservedSingle(v_reg + 1, hi); |
| 653 | } |
| 654 | |
| 655 | /* Clobber all regs that might be used by an external C call */ |
| 656 | void Arm64Mir2Lir::ClobberCallerSave() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 657 | // TODO(Arm64): implement this. |
| 658 | UNIMPLEMENTED(WARNING); |
| 659 | |
| 660 | Clobber(rs_x0); |
| 661 | Clobber(rs_x1); |
| 662 | Clobber(rs_x2); |
| 663 | Clobber(rs_x3); |
| 664 | Clobber(rs_x12); |
| 665 | Clobber(rs_x30); |
| 666 | Clobber(rs_f0); |
| 667 | Clobber(rs_f1); |
| 668 | Clobber(rs_f2); |
| 669 | Clobber(rs_f3); |
| 670 | Clobber(rs_f4); |
| 671 | Clobber(rs_f5); |
| 672 | Clobber(rs_f6); |
| 673 | Clobber(rs_f7); |
| 674 | Clobber(rs_f8); |
| 675 | Clobber(rs_f9); |
| 676 | Clobber(rs_f10); |
| 677 | Clobber(rs_f11); |
| 678 | Clobber(rs_f12); |
| 679 | Clobber(rs_f13); |
| 680 | Clobber(rs_f14); |
| 681 | Clobber(rs_f15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 682 | } |
| 683 | |
| 684 | RegLocation Arm64Mir2Lir::GetReturnWideAlt() { |
| 685 | RegLocation res = LocCReturnWide(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 686 | res.reg.SetReg(rx2); |
| 687 | res.reg.SetHighReg(rx3); |
| 688 | Clobber(rs_x2); |
| 689 | Clobber(rs_x3); |
| 690 | MarkInUse(rs_x2); |
| 691 | MarkInUse(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 692 | MarkWide(res.reg); |
| 693 | return res; |
| 694 | } |
| 695 | |
| 696 | RegLocation Arm64Mir2Lir::GetReturnAlt() { |
| 697 | RegLocation res = LocCReturn(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 698 | res.reg.SetReg(rx1); |
| 699 | Clobber(rs_x1); |
| 700 | MarkInUse(rs_x1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 701 | return res; |
| 702 | } |
| 703 | |
| 704 | /* To be used when explicitly managing register use */ |
| 705 | void Arm64Mir2Lir::LockCallTemps() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 706 | LockTemp(rs_x0); |
| 707 | LockTemp(rs_x1); |
| 708 | LockTemp(rs_x2); |
| 709 | LockTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 710 | } |
| 711 | |
| 712 | /* To be used when explicitly managing register use */ |
| 713 | void Arm64Mir2Lir::FreeCallTemps() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 714 | FreeTemp(rs_x0); |
| 715 | FreeTemp(rs_x1); |
| 716 | FreeTemp(rs_x2); |
| 717 | FreeTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 718 | } |
| 719 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 720 | RegStorage Arm64Mir2Lir::LoadHelper(A64ThreadOffset offset) { |
| 721 | // TODO(Arm64): use LoadWordDisp instead. |
| 722 | // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); |
| 723 | LoadBaseDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR, k64); |
| 724 | return rs_rA64_LR; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 725 | } |
| 726 | |
| 727 | LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 728 | RegStorage tmp = rs_x0; |
| 729 | LoadWordDisp(rs_rA64_SELF, A64_THREAD_SUSPEND_TRIGGER_OFFSET, tmp); |
| 730 | LIR* load2 = LoadWordDisp(tmp, 0, tmp); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 731 | return load2; |
| 732 | } |
| 733 | |
| 734 | uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { |
| 735 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 736 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { |
| 740 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 741 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 742 | } |
| 743 | |
| 744 | const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { |
| 745 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 746 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | /* |
| 750 | * Somewhat messy code here. We want to allocate a pair of contiguous |
| 751 | * physical single-precision floating point registers starting with |
| 752 | * an even numbered reg. It is possible that the paired s_reg (s_reg+1) |
| 753 | * has already been allocated - try to fit if possible. Fail to |
| 754 | * allocate if we can't meet the requirements for the pair of |
| 755 | * s_reg<=sX[even] & (s_reg+1)<= sX+1. |
| 756 | */ |
| 757 | // TODO: needs rewrite to support non-backed 64-bit float regs. |
| 758 | RegStorage Arm64Mir2Lir::AllocPreservedDouble(int s_reg) { |
| 759 | RegStorage res; |
| 760 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 761 | int p_map_idx = SRegToPMap(s_reg); |
| 762 | if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { |
| 763 | // Upper reg is already allocated. Can we fit? |
| 764 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 765 | if ((high_reg & 1) == 0) { |
| 766 | // High reg is even - fail. |
| 767 | return res; // Invalid. |
| 768 | } |
| 769 | // Is the low reg of the pair free? |
| 770 | // FIXME: rework. |
| 771 | RegisterInfo* p = GetRegInfo(RegStorage::FloatSolo32(high_reg - 1)); |
| 772 | if (p->InUse() || p->IsTemp()) { |
| 773 | // Already allocated or not preserved - fail. |
| 774 | return res; // Invalid. |
| 775 | } |
| 776 | // OK - good to go. |
| 777 | res = RegStorage::FloatSolo64(p->GetReg().GetRegNum() >> 1); |
| 778 | p->MarkInUse(); |
| 779 | MarkPreservedSingle(v_reg, p->GetReg()); |
| 780 | } else { |
| 781 | /* |
| 782 | * TODO: until runtime support is in, make sure we avoid promoting the same vreg to |
| 783 | * different underlying physical registers. |
| 784 | */ |
| 785 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->dp_regs_); |
| 786 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 787 | if (!info->IsTemp() && !info->InUse()) { |
| 788 | res = info->GetReg(); |
| 789 | info->MarkInUse(); |
| 790 | MarkPreservedDouble(v_reg, info->GetReg()); |
| 791 | break; |
| 792 | } |
| 793 | } |
| 794 | } |
| 795 | if (res.Valid()) { |
| 796 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 797 | promotion_map_[p_map_idx].FpReg = res.DoubleToLowSingle().GetReg(); |
| 798 | promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; |
| 799 | promotion_map_[p_map_idx+1].FpReg = res.DoubleToHighSingle().GetReg(); |
| 800 | } |
| 801 | return res; |
| 802 | } |
| 803 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 804 | // TODO(Arm64): reuse info in QuickArgumentVisitor? |
| 805 | static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used, |
| 806 | OpSize* op_size) { |
| 807 | if (loc->fp) { |
| 808 | int n = *num_fpr_used; |
| 809 | if (n < 8) { |
| 810 | *num_fpr_used = n + 1; |
| 811 | RegStorage::RegStorageKind reg_kind; |
| 812 | if (loc->wide) { |
| 813 | *op_size = kDouble; |
| 814 | reg_kind = RegStorage::k64BitSolo; |
| 815 | } else { |
| 816 | *op_size = kSingle; |
| 817 | reg_kind = RegStorage::k32BitSolo; |
| 818 | } |
| 819 | return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n); |
| 820 | } |
| 821 | } else { |
| 822 | int n = *num_gpr_used; |
| 823 | if (n < 7) { |
| 824 | *num_gpr_used = n + 1; |
| 825 | if (loc->wide) { |
| 826 | *op_size = k64; |
| 827 | return RegStorage::Solo64(n); |
| 828 | } else { |
| 829 | *op_size = k32; |
| 830 | return RegStorage::Solo32(n); |
| 831 | } |
| 832 | } |
| 833 | } |
| 834 | |
| 835 | return RegStorage::InvalidReg(); |
| 836 | } |
| 837 | |
| 838 | /* |
| 839 | * If there are any ins passed in registers that have not been promoted |
| 840 | * to a callee-save register, flush them to the frame. Perform initial |
| 841 | * assignment of promoted arguments. |
| 842 | * |
| 843 | * ArgLocs is an array of location records describing the incoming arguments |
| 844 | * with one location record per word of argument. |
| 845 | */ |
| 846 | void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { |
| 847 | int num_gpr_used = 1; |
| 848 | int num_fpr_used = 0; |
| 849 | |
| 850 | /* |
| 851 | * Dummy up a RegLocation for the incoming Method* |
| 852 | * It will attempt to keep kArg0 live (or copy it to home location |
| 853 | * if promoted). |
| 854 | */ |
| 855 | RegLocation rl_src = rl_method; |
| 856 | rl_src.location = kLocPhysReg; |
| 857 | rl_src.reg = TargetReg(kArg0); |
| 858 | rl_src.home = false; |
| 859 | MarkLive(rl_src); |
| 860 | |
| 861 | // TODO(Arm64): compress the Method pointer? |
| 862 | StoreValueWide(rl_method, rl_src); |
| 863 | |
| 864 | // If Method* has been promoted, explicitly flush |
| 865 | if (rl_method.location == kLocPhysReg) { |
| 866 | StoreWordDisp(TargetReg(kSp), 0, TargetReg(kArg0)); |
| 867 | } |
| 868 | |
| 869 | if (cu_->num_ins == 0) { |
| 870 | return; |
| 871 | } |
| 872 | |
| 873 | int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; |
| 874 | for (int i = 0; i < cu_->num_ins; i++) { |
| 875 | PromotionMap* v_map = &promotion_map_[start_vreg + i]; |
| 876 | RegLocation* t_loc = &ArgLocs[i]; |
| 877 | OpSize op_size; |
| 878 | RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size); |
| 879 | |
| 880 | if (reg.Valid()) { |
| 881 | if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { |
| 882 | OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); |
| 883 | } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { |
| 884 | OpRegCopy(RegStorage::Solo32(v_map->FpReg), reg); |
| 885 | } else { |
| 886 | StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size); |
| 887 | if (reg.Is64Bit()) { |
| 888 | if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) { |
| 889 | LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots"; |
| 890 | } |
| 891 | i += 1; |
| 892 | } |
| 893 | } |
| 894 | } else { |
| 895 | // If arriving in frame & promoted |
| 896 | if (v_map->core_location == kLocPhysReg) { |
| 897 | LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), |
| 898 | RegStorage::Solo32(v_map->core_reg)); |
| 899 | } |
| 900 | if (v_map->fp_location == kLocPhysReg) { |
| 901 | LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->FpReg)); |
| 902 | } |
| 903 | } |
| 904 | } |
| 905 | } |
| 906 | |
| 907 | int Arm64Mir2Lir::LoadArgRegs(CallInfo* info, int call_state, |
| 908 | NextCallInsn next_call_insn, |
| 909 | const MethodReference& target_method, |
| 910 | uint32_t vtable_idx, uintptr_t direct_code, |
| 911 | uintptr_t direct_method, InvokeType type, bool skip_this) { |
| 912 | int last_arg_reg = TargetReg(kArg3).GetReg(); |
| 913 | int next_reg = TargetReg(kArg1).GetReg(); |
| 914 | int next_arg = 0; |
| 915 | if (skip_this) { |
| 916 | next_reg++; |
| 917 | next_arg++; |
| 918 | } |
| 919 | for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) { |
| 920 | RegLocation rl_arg = info->args[next_arg++]; |
| 921 | rl_arg = UpdateRawLoc(rl_arg); |
| 922 | if (rl_arg.wide && (next_reg <= TargetReg(kArg2).GetReg())) { |
| 923 | RegStorage r_tmp(RegStorage::k64BitPair, next_reg, next_reg + 1); |
| 924 | LoadValueDirectWideFixed(rl_arg, r_tmp); |
| 925 | next_reg++; |
| 926 | next_arg++; |
| 927 | } else { |
| 928 | if (rl_arg.wide) { |
| 929 | rl_arg = NarrowRegLoc(rl_arg); |
| 930 | rl_arg.is_const = false; |
| 931 | } |
| 932 | LoadValueDirectFixed(rl_arg, RegStorage::Solo32(next_reg)); |
| 933 | } |
| 934 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 935 | direct_code, direct_method, type); |
| 936 | } |
| 937 | return call_state; |
| 938 | } |
| 939 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 940 | } // namespace art |