Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "mips_lir.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 25 | class MipsMir2Lir FINAL : public Mir2Lir { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 26 | public: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
| 28 | |
| 29 | // Required for target - codegen utilities. |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 30 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 31 | RegLocation rl_dest, int lit); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 32 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 33 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 34 | RegStorage LoadHelper(ThreadOffset<4> offset); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 35 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 36 | OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 37 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 38 | OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 39 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 40 | RegStorage r_dest, OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 41 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 42 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 43 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
| 44 | OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 45 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 46 | OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 47 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 48 | RegStorage r_src, OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 49 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 50 | |
| 51 | // Required for target - register utilities. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 52 | RegStorage AllocTypedTemp(bool fp_hint, int reg_class); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 53 | RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 54 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 55 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 56 | RegLocation GetReturnAlt(); |
| 57 | RegLocation GetReturnWideAlt(); |
| 58 | RegLocation LocCReturn(); |
| 59 | RegLocation LocCReturnDouble(); |
| 60 | RegLocation LocCReturnFloat(); |
| 61 | RegLocation LocCReturnWide(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 62 | uint64_t GetRegMaskCommon(RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 63 | void AdjustSpillMask(); |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 64 | void ClobberCallerSave(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 65 | void FreeCallTemps(); |
| 66 | void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); |
| 67 | void LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 68 | void MarkPreservedSingle(int v_reg, RegStorage reg); |
| 69 | void MarkPreservedDouble(int v_reg, RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 70 | void CompilerInitializeRegAlloc(); |
| 71 | |
| 72 | // Required for target - miscellaneous. |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 73 | void AssembleLIR(); |
| 74 | int AssignInsnOffsets(); |
| 75 | void AssignOffsets(); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 76 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 77 | void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 78 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 79 | const char* GetTargetInstFmt(int opcode); |
| 80 | const char* GetTargetInstName(int opcode); |
| 81 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
| 82 | uint64_t GetPCUseDefEncoding(); |
| 83 | uint64_t GetTargetInstFlags(int opcode); |
| 84 | int GetInsnSize(LIR* lir); |
| 85 | bool IsUnconditionalBranch(LIR* lir); |
| 86 | |
| 87 | // Required for target - Dalvik-level generators. |
| 88 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 89 | RegLocation rl_src1, RegLocation rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 90 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 91 | RegLocation rl_index, RegLocation rl_dest, int scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 92 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 93 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 94 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 95 | RegLocation rl_shift); |
| 96 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 97 | RegLocation rl_src2); |
| 98 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 99 | RegLocation rl_src2); |
| 100 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 101 | RegLocation rl_src2); |
| 102 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 103 | RegLocation rl_src2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 104 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 105 | RegLocation rl_src2); |
| 106 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 107 | RegLocation rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 108 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 109 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 111 | bool GenInlinedSqrt(CallInfo* info); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 112 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 113 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 114 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 115 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 116 | RegLocation rl_src2); |
| 117 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 118 | RegLocation rl_src2); |
| 119 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 120 | RegLocation rl_src2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 121 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 122 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 123 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 124 | void GenDivZeroCheckWide(RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 125 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 126 | void GenExitSequence(); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 127 | void GenSpecialExitSequence(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 128 | void GenFillArrayData(uint32_t table_offset, RegLocation rl_src); |
| 129 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 130 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 131 | void GenSelect(BasicBlock* bb, MIR* mir); |
| 132 | void GenMemBarrier(MemBarrierKind barrier_kind); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 133 | void GenMoveException(RegLocation rl_dest); |
| 134 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 135 | int first_bit, int second_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 136 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 137 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
| 138 | void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); |
| 139 | void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 140 | bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 141 | |
| 142 | // Required for target - single operation generators. |
| 143 | LIR* OpUnconditionalBranch(LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 144 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 145 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 146 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 147 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 148 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 149 | LIR* OpIT(ConditionCode cond, const char* guide); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 150 | void OpEndIT(LIR* it); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 151 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 152 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 153 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 154 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 155 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
| 156 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 157 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 158 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 159 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 160 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 161 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 162 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 163 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 164 | LIR* OpTestSuspend(LIR* target); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 165 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 166 | LIR* OpVldm(RegStorage r_base, int count); |
| 167 | LIR* OpVstm(RegStorage r_base, int count); |
| 168 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 169 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 170 | void OpTlsCmp(ThreadOffset<4> offset, int val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 171 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 172 | // TODO: collapse r_dest. |
| 173 | LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 174 | RegStorage r_dest_hi, OpSize size); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 175 | // TODO: collapse r_src. |
| 176 | LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, |
| 177 | RegStorage r_src_hi, OpSize size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 178 | void SpillCoreRegs(); |
| 179 | void UnSpillCoreRegs(); |
| 180 | static const MipsEncodingMap EncodingMap[kMipsLast]; |
| 181 | bool InexpensiveConstantInt(int32_t value); |
| 182 | bool InexpensiveConstantFloat(int32_t value); |
| 183 | bool InexpensiveConstantLong(int64_t value); |
| 184 | bool InexpensiveConstantDouble(int64_t value); |
| 185 | |
| 186 | private: |
| 187 | void ConvertShortToLongBranch(LIR* lir); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 188 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
| 189 | RegLocation rl_src2, bool is_div, bool check_zero); |
| 190 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | } // namespace art |
| 194 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 195 | #endif // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |