Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains register alloction support. */ |
| 18 | |
| 19 | #include "dex/compiler_ir.h" |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "mir_to_lir-inl.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
| 25 | /* |
| 26 | * Free all allocated temps in the temp pools. Note that this does |
| 27 | * not affect the "liveness" of a temp register, which will stay |
| 28 | * live until it is either explicitly killed or reallocated. |
| 29 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 30 | void Mir2Lir::ResetRegPool() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 31 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 32 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
| 33 | info->in_use = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 34 | } |
| 35 | // Reset temp tracking sanity check. |
| 36 | if (kIsDebugBuild) { |
| 37 | live_sreg_ = INVALID_SREG; |
| 38 | } |
| 39 | } |
| 40 | |
| 41 | /* |
| 42 | * Set up temp & preserved register pools specialized by target. |
| 43 | * Note: num_regs may be zero. |
| 44 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 45 | void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 46 | for (int i = 0; i < num; i++) { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 47 | uint32_t reg_number = reg_nums[i]; |
| 48 | regs[i].reg = reg_number; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | regs[i].in_use = false; |
| 50 | regs[i].is_temp = false; |
| 51 | regs[i].pair = false; |
| 52 | regs[i].live = false; |
| 53 | regs[i].dirty = false; |
| 54 | regs[i].s_reg = INVALID_SREG; |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 55 | size_t map_size = reginfo_map_.Size(); |
| 56 | if (reg_number >= map_size) { |
| 57 | for (uint32_t i = 0; i < ((reg_number - map_size) + 1); i++) { |
| 58 | reginfo_map_.Insert(NULL); |
| 59 | } |
| 60 | } |
| 61 | reginfo_map_.Put(reg_number, ®s[i]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | } |
| 63 | } |
| 64 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 65 | void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | LOG(INFO) << "================================================"; |
| 67 | for (int i = 0; i < num_regs; i++) { |
| 68 | LOG(INFO) << StringPrintf( |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 69 | "R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d", |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 70 | p[i].reg, p[i].is_temp, p[i].in_use, p[i].pair, p[i].partner, |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 71 | p[i].live, p[i].dirty, p[i].s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 72 | } |
| 73 | LOG(INFO) << "================================================"; |
| 74 | } |
| 75 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 76 | void Mir2Lir::DumpCoreRegPool() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 77 | DumpRegPool(reg_pool_->core_regs, reg_pool_->num_core_regs); |
| 78 | } |
| 79 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 80 | void Mir2Lir::DumpFpRegPool() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 81 | DumpRegPool(reg_pool_->FPRegs, reg_pool_->num_fp_regs); |
| 82 | } |
| 83 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 84 | void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 85 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 86 | if (p[i].s_reg == s_reg) { |
| 87 | if (p[i].is_temp) { |
| 88 | p[i].live = false; |
| 89 | } |
| 90 | p[i].def_start = NULL; |
| 91 | p[i].def_end = NULL; |
| 92 | } |
| 93 | } |
| 94 | } |
| 95 | |
| 96 | /* |
| 97 | * Break the association between a Dalvik vreg and a physical temp register of either register |
| 98 | * class. |
| 99 | * TODO: Ideally, the public version of this code should not exist. Besides its local usage |
| 100 | * in the register utilities, is is also used by code gen routines to work around a deficiency in |
| 101 | * local register allocation, which fails to distinguish between the "in" and "out" identities |
| 102 | * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg |
| 103 | * is used both as the source and destination register of an operation in which the type |
| 104 | * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is |
| 105 | * addressed. |
| 106 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 107 | void Mir2Lir::ClobberSReg(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 108 | /* Reset live temp tracking sanity checker */ |
| 109 | if (kIsDebugBuild) { |
| 110 | if (s_reg == live_sreg_) { |
| 111 | live_sreg_ = INVALID_SREG; |
| 112 | } |
| 113 | } |
| 114 | ClobberSRegBody(reg_pool_->core_regs, reg_pool_->num_core_regs, s_reg); |
| 115 | ClobberSRegBody(reg_pool_->FPRegs, reg_pool_->num_fp_regs, s_reg); |
| 116 | } |
| 117 | |
| 118 | /* |
| 119 | * SSA names associated with the initial definitions of Dalvik |
| 120 | * registers are the same as the Dalvik register number (and |
| 121 | * thus take the same position in the promotion_map. However, |
| 122 | * the special Method* and compiler temp resisters use negative |
| 123 | * v_reg numbers to distinguish them and can have an arbitrary |
| 124 | * ssa name (above the last original Dalvik register). This function |
| 125 | * maps SSA names to positions in the promotion_map array. |
| 126 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 127 | int Mir2Lir::SRegToPMap(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 128 | DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); |
| 129 | DCHECK_GE(s_reg, 0); |
| 130 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 131 | if (v_reg >= 0) { |
| 132 | DCHECK_LT(v_reg, cu_->num_dalvik_registers); |
| 133 | return v_reg; |
| 134 | } else { |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 135 | /* |
| 136 | * It must be the case that the v_reg for temporary is less than or equal to the |
| 137 | * base reg for temps. For that reason, "position" must be zero or positive. |
| 138 | */ |
| 139 | unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg)); |
| 140 | |
| 141 | // The temporaries are placed after dalvik registers in the promotion map |
| 142 | DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps()); |
| 143 | return cu_->num_dalvik_registers + position; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 144 | } |
| 145 | } |
| 146 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 147 | void Mir2Lir::RecordCorePromotion(int reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 148 | int p_map_idx = SRegToPMap(s_reg); |
| 149 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 150 | GetRegInfo(reg)->in_use = true; |
| 151 | core_spill_mask_ |= (1 << reg); |
| 152 | // Include reg for later sort |
| 153 | core_vmap_table_.push_back(reg << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); |
| 154 | num_core_spills_++; |
| 155 | promotion_map_[p_map_idx].core_location = kLocPhysReg; |
| 156 | promotion_map_[p_map_idx].core_reg = reg; |
| 157 | } |
| 158 | |
| 159 | /* Reserve a callee-save register. Return -1 if none available */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 160 | int Mir2Lir::AllocPreservedCoreReg(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 161 | int res = -1; |
| 162 | RegisterInfo* core_regs = reg_pool_->core_regs; |
| 163 | for (int i = 0; i < reg_pool_->num_core_regs; i++) { |
| 164 | if (!core_regs[i].is_temp && !core_regs[i].in_use) { |
| 165 | res = core_regs[i].reg; |
| 166 | RecordCorePromotion(res, s_reg); |
| 167 | break; |
| 168 | } |
| 169 | } |
| 170 | return res; |
| 171 | } |
| 172 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 173 | void Mir2Lir::RecordFpPromotion(int reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 174 | int p_map_idx = SRegToPMap(s_reg); |
| 175 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 176 | GetRegInfo(reg)->in_use = true; |
| 177 | MarkPreservedSingle(v_reg, reg); |
| 178 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 179 | promotion_map_[p_map_idx].FpReg = reg; |
| 180 | } |
| 181 | |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 182 | // Reserve a callee-save fp single register. |
| 183 | int Mir2Lir::AllocPreservedSingle(int s_reg) { |
| 184 | int res = -1; // Return code if none available. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 185 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 186 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 187 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 188 | res = FPRegs[i].reg; |
| 189 | RecordFpPromotion(res, s_reg); |
| 190 | break; |
| 191 | } |
| 192 | } |
| 193 | return res; |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Somewhat messy code here. We want to allocate a pair of contiguous |
| 198 | * physical single-precision floating point registers starting with |
| 199 | * an even numbered reg. It is possible that the paired s_reg (s_reg+1) |
| 200 | * has already been allocated - try to fit if possible. Fail to |
| 201 | * allocate if we can't meet the requirements for the pair of |
| 202 | * s_reg<=sX[even] & (s_reg+1)<= sX+1. |
| 203 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 204 | int Mir2Lir::AllocPreservedDouble(int s_reg) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 205 | int res = -1; // Assume failure |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 206 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 207 | int p_map_idx = SRegToPMap(s_reg); |
| 208 | if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { |
| 209 | // Upper reg is already allocated. Can we fit? |
| 210 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 211 | if ((high_reg & 1) == 0) { |
| 212 | // High reg is even - fail. |
| 213 | return res; |
| 214 | } |
| 215 | // Is the low reg of the pair free? |
| 216 | RegisterInfo* p = GetRegInfo(high_reg-1); |
| 217 | if (p->in_use || p->is_temp) { |
| 218 | // Already allocated or not preserved - fail. |
| 219 | return res; |
| 220 | } |
| 221 | // OK - good to go. |
| 222 | res = p->reg; |
| 223 | p->in_use = true; |
| 224 | DCHECK_EQ((res & 1), 0); |
| 225 | MarkPreservedSingle(v_reg, res); |
| 226 | } else { |
| 227 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 228 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
| 229 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use && |
| 230 | ((FPRegs[i].reg & 0x1) == 0x0) && |
| 231 | !FPRegs[i+1].is_temp && !FPRegs[i+1].in_use && |
| 232 | ((FPRegs[i+1].reg & 0x1) == 0x1) && |
| 233 | (FPRegs[i].reg + 1) == FPRegs[i+1].reg) { |
| 234 | res = FPRegs[i].reg; |
| 235 | FPRegs[i].in_use = true; |
| 236 | MarkPreservedSingle(v_reg, res); |
| 237 | FPRegs[i+1].in_use = true; |
| 238 | DCHECK_EQ(res + 1, FPRegs[i+1].reg); |
| 239 | MarkPreservedSingle(v_reg+1, res+1); |
| 240 | break; |
| 241 | } |
| 242 | } |
| 243 | } |
| 244 | if (res != -1) { |
| 245 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 246 | promotion_map_[p_map_idx].FpReg = res; |
| 247 | promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; |
| 248 | promotion_map_[p_map_idx+1].FpReg = res + 1; |
| 249 | } |
| 250 | return res; |
| 251 | } |
| 252 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 253 | int Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 254 | bool required) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 255 | int next = *next_temp; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 256 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 257 | if (next >= num_regs) |
| 258 | next = 0; |
| 259 | if (p[next].is_temp && !p[next].in_use && !p[next].live) { |
| 260 | Clobber(p[next].reg); |
| 261 | p[next].in_use = true; |
| 262 | p[next].pair = false; |
| 263 | *next_temp = next + 1; |
| 264 | return p[next].reg; |
| 265 | } |
| 266 | next++; |
| 267 | } |
| 268 | next = *next_temp; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 269 | for (int i = 0; i< num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 270 | if (next >= num_regs) |
| 271 | next = 0; |
| 272 | if (p[next].is_temp && !p[next].in_use) { |
| 273 | Clobber(p[next].reg); |
| 274 | p[next].in_use = true; |
| 275 | p[next].pair = false; |
| 276 | *next_temp = next + 1; |
| 277 | return p[next].reg; |
| 278 | } |
| 279 | next++; |
| 280 | } |
| 281 | if (required) { |
| 282 | CodegenDump(); |
| 283 | DumpRegPool(reg_pool_->core_regs, |
| 284 | reg_pool_->num_core_regs); |
| 285 | LOG(FATAL) << "No free temp registers"; |
| 286 | } |
| 287 | return -1; // No register available |
| 288 | } |
| 289 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 290 | // REDO: too many assumptions. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 291 | int Mir2Lir::AllocTempDouble() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 292 | RegisterInfo* p = reg_pool_->FPRegs; |
| 293 | int num_regs = reg_pool_->num_fp_regs; |
| 294 | /* Start looking at an even reg */ |
| 295 | int next = reg_pool_->next_fp_reg & ~0x1; |
| 296 | |
| 297 | // First try to avoid allocating live registers |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 298 | for (int i = 0; i < num_regs; i+=2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 299 | if (next >= num_regs) |
| 300 | next = 0; |
| 301 | if ((p[next].is_temp && !p[next].in_use && !p[next].live) && |
| 302 | (p[next+1].is_temp && !p[next+1].in_use && !p[next+1].live)) { |
| 303 | Clobber(p[next].reg); |
| 304 | Clobber(p[next+1].reg); |
| 305 | p[next].in_use = true; |
| 306 | p[next+1].in_use = true; |
| 307 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 308 | DCHECK_EQ((p[next].reg & 0x1), 0); |
| 309 | reg_pool_->next_fp_reg = next + 2; |
| 310 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 311 | reg_pool_->next_fp_reg = 0; |
| 312 | } |
| 313 | return p[next].reg; |
| 314 | } |
| 315 | next += 2; |
| 316 | } |
| 317 | next = reg_pool_->next_fp_reg & ~0x1; |
| 318 | |
| 319 | // No choice - find a pair and kill it. |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 320 | for (int i = 0; i < num_regs; i+=2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 321 | if (next >= num_regs) |
| 322 | next = 0; |
| 323 | if (p[next].is_temp && !p[next].in_use && p[next+1].is_temp && |
| 324 | !p[next+1].in_use) { |
| 325 | Clobber(p[next].reg); |
| 326 | Clobber(p[next+1].reg); |
| 327 | p[next].in_use = true; |
| 328 | p[next+1].in_use = true; |
| 329 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 330 | DCHECK_EQ((p[next].reg & 0x1), 0); |
| 331 | reg_pool_->next_fp_reg = next + 2; |
| 332 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 333 | reg_pool_->next_fp_reg = 0; |
| 334 | } |
| 335 | return p[next].reg; |
| 336 | } |
| 337 | next += 2; |
| 338 | } |
| 339 | LOG(FATAL) << "No free temp registers (pair)"; |
| 340 | return -1; |
| 341 | } |
| 342 | |
| 343 | /* Return a temp if one is available, -1 otherwise */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 344 | int Mir2Lir::AllocFreeTemp() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 345 | return AllocTempBody(reg_pool_->core_regs, |
| 346 | reg_pool_->num_core_regs, |
Vladimir Marko | 73e08b3 | 2013-11-21 10:58:36 +0000 | [diff] [blame] | 347 | ®_pool_->next_core_reg, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 348 | } |
| 349 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 350 | int Mir2Lir::AllocTemp() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 351 | return AllocTempBody(reg_pool_->core_regs, |
| 352 | reg_pool_->num_core_regs, |
| 353 | ®_pool_->next_core_reg, true); |
| 354 | } |
| 355 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 356 | int Mir2Lir::AllocTempFloat() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 357 | return AllocTempBody(reg_pool_->FPRegs, |
| 358 | reg_pool_->num_fp_regs, |
| 359 | ®_pool_->next_fp_reg, true); |
| 360 | } |
| 361 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 362 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 363 | if (s_reg == -1) |
| 364 | return NULL; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 365 | for (int i = 0; i < num_regs; i++) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 366 | if ((p[i].s_reg == s_reg) && p[i].live) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 367 | if (p[i].is_temp) |
| 368 | p[i].in_use = true; |
| 369 | return &p[i]; |
| 370 | } |
| 371 | } |
| 372 | return NULL; |
| 373 | } |
| 374 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 375 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 376 | RegisterInfo* res = NULL; |
| 377 | switch (reg_class) { |
| 378 | case kAnyReg: |
| 379 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 380 | reg_pool_->num_fp_regs, s_reg); |
| 381 | if (res) |
| 382 | break; |
| 383 | /* Intentional fallthrough */ |
| 384 | case kCoreReg: |
| 385 | res = AllocLiveBody(reg_pool_->core_regs, |
| 386 | reg_pool_->num_core_regs, s_reg); |
| 387 | break; |
| 388 | case kFPReg: |
| 389 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 390 | reg_pool_->num_fp_regs, s_reg); |
| 391 | break; |
| 392 | default: |
| 393 | LOG(FATAL) << "Invalid register type"; |
| 394 | } |
| 395 | return res; |
| 396 | } |
| 397 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 398 | void Mir2Lir::FreeTemp(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 399 | RegisterInfo* p = GetRegInfo(reg); |
| 400 | if (p->is_temp) { |
| 401 | p->in_use = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 402 | } |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 403 | p->pair = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 404 | } |
| 405 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 406 | Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 407 | RegisterInfo* p = GetRegInfo(reg); |
| 408 | return p->live ? p : NULL; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 409 | } |
| 410 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 411 | Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 412 | RegisterInfo* p = GetRegInfo(reg); |
| 413 | return (p->is_temp) ? p : NULL; |
| 414 | } |
| 415 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 416 | Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 417 | RegisterInfo* p = GetRegInfo(reg); |
| 418 | return (p->is_temp) ? NULL : p; |
| 419 | } |
| 420 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 421 | bool Mir2Lir::IsDirty(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | RegisterInfo* p = GetRegInfo(reg); |
| 423 | return p->dirty; |
| 424 | } |
| 425 | |
| 426 | /* |
| 427 | * Similar to AllocTemp(), but forces the allocation of a specific |
| 428 | * register. No check is made to see if the register was previously |
| 429 | * allocated. Use with caution. |
| 430 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 431 | void Mir2Lir::LockTemp(int reg) { |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 432 | RegisterInfo* p = GetRegInfo(reg); |
| 433 | DCHECK(p->is_temp); |
| 434 | p->in_use = true; |
| 435 | p->live = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 436 | } |
| 437 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 438 | void Mir2Lir::ResetDef(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 439 | ResetDefBody(GetRegInfo(reg)); |
| 440 | } |
| 441 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 442 | void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 443 | if (start && finish) { |
| 444 | LIR *p; |
| 445 | DCHECK_EQ(s_reg1, s_reg2); |
Brian Carlstrom | 02c8cc6 | 2013-07-18 15:54:44 -0700 | [diff] [blame] | 446 | for (p = start; ; p = p->next) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | NopLIR(p); |
| 448 | if (p == finish) |
| 449 | break; |
| 450 | } |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | /* |
| 455 | * Mark the beginning and end LIR of a def sequence. Note that |
| 456 | * on entry start points to the LIR prior to the beginning of the |
| 457 | * sequence. |
| 458 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 459 | void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 460 | DCHECK(!rl.wide); |
| 461 | DCHECK(start && start->next); |
| 462 | DCHECK(finish); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 463 | RegisterInfo* p = GetRegInfo(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 464 | p->def_start = start->next; |
| 465 | p->def_end = finish; |
| 466 | } |
| 467 | |
| 468 | /* |
| 469 | * Mark the beginning and end LIR of a def sequence. Note that |
| 470 | * on entry start points to the LIR prior to the beginning of the |
| 471 | * sequence. |
| 472 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 473 | void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 474 | DCHECK(rl.wide); |
| 475 | DCHECK(start && start->next); |
| 476 | DCHECK(finish); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 477 | RegisterInfo* p = GetRegInfo(rl.reg.GetReg()); |
| 478 | ResetDef(rl.reg.GetHighReg()); // Only track low of pair |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 479 | p->def_start = start->next; |
| 480 | p->def_end = finish; |
| 481 | } |
| 482 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 483 | RegLocation Mir2Lir::WideToNarrow(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 484 | DCHECK(rl.wide); |
| 485 | if (rl.location == kLocPhysReg) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 486 | RegisterInfo* info_lo = GetRegInfo(rl.reg.GetReg()); |
| 487 | RegisterInfo* info_hi = GetRegInfo(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 488 | if (info_lo->is_temp) { |
| 489 | info_lo->pair = false; |
| 490 | info_lo->def_start = NULL; |
| 491 | info_lo->def_end = NULL; |
| 492 | } |
| 493 | if (info_hi->is_temp) { |
| 494 | info_hi->pair = false; |
| 495 | info_hi->def_start = NULL; |
| 496 | info_hi->def_end = NULL; |
| 497 | } |
| 498 | } |
| 499 | rl.wide = false; |
| 500 | return rl; |
| 501 | } |
| 502 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 503 | void Mir2Lir::ResetDefLoc(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 504 | DCHECK(!rl.wide); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 505 | RegisterInfo* p = IsTemp(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 506 | if (p && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 507 | DCHECK(!p->pair); |
| 508 | NullifyRange(p->def_start, p->def_end, p->s_reg, rl.s_reg_low); |
| 509 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 510 | ResetDef(rl.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 511 | } |
| 512 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 513 | void Mir2Lir::ResetDefLocWide(RegLocation rl) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 514 | DCHECK(rl.wide); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 515 | RegisterInfo* p_low = IsTemp(rl.reg.GetReg()); |
| 516 | RegisterInfo* p_high = IsTemp(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 517 | if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 518 | DCHECK(p_low->pair); |
| 519 | NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); |
| 520 | } |
| 521 | if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 522 | DCHECK(p_high->pair); |
| 523 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 524 | ResetDef(rl.reg.GetReg()); |
| 525 | ResetDef(rl.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 526 | } |
| 527 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 528 | void Mir2Lir::ResetDefTracking() { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 529 | for (int i = 0; i< reg_pool_->num_core_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 530 | ResetDefBody(®_pool_->core_regs[i]); |
| 531 | } |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 532 | for (int i = 0; i< reg_pool_->num_fp_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 533 | ResetDefBody(®_pool_->FPRegs[i]); |
| 534 | } |
| 535 | } |
| 536 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 537 | void Mir2Lir::ClobberAllRegs() { |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 538 | GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); |
| 539 | for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { |
| 540 | info->live = false; |
| 541 | info->s_reg = INVALID_SREG; |
| 542 | info->def_start = NULL; |
| 543 | info->def_end = NULL; |
| 544 | info->pair = false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 545 | } |
| 546 | } |
| 547 | |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 548 | void Mir2Lir::FlushSpecificReg(RegisterInfo* info) { |
| 549 | if (info->pair) { |
| 550 | FlushRegWide(info->reg, info->partner); |
| 551 | } else { |
| 552 | FlushReg(info->reg); |
| 553 | } |
| 554 | } |
| 555 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 556 | // Make sure nothing is live and dirty |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 557 | void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) { |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 558 | for (int i = 0; i < num_regs; i++) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 559 | if (info[i].live && info[i].dirty) { |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 560 | FlushSpecificReg(&info[i]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 561 | } |
| 562 | } |
| 563 | } |
| 564 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 565 | void Mir2Lir::FlushAllRegs() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 566 | FlushAllRegsBody(reg_pool_->core_regs, |
| 567 | reg_pool_->num_core_regs); |
| 568 | FlushAllRegsBody(reg_pool_->FPRegs, |
| 569 | reg_pool_->num_fp_regs); |
| 570 | ClobberAllRegs(); |
| 571 | } |
| 572 | |
| 573 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 574 | // TUNING: rewrite all of this reg stuff. Probably use an attribute table |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 575 | bool Mir2Lir::RegClassMatches(int reg_class, int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 576 | if (reg_class == kAnyReg) { |
| 577 | return true; |
| 578 | } else if (reg_class == kCoreReg) { |
| 579 | return !IsFpReg(reg); |
| 580 | } else { |
| 581 | return IsFpReg(reg); |
| 582 | } |
| 583 | } |
| 584 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 585 | void Mir2Lir::MarkLive(int reg, int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 586 | RegisterInfo* info = GetRegInfo(reg); |
| 587 | if ((info->reg == reg) && (info->s_reg == s_reg) && info->live) { |
| 588 | return; /* already live */ |
| 589 | } else if (s_reg != INVALID_SREG) { |
| 590 | ClobberSReg(s_reg); |
| 591 | if (info->is_temp) { |
| 592 | info->live = true; |
| 593 | } |
| 594 | } else { |
| 595 | /* Can't be live if no associated s_reg */ |
| 596 | DCHECK(info->is_temp); |
| 597 | info->live = false; |
| 598 | } |
| 599 | info->s_reg = s_reg; |
| 600 | } |
| 601 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 602 | void Mir2Lir::MarkTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 603 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 604 | tempreg_info_.Insert(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 605 | info->is_temp = true; |
| 606 | } |
| 607 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 608 | void Mir2Lir::UnmarkTemp(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 609 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 610 | tempreg_info_.Delete(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 611 | info->is_temp = false; |
| 612 | } |
| 613 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 614 | void Mir2Lir::MarkPair(int low_reg, int high_reg) { |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 615 | DCHECK_NE(low_reg, high_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 616 | RegisterInfo* info_lo = GetRegInfo(low_reg); |
| 617 | RegisterInfo* info_hi = GetRegInfo(high_reg); |
| 618 | info_lo->pair = info_hi->pair = true; |
| 619 | info_lo->partner = high_reg; |
| 620 | info_hi->partner = low_reg; |
| 621 | } |
| 622 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 623 | void Mir2Lir::MarkClean(RegLocation loc) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 624 | RegisterInfo* info = GetRegInfo(loc.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 625 | info->dirty = false; |
| 626 | if (loc.wide) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 627 | info = GetRegInfo(loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 628 | info->dirty = false; |
| 629 | } |
| 630 | } |
| 631 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 632 | void Mir2Lir::MarkDirty(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 633 | if (loc.home) { |
| 634 | // If already home, can't be dirty |
| 635 | return; |
| 636 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 637 | RegisterInfo* info = GetRegInfo(loc.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 638 | info->dirty = true; |
| 639 | if (loc.wide) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 640 | info = GetRegInfo(loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 641 | info->dirty = true; |
| 642 | } |
| 643 | } |
| 644 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 645 | void Mir2Lir::MarkInUse(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 646 | RegisterInfo* info = GetRegInfo(reg); |
| 647 | info->in_use = true; |
| 648 | } |
| 649 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 650 | void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 651 | RegisterInfo* new_info = GetRegInfo(new_reg); |
| 652 | RegisterInfo* old_info = GetRegInfo(old_reg); |
| 653 | // Target temp status must not change |
| 654 | bool is_temp = new_info->is_temp; |
| 655 | *new_info = *old_info; |
| 656 | // Restore target's temp status |
| 657 | new_info->is_temp = is_temp; |
| 658 | new_info->reg = new_reg; |
| 659 | } |
| 660 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 661 | bool Mir2Lir::CheckCorePoolSanity() { |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 662 | for (static int i = 0; i < reg_pool_->num_core_regs; i++) { |
| 663 | if (reg_pool_->core_regs[i].pair) { |
| 664 | static int my_reg = reg_pool_->core_regs[i].reg; |
| 665 | static int my_sreg = reg_pool_->core_regs[i].s_reg; |
| 666 | static int partner_reg = reg_pool_->core_regs[i].partner; |
| 667 | static RegisterInfo* partner = GetRegInfo(partner_reg); |
| 668 | DCHECK(partner != NULL); |
| 669 | DCHECK(partner->pair); |
| 670 | DCHECK_EQ(my_reg, partner->partner); |
| 671 | static int partner_sreg = partner->s_reg; |
| 672 | if (my_sreg == INVALID_SREG) { |
| 673 | DCHECK_EQ(partner_sreg, INVALID_SREG); |
| 674 | } else { |
| 675 | int diff = my_sreg - partner_sreg; |
| 676 | DCHECK((diff == -1) || (diff == 1)); |
| 677 | } |
| 678 | } |
| 679 | if (!reg_pool_->core_regs[i].live) { |
| 680 | DCHECK(reg_pool_->core_regs[i].def_start == NULL); |
| 681 | DCHECK(reg_pool_->core_regs[i].def_end == NULL); |
| 682 | } |
| 683 | } |
| 684 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 685 | } |
| 686 | |
| 687 | /* |
| 688 | * Return an updated location record with current in-register status. |
| 689 | * If the value lives in live temps, reflect that fact. No code |
| 690 | * is generated. If the live value is part of an older pair, |
| 691 | * clobber both low and high. |
| 692 | * TUNING: clobbering both is a bit heavy-handed, but the alternative |
| 693 | * is a bit complex when dealing with FP regs. Examine code to see |
| 694 | * if it's worthwhile trying to be more clever here. |
| 695 | */ |
| 696 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 697 | RegLocation Mir2Lir::UpdateLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 698 | DCHECK(!loc.wide); |
| 699 | DCHECK(CheckCorePoolSanity()); |
| 700 | if (loc.location != kLocPhysReg) { |
| 701 | DCHECK((loc.location == kLocDalvikFrame) || |
| 702 | (loc.location == kLocCompilerTemp)); |
| 703 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 704 | if (info_lo) { |
| 705 | if (info_lo->pair) { |
| 706 | Clobber(info_lo->reg); |
| 707 | Clobber(info_lo->partner); |
| 708 | FreeTemp(info_lo->reg); |
| 709 | } else { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 710 | loc.reg = RegStorage(RegStorage::k32BitSolo, info_lo->reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 711 | loc.location = kLocPhysReg; |
| 712 | } |
| 713 | } |
| 714 | } |
| 715 | |
| 716 | return loc; |
| 717 | } |
| 718 | |
| 719 | /* see comments for update_loc */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 720 | RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 721 | DCHECK(loc.wide); |
| 722 | DCHECK(CheckCorePoolSanity()); |
| 723 | if (loc.location != kLocPhysReg) { |
| 724 | DCHECK((loc.location == kLocDalvikFrame) || |
| 725 | (loc.location == kLocCompilerTemp)); |
| 726 | // Are the dalvik regs already live in physical registers? |
| 727 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 728 | RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); |
| 729 | bool match = true; |
| 730 | match = match && (info_lo != NULL); |
| 731 | match = match && (info_hi != NULL); |
| 732 | // Are they both core or both FP? |
| 733 | match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); |
| 734 | // If a pair of floating point singles, are they properly aligned? |
| 735 | if (match && IsFpReg(info_lo->reg)) { |
| 736 | match &= ((info_lo->reg & 0x1) == 0); |
| 737 | match &= ((info_hi->reg - info_lo->reg) == 1); |
| 738 | } |
| 739 | // If previously used as a pair, it is the same pair? |
| 740 | if (match && (info_lo->pair || info_hi->pair)) { |
| 741 | match = (info_lo->pair == info_hi->pair); |
| 742 | match &= ((info_lo->reg == info_hi->partner) && |
| 743 | (info_hi->reg == info_lo->partner)); |
| 744 | } |
| 745 | if (match) { |
| 746 | // Can reuse - update the register usage info |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 747 | loc.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 748 | loc.reg = RegStorage(RegStorage::k64BitPair, info_lo->reg, info_hi->reg); |
| 749 | MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); |
| 750 | DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 751 | return loc; |
| 752 | } |
| 753 | // Can't easily reuse - clobber and free any overlaps |
| 754 | if (info_lo) { |
| 755 | Clobber(info_lo->reg); |
| 756 | FreeTemp(info_lo->reg); |
| 757 | if (info_lo->pair) |
| 758 | Clobber(info_lo->partner); |
| 759 | } |
| 760 | if (info_hi) { |
| 761 | Clobber(info_hi->reg); |
| 762 | FreeTemp(info_hi->reg); |
| 763 | if (info_hi->pair) |
| 764 | Clobber(info_hi->partner); |
| 765 | } |
| 766 | } |
| 767 | return loc; |
| 768 | } |
| 769 | |
| 770 | |
| 771 | /* For use in cases we don't know (or care) width */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 772 | RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 773 | if (loc.wide) |
| 774 | return UpdateLocWide(loc); |
| 775 | else |
| 776 | return UpdateLoc(loc); |
| 777 | } |
| 778 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 779 | RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 780 | DCHECK(loc.wide); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 781 | int32_t low_reg; |
| 782 | int32_t high_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 783 | |
| 784 | loc = UpdateLocWide(loc); |
| 785 | |
| 786 | /* If already in registers, we can assume proper form. Right reg class? */ |
| 787 | if (loc.location == kLocPhysReg) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 788 | DCHECK_EQ(IsFpReg(loc.reg.GetReg()), IsFpReg(loc.reg.GetHighReg())); |
| 789 | DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); |
| 790 | if (!RegClassMatches(reg_class, loc.reg.GetReg())) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 791 | /* Wrong register class. Reallocate and copy */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 792 | RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class); |
| 793 | low_reg = new_regs.GetReg(); |
| 794 | high_reg = new_regs.GetHighReg(); |
| 795 | OpRegCopyWide(low_reg, high_reg, loc.reg.GetReg(), loc.reg.GetHighReg()); |
| 796 | CopyRegInfo(low_reg, loc.reg.GetReg()); |
| 797 | CopyRegInfo(high_reg, loc.reg.GetHighReg()); |
| 798 | Clobber(loc.reg.GetReg()); |
| 799 | Clobber(loc.reg.GetHighReg()); |
| 800 | loc.reg = new_regs; |
| 801 | MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); |
| 802 | DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 803 | } |
| 804 | return loc; |
| 805 | } |
| 806 | |
| 807 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 808 | DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); |
| 809 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 810 | loc.reg = AllocTypedTempWide(loc.fp, reg_class); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 811 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 812 | MarkPair(loc.reg.GetReg(), loc.reg.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 813 | if (update) { |
| 814 | loc.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 815 | MarkLive(loc.reg.GetReg(), loc.s_reg_low); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 816 | // Does this wide value live in two registers or one vector register? |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 817 | if (loc.reg.GetReg() != loc.reg.GetHighReg()) { |
| 818 | MarkLive(loc.reg.GetHighReg(), GetSRegHi(loc.s_reg_low)); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 819 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 820 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 821 | DCHECK(!IsFpReg(loc.reg.GetReg()) || ((loc.reg.GetReg() & 0x1) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 822 | return loc; |
| 823 | } |
| 824 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 825 | RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 826 | int new_reg; |
| 827 | |
| 828 | if (loc.wide) |
| 829 | return EvalLocWide(loc, reg_class, update); |
| 830 | |
| 831 | loc = UpdateLoc(loc); |
| 832 | |
| 833 | if (loc.location == kLocPhysReg) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 834 | if (!RegClassMatches(reg_class, loc.reg.GetReg())) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 835 | /* Wrong register class. Realloc, copy and transfer ownership */ |
| 836 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 837 | OpRegCopy(new_reg, loc.reg.GetReg()); |
| 838 | CopyRegInfo(new_reg, loc.reg.GetReg()); |
| 839 | Clobber(loc.reg.GetReg()); |
| 840 | loc.reg = RegStorage(RegStorage::k32BitSolo, new_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 841 | } |
| 842 | return loc; |
| 843 | } |
| 844 | |
| 845 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 846 | |
| 847 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 848 | loc.reg = RegStorage(RegStorage::k32BitSolo, new_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 849 | |
| 850 | if (update) { |
| 851 | loc.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 852 | MarkLive(loc.reg.GetReg(), loc.s_reg_low); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 853 | } |
| 854 | return loc; |
| 855 | } |
| 856 | |
| 857 | /* USE SSA names to count references of base Dalvik v_regs. */ |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 858 | void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 859 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 860 | RegLocation loc = mir_graph_->reg_location_[i]; |
| 861 | RefCounts* counts = loc.fp ? fp_counts : core_counts; |
| 862 | int p_map_idx = SRegToPMap(loc.s_reg_low); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 863 | if (loc.fp) { |
| 864 | if (loc.wide) { |
| 865 | // Treat doubles as a unit, using upper half of fp_counts array. |
| 866 | counts[p_map_idx + num_regs].count += mir_graph_->GetUseCount(i); |
| 867 | i++; |
| 868 | } else { |
| 869 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 870 | } |
| 871 | } else if (!IsInexpensiveConstant(loc)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 872 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
| 873 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 874 | } |
| 875 | } |
| 876 | |
| 877 | /* qsort callback function, sort descending */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 878 | static int SortCounts(const void *val1, const void *val2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 879 | const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); |
| 880 | const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); |
Brian Carlstrom | 4b8c13e | 2013-08-23 18:10:32 -0700 | [diff] [blame] | 881 | // Note that we fall back to sorting on reg so we get stable output |
| 882 | // on differing qsort implementations (such as on host and target or |
| 883 | // between local host and build servers). |
| 884 | return (op1->count == op2->count) |
| 885 | ? (op1->s_reg - op2->s_reg) |
| 886 | : (op1->count < op2->count ? 1 : -1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 887 | } |
| 888 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 889 | void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 890 | LOG(INFO) << msg; |
| 891 | for (int i = 0; i < size; i++) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 892 | if ((arr[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 893 | LOG(INFO) << "s_reg[D" << (arr[i].s_reg & ~STARTING_DOUBLE_SREG) << "]: " << arr[i].count; |
| 894 | } else { |
| 895 | LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; |
| 896 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 897 | } |
| 898 | } |
| 899 | |
| 900 | /* |
| 901 | * Note: some portions of this code required even if the kPromoteRegs |
| 902 | * optimization is disabled. |
| 903 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 904 | void Mir2Lir::DoPromotion() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 905 | int dalvik_regs = cu_->num_dalvik_registers; |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 906 | int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 907 | const int promotion_threshold = 1; |
buzbee | d69835d | 2014-02-03 14:40:27 -0800 | [diff] [blame] | 908 | // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp |
| 909 | promotion_map_ = static_cast<PromotionMap*> |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame^] | 910 | (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 911 | |
| 912 | // Allow target code to add any special registers |
| 913 | AdjustSpillMask(); |
| 914 | |
| 915 | /* |
| 916 | * Simple register promotion. Just do a static count of the uses |
| 917 | * of Dalvik registers. Note that we examine the SSA names, but |
| 918 | * count based on original Dalvik register name. Count refs |
| 919 | * separately based on type in order to give allocation |
| 920 | * preference to fp doubles - which must be allocated sequential |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 921 | * physical single fp registers starting with an even-numbered |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 922 | * reg. |
| 923 | * TUNING: replace with linear scan once we have the ability |
| 924 | * to describe register live ranges for GC. |
| 925 | */ |
| 926 | RefCounts *core_regs = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 927 | static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * num_regs, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame^] | 928 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 929 | RefCounts *FpRegs = |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 930 | static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * num_regs * 2, |
Vladimir Marko | 83cc7ae | 2014-02-12 18:02:05 +0000 | [diff] [blame^] | 931 | kArenaAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 932 | // Set ssa names for original Dalvik registers |
| 933 | for (int i = 0; i < dalvik_regs; i++) { |
| 934 | core_regs[i].s_reg = FpRegs[i].s_reg = i; |
| 935 | } |
Razvan A Lupusoru | da7a69b | 2014-01-08 15:09:50 -0800 | [diff] [blame] | 936 | |
| 937 | // Set ssa names for compiler temporaries |
| 938 | for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) { |
| 939 | CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx); |
| 940 | core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 941 | FpRegs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
| 942 | FpRegs[num_regs + dalvik_regs + ct_idx].s_reg = ct->s_reg_low; |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 943 | } |
| 944 | |
| 945 | // Duplicate in upper half to represent possible fp double starting sregs. |
| 946 | for (int i = 0; i < num_regs; i++) { |
| 947 | FpRegs[num_regs + i].s_reg = FpRegs[i].s_reg | STARTING_DOUBLE_SREG; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 948 | } |
| 949 | |
| 950 | // Sum use counts of SSA regs by original Dalvik vreg. |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 951 | CountRefs(core_regs, FpRegs, num_regs); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 952 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 953 | |
| 954 | // Sort the count arrays |
| 955 | qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 956 | qsort(FpRegs, num_regs * 2, sizeof(RefCounts), SortCounts); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 957 | |
| 958 | if (cu_->verbose) { |
| 959 | DumpCounts(core_regs, num_regs, "Core regs after sort"); |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 960 | DumpCounts(FpRegs, num_regs * 2, "Fp regs after sort"); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | if (!(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 964 | // Promote FpRegs |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 965 | for (int i = 0; (i < (num_regs * 2)) && (FpRegs[i].count >= promotion_threshold); i++) { |
| 966 | int p_map_idx = SRegToPMap(FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG); |
| 967 | if ((FpRegs[i].s_reg & STARTING_DOUBLE_SREG) != 0) { |
| 968 | if ((promotion_map_[p_map_idx].fp_location != kLocPhysReg) && |
| 969 | (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg)) { |
| 970 | int low_sreg = FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG; |
| 971 | // Ignore result - if can't alloc double may still be able to alloc singles. |
| 972 | AllocPreservedDouble(low_sreg); |
| 973 | } |
| 974 | } else if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { |
| 975 | int reg = AllocPreservedSingle(FpRegs[i].s_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 976 | if (reg < 0) { |
buzbee | c729a6b | 2013-09-14 16:04:31 -0700 | [diff] [blame] | 977 | break; // No more left. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 978 | } |
| 979 | } |
| 980 | } |
| 981 | |
| 982 | // Promote core regs |
| 983 | for (int i = 0; (i < num_regs) && |
| 984 | (core_regs[i].count >= promotion_threshold); i++) { |
| 985 | int p_map_idx = SRegToPMap(core_regs[i].s_reg); |
| 986 | if (promotion_map_[p_map_idx].core_location != |
| 987 | kLocPhysReg) { |
| 988 | int reg = AllocPreservedCoreReg(core_regs[i].s_reg); |
| 989 | if (reg < 0) { |
| 990 | break; // No more left |
| 991 | } |
| 992 | } |
| 993 | } |
| 994 | } |
| 995 | |
| 996 | // Now, update SSA names to new home locations |
| 997 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 998 | RegLocation *curr = &mir_graph_->reg_location_[i]; |
| 999 | int p_map_idx = SRegToPMap(curr->s_reg_low); |
| 1000 | if (!curr->wide) { |
| 1001 | if (curr->fp) { |
| 1002 | if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { |
| 1003 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1004 | curr->reg = RegStorage(RegStorage::k32BitSolo, promotion_map_[p_map_idx].FpReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1005 | curr->home = true; |
| 1006 | } |
| 1007 | } else { |
| 1008 | if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { |
| 1009 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1010 | curr->reg = RegStorage(RegStorage::k32BitSolo, promotion_map_[p_map_idx].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1011 | curr->home = true; |
| 1012 | } |
| 1013 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1014 | } else { |
| 1015 | if (curr->high_word) { |
| 1016 | continue; |
| 1017 | } |
| 1018 | if (curr->fp) { |
| 1019 | if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1020 | (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1021 | int low_reg = promotion_map_[p_map_idx].FpReg; |
| 1022 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 1023 | // Doubles require pair of singles starting at even reg |
| 1024 | if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { |
| 1025 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1026 | curr->reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1027 | curr->home = true; |
| 1028 | } |
| 1029 | } |
| 1030 | } else { |
| 1031 | if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) |
| 1032 | && (promotion_map_[p_map_idx+1].core_location == |
| 1033 | kLocPhysReg)) { |
| 1034 | curr->location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1035 | curr->reg = RegStorage(RegStorage::k64BitPair, promotion_map_[p_map_idx].core_reg, |
| 1036 | promotion_map_[p_map_idx+1].core_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1037 | curr->home = true; |
| 1038 | } |
| 1039 | } |
| 1040 | } |
| 1041 | } |
| 1042 | if (cu_->verbose) { |
| 1043 | DumpPromotionMap(); |
| 1044 | } |
| 1045 | } |
| 1046 | |
| 1047 | /* Returns sp-relative offset in bytes for a VReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1048 | int Mir2Lir::VRegOffset(int v_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1049 | return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, |
| 1050 | fp_spill_mask_, frame_size_, v_reg); |
| 1051 | } |
| 1052 | |
| 1053 | /* Returns sp-relative offset in bytes for a SReg */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1054 | int Mir2Lir::SRegOffset(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1055 | return VRegOffset(mir_graph_->SRegToVReg(s_reg)); |
| 1056 | } |
| 1057 | |
| 1058 | /* Mark register usage state and return long retloc */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1059 | RegLocation Mir2Lir::GetReturnWide(bool is_double) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1060 | RegLocation gpr_res = LocCReturnWide(); |
| 1061 | RegLocation fpr_res = LocCReturnDouble(); |
| 1062 | RegLocation res = is_double ? fpr_res : gpr_res; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1063 | Clobber(res.reg.GetReg()); |
| 1064 | Clobber(res.reg.GetHighReg()); |
| 1065 | LockTemp(res.reg.GetReg()); |
| 1066 | LockTemp(res.reg.GetHighReg()); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 1067 | // Does this wide value live in two registers or one vector register? |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1068 | if (res.reg.GetReg() != res.reg.GetHighReg()) { |
| 1069 | MarkPair(res.reg.GetReg(), res.reg.GetHighReg()); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 1070 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1071 | return res; |
| 1072 | } |
| 1073 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1074 | RegLocation Mir2Lir::GetReturn(bool is_float) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1075 | RegLocation gpr_res = LocCReturn(); |
| 1076 | RegLocation fpr_res = LocCReturnFloat(); |
| 1077 | RegLocation res = is_float ? fpr_res : gpr_res; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1078 | Clobber(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1079 | if (cu_->instruction_set == kMips) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1080 | MarkInUse(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1081 | } else { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1082 | LockTemp(res.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1083 | } |
| 1084 | return res; |
| 1085 | } |
| 1086 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1087 | void Mir2Lir::SimpleRegAlloc() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1088 | DoPromotion(); |
| 1089 | |
| 1090 | if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { |
| 1091 | LOG(INFO) << "After Promotion"; |
| 1092 | mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); |
| 1093 | } |
| 1094 | |
| 1095 | /* Set the frame size */ |
| 1096 | frame_size_ = ComputeFrameSize(); |
| 1097 | } |
| 1098 | |
| 1099 | /* |
| 1100 | * Get the "real" sreg number associated with an s_reg slot. In general, |
| 1101 | * s_reg values passed through codegen are the SSA names created by |
| 1102 | * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location |
| 1103 | * array. However, renaming is accomplished by simply replacing RegLocation |
| 1104 | * entries in the reglocation[] array. Therefore, when location |
| 1105 | * records for operands are first created, we need to ask the locRecord |
| 1106 | * identified by the dataflow pass what it's new name is. |
| 1107 | */ |
| 1108 | int Mir2Lir::GetSRegHi(int lowSreg) { |
| 1109 | return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; |
| 1110 | } |
| 1111 | |
| 1112 | bool Mir2Lir::oat_live_out(int s_reg) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 1113 | // For now. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1114 | return true; |
| 1115 | } |
| 1116 | |
| 1117 | int Mir2Lir::oatSSASrc(MIR* mir, int num) { |
| 1118 | DCHECK_GT(mir->ssa_rep->num_uses, num); |
| 1119 | return mir->ssa_rep->uses[num]; |
| 1120 | } |
| 1121 | |
| 1122 | } // namespace art |