Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Mips ISA */ |
| 18 | |
| 19 | #include "codegen_mips.h" |
Ian Rogers | d582fa4 | 2014-11-05 23:46:43 -0800 | [diff] [blame] | 20 | |
Andreas Gampe | 0b9203e | 2015-01-22 20:39:27 -0800 | [diff] [blame] | 21 | #include "base/logging.h" |
| 22 | #include "dex/mir_graph.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 24 | #include "dex/reg_storage_eq.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 25 | #include "entrypoints/quick/quick_entrypoints.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 26 | #include "mips_lir.h" |
Ian Rogers | 7e70b00 | 2014-10-08 11:47:24 -0700 | [diff] [blame] | 27 | #include "mirror/array-inl.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 28 | |
| 29 | namespace art { |
| 30 | |
| 31 | /* |
| 32 | * Compare two 64-bit values |
| 33 | * x = y return 0 |
| 34 | * x < y return -1 |
| 35 | * x > y return 1 |
| 36 | * |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 37 | * Mips32 implementation |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 38 | * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 |
| 39 | * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 |
| 40 | * subu res, t0, t1 # res = -1:1:0 for [ < > = ] |
| 41 | * bnez res, finish |
| 42 | * sltu t0, x.lo, y.lo |
| 43 | * sgtu r1, x.lo, y.lo |
| 44 | * subu res, t0, t1 |
| 45 | * finish: |
| 46 | * |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 47 | * Mips64 implementation |
| 48 | * slt temp, x, y; # (x < y) ? 1:0 |
| 49 | * slt res, y, x; # (x > y) ? 1:0 |
| 50 | * subu res, res, temp; # res = -1:1:0 for [ < > = ] |
| 51 | * |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 52 | */ |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 53 | void MipsMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 54 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 55 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 56 | if (cu_->target64) { |
| 57 | RegStorage temp = AllocTempWide(); |
| 58 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 59 | NewLIR3(kMipsSlt, temp.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
| 60 | NewLIR3(kMipsSlt, rl_result.reg.GetReg(), rl_src2.reg.GetReg(), rl_src1.reg.GetReg()); |
| 61 | NewLIR3(kMipsSubu, rl_result.reg.GetReg(), rl_result.reg.GetReg(), temp.GetReg()); |
| 62 | FreeTemp(temp); |
| 63 | StoreValue(rl_dest, rl_result); |
| 64 | } else { |
| 65 | RegStorage t0 = AllocTemp(); |
| 66 | RegStorage t1 = AllocTemp(); |
| 67 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 68 | NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); |
| 69 | NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg()); |
| 70 | NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg()); |
| 71 | LIR* branch = OpCmpImmBranch(kCondNe, rl_result.reg, 0, NULL); |
| 72 | NewLIR3(kMipsSltu, t0.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
| 73 | NewLIR3(kMipsSltu, t1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetLowReg()); |
| 74 | NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg()); |
| 75 | FreeTemp(t0); |
| 76 | FreeTemp(t1); |
| 77 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 78 | branch->target = target; |
| 79 | StoreValue(rl_dest, rl_result); |
| 80 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 81 | } |
| 82 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 83 | LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 84 | LIR* branch; |
| 85 | MipsOpCode slt_op; |
| 86 | MipsOpCode br_op; |
| 87 | bool cmp_zero = false; |
| 88 | bool swapped = false; |
| 89 | switch (cond) { |
| 90 | case kCondEq: |
| 91 | br_op = kMipsBeq; |
| 92 | cmp_zero = true; |
| 93 | break; |
| 94 | case kCondNe: |
| 95 | br_op = kMipsBne; |
| 96 | cmp_zero = true; |
| 97 | break; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 98 | case kCondUlt: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 99 | slt_op = kMipsSltu; |
| 100 | br_op = kMipsBnez; |
| 101 | break; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 102 | case kCondUge: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 103 | slt_op = kMipsSltu; |
| 104 | br_op = kMipsBeqz; |
| 105 | break; |
| 106 | case kCondGe: |
| 107 | slt_op = kMipsSlt; |
| 108 | br_op = kMipsBeqz; |
| 109 | break; |
| 110 | case kCondGt: |
| 111 | slt_op = kMipsSlt; |
| 112 | br_op = kMipsBnez; |
| 113 | swapped = true; |
| 114 | break; |
| 115 | case kCondLe: |
| 116 | slt_op = kMipsSlt; |
| 117 | br_op = kMipsBeqz; |
| 118 | swapped = true; |
| 119 | break; |
| 120 | case kCondLt: |
| 121 | slt_op = kMipsSlt; |
| 122 | br_op = kMipsBnez; |
| 123 | break; |
| 124 | case kCondHi: // Gtu |
| 125 | slt_op = kMipsSltu; |
| 126 | br_op = kMipsBnez; |
| 127 | swapped = true; |
| 128 | break; |
| 129 | default: |
| 130 | LOG(FATAL) << "No support for ConditionCode: " << cond; |
| 131 | return NULL; |
| 132 | } |
| 133 | if (cmp_zero) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 134 | branch = NewLIR2(br_op, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 135 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 136 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 137 | if (swapped) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 138 | NewLIR3(slt_op, t_reg.GetReg(), src2.GetReg(), src1.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 140 | NewLIR3(slt_op, t_reg.GetReg(), src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 141 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 142 | branch = NewLIR1(br_op, t_reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 143 | FreeTemp(t_reg); |
| 144 | } |
| 145 | branch->target = target; |
| 146 | return branch; |
| 147 | } |
| 148 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 149 | LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 150 | LIR* branch; |
| 151 | if (check_value != 0) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 152 | // TUNING: handle s16 & kCondLt/Mi case using slti. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 153 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 154 | LoadConstant(t_reg, check_value); |
| 155 | branch = OpCmpBranch(cond, reg, t_reg, target); |
| 156 | FreeTemp(t_reg); |
| 157 | return branch; |
| 158 | } |
| 159 | MipsOpCode opc; |
| 160 | switch (cond) { |
| 161 | case kCondEq: opc = kMipsBeqz; break; |
| 162 | case kCondGe: opc = kMipsBgez; break; |
| 163 | case kCondGt: opc = kMipsBgtz; break; |
| 164 | case kCondLe: opc = kMipsBlez; break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 165 | // case KCondMi: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 166 | case kCondLt: opc = kMipsBltz; break; |
| 167 | case kCondNe: opc = kMipsBnez; break; |
| 168 | default: |
| 169 | // Tuning: use slti when applicable |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 170 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 171 | LoadConstant(t_reg, check_value); |
| 172 | branch = OpCmpBranch(cond, reg, t_reg, target); |
| 173 | FreeTemp(t_reg); |
| 174 | return branch; |
| 175 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 176 | branch = NewLIR1(opc, reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 177 | branch->target = target; |
| 178 | return branch; |
| 179 | } |
| 180 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 181 | LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 182 | LIR* res; |
| 183 | MipsOpCode opcode; |
| 184 | |
| 185 | if (!cu_->target64) { |
| 186 | // If src or dest is a pair, we'll be using low reg. |
| 187 | if (r_dest.IsPair()) { |
| 188 | r_dest = r_dest.GetLow(); |
| 189 | } |
| 190 | if (r_src.IsPair()) { |
| 191 | r_src = r_src.GetLow(); |
| 192 | } |
| 193 | } else { |
| 194 | DCHECK(!r_dest.IsPair() && !r_src.IsPair()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 195 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 196 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 197 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 198 | return OpFpRegCopy(r_dest, r_src); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 199 | if (cu_->target64) { |
| 200 | // TODO: Check that r_src and r_dest are both 32 or both 64 bits length on Mips64. |
| 201 | if (r_dest.Is64Bit() || r_src.Is64Bit()) { |
| 202 | opcode = kMipsMove; |
| 203 | } else { |
| 204 | opcode = kMipsSll; |
| 205 | } |
| 206 | } else { |
| 207 | opcode = kMipsMove; |
| 208 | } |
| 209 | res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 210 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
| 211 | res->flags.is_nop = true; |
| 212 | } |
| 213 | return res; |
| 214 | } |
| 215 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 216 | void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 217 | if (r_dest != r_src) { |
| 218 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 219 | AppendLIR(res); |
| 220 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 221 | } |
| 222 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 223 | void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 224 | if (cu_->target64) { |
| 225 | OpRegCopy(r_dest, r_src); |
| 226 | return; |
| 227 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 228 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 229 | bool dest_fp = r_dest.IsFloat(); |
| 230 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 231 | if (dest_fp) { |
| 232 | if (src_fp) { |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 233 | // Here if both src and dest are fp registers. OpRegCopy will choose the right copy |
| 234 | // (solo or pair). |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 235 | OpRegCopy(r_dest, r_src); |
| 236 | } else { |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 237 | // note the operands are swapped for the mtc1 and mthc1 instr. |
| 238 | // Here if dest is fp reg and src is core reg. |
| 239 | if (fpuIs32Bit_) { |
| 240 | NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetLowReg()); |
| 241 | NewLIR2(kMipsMtc1, r_src.GetHighReg(), r_dest.GetHighReg()); |
| 242 | } else { |
| 243 | r_dest = Fp64ToSolo32(r_dest); |
| 244 | NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetReg()); |
| 245 | NewLIR2(kMipsMthc1, r_src.GetHighReg(), r_dest.GetReg()); |
| 246 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 247 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 248 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 249 | if (src_fp) { |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 250 | // Here if dest is core reg and src is fp reg. |
| 251 | if (fpuIs32Bit_) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 252 | NewLIR2(kMipsMfc1, r_dest.GetLowReg(), r_src.GetLowReg()); |
| 253 | NewLIR2(kMipsMfc1, r_dest.GetHighReg(), r_src.GetHighReg()); |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 254 | } else { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 255 | r_src = Fp64ToSolo32(r_src); |
| 256 | NewLIR2(kMipsMfc1, r_dest.GetLowReg(), r_src.GetReg()); |
| 257 | NewLIR2(kMipsMfhc1, r_dest.GetHighReg(), r_src.GetReg()); |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 258 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 259 | } else { |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 260 | // Here if both src and dest are core registers. |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 261 | // Handle overlap. |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 262 | if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 263 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 264 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 265 | } else { |
| 266 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 267 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 268 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 269 | } |
| 270 | } |
| 271 | } |
| 272 | } |
| 273 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 274 | void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 275 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 276 | RegisterClass dest_reg_class) { |
| 277 | UNUSED(dest_reg_class); |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 278 | // Implement as a branch-over. |
| 279 | // TODO: Conditional move? |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 280 | LoadConstant(rs_dest, true_val); |
Raghu Gandham | 08f8d4c | 2014-08-14 13:46:53 -0700 | [diff] [blame] | 281 | LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, NULL); |
| 282 | LoadConstant(rs_dest, false_val); |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 283 | LIR* target_label = NewLIR0(kPseudoTargetLabel); |
| 284 | ne_branchover->target = target_label; |
| 285 | } |
| 286 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 287 | void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 288 | UNUSED(bb, mir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 289 | UNIMPLEMENTED(FATAL) << "Need codegen for select"; |
| 290 | } |
| 291 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 292 | void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 293 | UNUSED(bb, mir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 294 | UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch"; |
| 295 | } |
| 296 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 297 | RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, |
Andreas Gampe | 8ebdc2b | 2015-01-14 12:09:25 -0800 | [diff] [blame] | 298 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 299 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 300 | |
| 301 | if (isaIsR6_) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 302 | NewLIR3(is_div ? kMipsR6Div : kMipsR6Mod, rl_result.reg.GetReg(), reg1.GetReg(), reg2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 303 | } else { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 304 | NewLIR2(kMipsR2Div, reg1.GetReg(), reg2.GetReg()); |
| 305 | NewLIR1(is_div ? kMipsR2Mflo : kMipsR2Mfhi, rl_result.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 306 | } |
| 307 | return rl_result; |
| 308 | } |
| 309 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 310 | RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 311 | RegStorage t_reg = AllocTemp(); |
| 312 | NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit); |
Douglas Leung | 027f0ff | 2015-02-27 19:05:03 -0800 | [diff] [blame] | 313 | RegLocation rl_result = GenDivRem(rl_dest, reg1, t_reg, is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 314 | FreeTemp(t_reg); |
| 315 | return rl_result; |
| 316 | } |
| 317 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 318 | RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 319 | bool is_div, int flags) { |
| 320 | UNUSED(rl_dest, rl_src1, rl_src2, is_div, flags); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 321 | LOG(FATAL) << "Unexpected use of GenDivRem for Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 322 | UNREACHABLE(); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 323 | } |
| 324 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 325 | RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, |
| 326 | bool is_div) { |
| 327 | UNUSED(rl_dest, rl_src1, lit, is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 328 | LOG(FATAL) << "Unexpected use of GenDivRemLit for Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 329 | UNREACHABLE(); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 330 | } |
| 331 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 332 | bool MipsMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 333 | UNUSED(info, is_long, is_object); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 334 | return false; |
| 335 | } |
| 336 | |
Vladimir Marko | 5030d3e | 2014-07-17 10:43:08 +0100 | [diff] [blame] | 337 | bool MipsMir2Lir::GenInlinedAbsFloat(CallInfo* info) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 338 | UNUSED(info); |
| 339 | // TODO: add Mips implementation. |
Vladimir Marko | 5030d3e | 2014-07-17 10:43:08 +0100 | [diff] [blame] | 340 | return false; |
| 341 | } |
| 342 | |
| 343 | bool MipsMir2Lir::GenInlinedAbsDouble(CallInfo* info) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 344 | UNUSED(info); |
| 345 | // TODO: add Mips implementation. |
Vladimir Marko | 5030d3e | 2014-07-17 10:43:08 +0100 | [diff] [blame] | 346 | return false; |
| 347 | } |
| 348 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 349 | bool MipsMir2Lir::GenInlinedSqrt(CallInfo* info) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 350 | UNUSED(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 351 | return false; |
| 352 | } |
| 353 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 354 | bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
| 355 | if (size != kSignedByte) { |
| 356 | // MIPS supports only aligned access. Defer unaligned access to JNI implementation. |
| 357 | return false; |
| 358 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 359 | RegLocation rl_src_address = info->args[0]; // Long address. |
| 360 | if (!cu_->target64) { |
| 361 | rl_src_address = NarrowRegLoc(rl_src_address); // Ignore high half in info->args[1]. |
| 362 | } |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 363 | RegLocation rl_dest = InlineTarget(info); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 364 | RegLocation rl_address; |
| 365 | if (cu_->target64) { |
| 366 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 367 | } else { |
| 368 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 369 | } |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 370 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 371 | DCHECK(size == kSignedByte); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 372 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 373 | StoreValue(rl_dest, rl_result); |
| 374 | return true; |
| 375 | } |
| 376 | |
| 377 | bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
| 378 | if (size != kSignedByte) { |
| 379 | // MIPS supports only aligned access. Defer unaligned access to JNI implementation. |
| 380 | return false; |
| 381 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 382 | RegLocation rl_src_address = info->args[0]; // Long address. |
| 383 | if (!cu_->target64) { |
| 384 | rl_src_address = NarrowRegLoc(rl_src_address); // Ignore high half in info->args[1]. |
| 385 | } |
| 386 | RegLocation rl_src_value = info->args[2]; // [size] value. |
| 387 | RegLocation rl_address; |
| 388 | if (cu_->target64) { |
| 389 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 390 | } else { |
| 391 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 392 | } |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 393 | DCHECK(size == kSignedByte); |
| 394 | RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 395 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 396 | return true; |
| 397 | } |
| 398 | |
Vladimir Marko | f6737f7 | 2015-03-23 17:05:14 +0000 | [diff] [blame] | 399 | void MipsMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 400 | UNUSED(reg, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | LOG(FATAL) << "Unexpected use of OpPcRelLoad for Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 402 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 403 | } |
| 404 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 405 | LIR* MipsMir2Lir::OpVldm(RegStorage r_base, int count) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 406 | UNUSED(r_base, count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 407 | LOG(FATAL) << "Unexpected use of OpVldm for Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 408 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 409 | } |
| 410 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 411 | LIR* MipsMir2Lir::OpVstm(RegStorage r_base, int count) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 412 | UNUSED(r_base, count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 413 | LOG(FATAL) << "Unexpected use of OpVstm for Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 414 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 415 | } |
| 416 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 417 | void MipsMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 418 | int first_bit, int second_bit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 419 | UNUSED(lit); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 420 | RegStorage t_reg = AllocTemp(); |
| 421 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 422 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 423 | FreeTemp(t_reg); |
| 424 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 425 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 426 | } |
| 427 | } |
| 428 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 429 | void MipsMir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 430 | if (cu_->target64) { |
| 431 | GenDivZeroCheck(reg); |
| 432 | } else { |
| 433 | DCHECK(reg.IsPair()); // TODO: support k64BitSolo. |
| 434 | RegStorage t_reg = AllocTemp(); |
| 435 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
| 436 | GenDivZeroCheck(t_reg); |
| 437 | FreeTemp(t_reg); |
| 438 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 439 | } |
| 440 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 441 | // Test suspend flag, return target of taken suspend branch. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 442 | LIR* MipsMir2Lir::OpTestSuspend(LIR* target) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 443 | OpRegImm(kOpSub, TargetPtrReg(kSuspend), 1); |
| 444 | return OpCmpImmBranch((target == NULL) ? kCondEq : kCondNe, TargetPtrReg(kSuspend), 0, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | } |
| 446 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 447 | // Decrement register and branch on condition. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 448 | LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 449 | OpRegImm(kOpSub, reg, 1); |
| 450 | return OpCmpImmBranch(c_code, reg, 0, target); |
| 451 | } |
| 452 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 453 | bool MipsMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 454 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 455 | UNUSED(dalvik_opcode, is_div, rl_src, rl_dest, lit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 456 | LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 457 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 458 | } |
| 459 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 460 | bool MipsMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 461 | UNUSED(rl_src, rl_dest, lit); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 462 | LOG(FATAL) << "Unexpected use of easyMultiply in Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 463 | UNREACHABLE(); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 464 | } |
| 465 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 466 | LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 467 | UNUSED(cond, guide); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 468 | LOG(FATAL) << "Unexpected use of OpIT in Mips"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 469 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 470 | } |
| 471 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 472 | void MipsMir2Lir::OpEndIT(LIR* it) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 473 | UNUSED(it); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 474 | LOG(FATAL) << "Unexpected use of OpEndIT in Mips"; |
| 475 | } |
| 476 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 477 | void MipsMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 478 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 479 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 480 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 481 | /* |
| 482 | * [v1 v0] = [a1 a0] + [a3 a2]; |
| 483 | * addu v0,a2,a0 |
| 484 | * addu t1,a3,a1 |
| 485 | * sltu v1,v0,a2 |
| 486 | * addu v1,v1,t1 |
| 487 | */ |
| 488 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 489 | OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src2.reg.GetLow(), rl_src1.reg.GetLow()); |
| 490 | RegStorage t_reg = AllocTemp(); |
| 491 | OpRegRegReg(kOpAdd, t_reg, rl_src2.reg.GetHigh(), rl_src1.reg.GetHigh()); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 492 | NewLIR3(kMipsSltu, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), |
| 493 | rl_src2.reg.GetLowReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 494 | OpRegRegReg(kOpAdd, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 495 | FreeTemp(t_reg); |
| 496 | StoreValueWide(rl_dest, rl_result); |
| 497 | } |
| 498 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 499 | void MipsMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 500 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 501 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 502 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 503 | /* |
| 504 | * [v1 v0] = [a1 a0] - [a3 a2]; |
| 505 | * sltu t1,a0,a2 |
| 506 | * subu v0,a0,a2 |
| 507 | * subu v1,a1,a3 |
| 508 | * subu v1,v1,t1 |
| 509 | */ |
| 510 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 511 | RegStorage t_reg = AllocTemp(); |
| 512 | NewLIR3(kMipsSltu, t_reg.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
| 513 | OpRegRegReg(kOpSub, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); |
| 514 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); |
| 515 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 516 | FreeTemp(t_reg); |
| 517 | StoreValueWide(rl_dest, rl_result); |
| 518 | } |
| 519 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 520 | void MipsMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 521 | RegLocation rl_src2, int flags) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 522 | if (cu_->target64) { |
| 523 | switch (opcode) { |
| 524 | case Instruction::NOT_LONG: |
| 525 | GenNotLong(rl_dest, rl_src2); |
| 526 | return; |
| 527 | case Instruction::ADD_LONG: |
| 528 | case Instruction::ADD_LONG_2ADDR: |
| 529 | GenLongOp(kOpAdd, rl_dest, rl_src1, rl_src2); |
| 530 | return; |
| 531 | case Instruction::SUB_LONG: |
| 532 | case Instruction::SUB_LONG_2ADDR: |
| 533 | GenLongOp(kOpSub, rl_dest, rl_src1, rl_src2); |
| 534 | return; |
| 535 | case Instruction::MUL_LONG: |
| 536 | case Instruction::MUL_LONG_2ADDR: |
| 537 | GenMulLong(rl_dest, rl_src1, rl_src2); |
| 538 | return; |
| 539 | case Instruction::DIV_LONG: |
| 540 | case Instruction::DIV_LONG_2ADDR: |
| 541 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true, flags); |
| 542 | return; |
| 543 | case Instruction::REM_LONG: |
| 544 | case Instruction::REM_LONG_2ADDR: |
| 545 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false, flags); |
| 546 | return; |
| 547 | case Instruction::AND_LONG: |
| 548 | case Instruction::AND_LONG_2ADDR: |
| 549 | GenLongOp(kOpAnd, rl_dest, rl_src1, rl_src2); |
| 550 | return; |
| 551 | case Instruction::OR_LONG: |
| 552 | case Instruction::OR_LONG_2ADDR: |
| 553 | GenLongOp(kOpOr, rl_dest, rl_src1, rl_src2); |
| 554 | return; |
| 555 | case Instruction::XOR_LONG: |
| 556 | case Instruction::XOR_LONG_2ADDR: |
| 557 | GenLongOp(kOpXor, rl_dest, rl_src1, rl_src2); |
| 558 | return; |
| 559 | case Instruction::NEG_LONG: |
| 560 | GenNegLong(rl_dest, rl_src2); |
| 561 | return; |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 562 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 563 | default: |
| 564 | LOG(FATAL) << "Invalid long arith op"; |
| 565 | return; |
| 566 | } |
| 567 | } else { |
| 568 | switch (opcode) { |
| 569 | case Instruction::ADD_LONG: |
| 570 | case Instruction::ADD_LONG_2ADDR: |
| 571 | GenAddLong(rl_dest, rl_src1, rl_src2); |
| 572 | return; |
| 573 | case Instruction::SUB_LONG: |
| 574 | case Instruction::SUB_LONG_2ADDR: |
| 575 | GenSubLong(rl_dest, rl_src1, rl_src2); |
| 576 | return; |
| 577 | case Instruction::NEG_LONG: |
| 578 | GenNegLong(rl_dest, rl_src2); |
| 579 | return; |
| 580 | default: |
| 581 | break; |
| 582 | } |
| 583 | // Fallback for all other ops. |
| 584 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 585 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 586 | } |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 587 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 588 | void MipsMir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, |
| 589 | RegLocation rl_src2) { |
| 590 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 591 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 592 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 593 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); |
| 594 | StoreValueWide(rl_dest, rl_result); |
| 595 | } |
| 596 | |
| 597 | void MipsMir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { |
| 598 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 599 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 600 | OpRegReg(kOpMvn, rl_result.reg, rl_src.reg); |
| 601 | StoreValueWide(rl_dest, rl_result); |
| 602 | } |
| 603 | |
| 604 | void MipsMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
| 605 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 606 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 607 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 608 | NewLIR3(kMips64Dmul, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
| 609 | StoreValueWide(rl_dest, rl_result); |
| 610 | } |
| 611 | |
| 612 | void MipsMir2Lir::GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 613 | RegLocation rl_src2, bool is_div, int flags) { |
| 614 | UNUSED(opcode); |
| 615 | // TODO: Implement easy div/rem? |
| 616 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 617 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 618 | if ((flags & MIR_IGNORE_DIV_ZERO_CHECK) == 0) { |
| 619 | GenDivZeroCheckWide(rl_src2.reg); |
| 620 | } |
| 621 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 622 | NewLIR3(is_div ? kMips64Ddiv : kMips64Dmod, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), |
| 623 | rl_src2.reg.GetReg()); |
| 624 | StoreValueWide(rl_dest, rl_result); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 625 | } |
| 626 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 627 | void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 628 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 629 | RegLocation rl_result; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 630 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 631 | if (cu_->target64) { |
| 632 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 633 | OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); |
| 634 | StoreValueWide(rl_dest, rl_result); |
| 635 | } else { |
| 636 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 637 | // [v1 v0] = -[a1 a0] |
| 638 | // negu v0,a0 |
| 639 | // negu v1,a1 |
| 640 | // sltu t1,r_zero |
| 641 | // subu v1,v1,t1 |
| 642 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
| 643 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 644 | RegStorage t_reg = AllocTemp(); |
| 645 | NewLIR3(kMipsSltu, t_reg.GetReg(), rZERO, rl_result.reg.GetLowReg()); |
| 646 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
| 647 | FreeTemp(t_reg); |
| 648 | StoreValueWide(rl_dest, rl_result); |
| 649 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 650 | } |
| 651 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 652 | /* |
| 653 | * Generate array load |
| 654 | */ |
| 655 | void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Andreas Gampe | 8ebdc2b | 2015-01-14 12:09:25 -0800 | [diff] [blame] | 656 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 657 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 658 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 659 | int data_offset; |
| 660 | RegLocation rl_result; |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 661 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 662 | rl_index = LoadValue(rl_index, kCoreReg); |
| 663 | |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 664 | // FIXME: need to add support for rl_index.is_const. |
| 665 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 666 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 667 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 668 | } else { |
| 669 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 670 | } |
| 671 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 672 | // Null object? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 673 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 674 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 675 | RegStorage reg_ptr = (cu_->target64) ? AllocTempRef() : AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 676 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 677 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 678 | if (needs_range_check) { |
| 679 | reg_len = AllocTemp(); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 680 | // Get len. |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 681 | Load32Disp(rl_array.reg, len_offset, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 682 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 683 | // reg_ptr -> array data. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 684 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 685 | FreeTemp(rl_array.reg); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 686 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 687 | if (scale) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 688 | RegStorage r_new_index = AllocTemp(); |
| 689 | OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 690 | OpRegReg(kOpAdd, reg_ptr, r_new_index); |
| 691 | FreeTemp(r_new_index); |
| 692 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 693 | OpRegReg(kOpAdd, reg_ptr, rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 694 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 695 | FreeTemp(rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 696 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 697 | |
| 698 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 699 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 700 | FreeTemp(reg_len); |
| 701 | } |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 702 | LoadBaseDisp(reg_ptr, 0, rl_result.reg, size, kNotVolatile); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 703 | |
| 704 | FreeTemp(reg_ptr); |
| 705 | StoreValueWide(rl_dest, rl_result); |
| 706 | } else { |
| 707 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 708 | |
| 709 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 710 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 711 | FreeTemp(reg_len); |
| 712 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 713 | |
| 714 | if (cu_->target64) { |
| 715 | if (rl_result.ref) { |
| 716 | LoadBaseIndexed(reg_ptr, As64BitReg(rl_index.reg), As32BitReg(rl_result.reg), scale, |
| 717 | kReference); |
| 718 | } else { |
| 719 | LoadBaseIndexed(reg_ptr, As64BitReg(rl_index.reg), rl_result.reg, scale, size); |
| 720 | } |
| 721 | } else { |
| 722 | LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); |
| 723 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 724 | |
| 725 | FreeTemp(reg_ptr); |
| 726 | StoreValue(rl_dest, rl_result); |
| 727 | } |
| 728 | } |
| 729 | |
| 730 | /* |
| 731 | * Generate array store |
| 732 | * |
| 733 | */ |
| 734 | void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Andreas Gampe | 8ebdc2b | 2015-01-14 12:09:25 -0800 | [diff] [blame] | 735 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 736 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 737 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 738 | int data_offset; |
| 739 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 740 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 741 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 742 | } else { |
| 743 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 744 | } |
| 745 | |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 746 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 747 | rl_index = LoadValue(rl_index, kCoreReg); |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 748 | |
| 749 | // FIXME: need to add support for rl_index.is_const. |
| 750 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 751 | RegStorage reg_ptr; |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 752 | bool allocated_reg_ptr_temp = false; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 753 | if (IsTemp(rl_array.reg) && !card_mark) { |
| 754 | Clobber(rl_array.reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 755 | reg_ptr = rl_array.reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 756 | } else { |
| 757 | reg_ptr = AllocTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 758 | OpRegCopy(reg_ptr, rl_array.reg); |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 759 | allocated_reg_ptr_temp = true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 760 | } |
| 761 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 762 | // Null object? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 763 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 764 | |
| 765 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 766 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 767 | if (needs_range_check) { |
| 768 | reg_len = AllocTemp(); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 769 | // NOTE: max live temps(4) here. |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 770 | // Get len. |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 771 | Load32Disp(rl_array.reg, len_offset, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 772 | } |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 773 | // reg_ptr -> array data. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 774 | OpRegImm(kOpAdd, reg_ptr, data_offset); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 775 | // At this point, reg_ptr points to array, 2 live temps. |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 776 | if ((size == k64) || (size == kDouble)) { |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 777 | // TUNING: specific wide routine that can handle fp regs. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 778 | if (scale) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 779 | RegStorage r_new_index = AllocTemp(); |
| 780 | OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 781 | OpRegReg(kOpAdd, reg_ptr, r_new_index); |
| 782 | FreeTemp(r_new_index); |
| 783 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 784 | OpRegReg(kOpAdd, reg_ptr, rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 785 | } |
| 786 | rl_src = LoadValueWide(rl_src, reg_class); |
| 787 | |
| 788 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 789 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 790 | FreeTemp(reg_len); |
| 791 | } |
| 792 | |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 793 | StoreBaseDisp(reg_ptr, 0, rl_src.reg, size, kNotVolatile); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 794 | } else { |
| 795 | rl_src = LoadValue(rl_src, reg_class); |
| 796 | if (needs_range_check) { |
Andreas Gampe | 8ebdc2b | 2015-01-14 12:09:25 -0800 | [diff] [blame] | 797 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 798 | FreeTemp(reg_len); |
| 799 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 800 | StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 801 | } |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 802 | if (allocated_reg_ptr_temp) { |
| 803 | FreeTemp(reg_ptr); |
| 804 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 805 | if (card_mark) { |
Vladimir Marko | 743b98c | 2014-11-24 19:45:41 +0000 | [diff] [blame] | 806 | MarkGCCard(opt_flags, rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 807 | } |
| 808 | } |
| 809 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 810 | void MipsMir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 811 | RegLocation rl_shift) { |
| 812 | if (!cu_->target64) { |
| 813 | Mir2Lir::GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); |
| 814 | return; |
| 815 | } |
| 816 | OpKind op = kOpBkpt; |
| 817 | switch (opcode) { |
| 818 | case Instruction::SHL_LONG: |
| 819 | case Instruction::SHL_LONG_2ADDR: |
| 820 | op = kOpLsl; |
| 821 | break; |
| 822 | case Instruction::SHR_LONG: |
| 823 | case Instruction::SHR_LONG_2ADDR: |
| 824 | op = kOpAsr; |
| 825 | break; |
| 826 | case Instruction::USHR_LONG: |
| 827 | case Instruction::USHR_LONG_2ADDR: |
| 828 | op = kOpLsr; |
| 829 | break; |
| 830 | default: |
| 831 | LOG(FATAL) << "Unexpected case: " << opcode; |
| 832 | } |
| 833 | rl_shift = LoadValue(rl_shift, kCoreReg); |
| 834 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 835 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 836 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg)); |
| 837 | StoreValueWide(rl_dest, rl_result); |
| 838 | } |
| 839 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 840 | void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 841 | RegLocation rl_src1, RegLocation rl_shift, int flags) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 842 | UNUSED(flags); |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 843 | if (!cu_->target64) { |
| 844 | // Default implementation is just to ignore the constant case. |
| 845 | GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); |
| 846 | return; |
| 847 | } |
| 848 | OpKind op = kOpBkpt; |
| 849 | // Per spec, we only care about low 6 bits of shift amount. |
| 850 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 851 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 852 | if (shift_amount == 0) { |
| 853 | StoreValueWide(rl_dest, rl_src1); |
| 854 | return; |
| 855 | } |
| 856 | |
| 857 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 858 | switch (opcode) { |
| 859 | case Instruction::SHL_LONG: |
| 860 | case Instruction::SHL_LONG_2ADDR: |
| 861 | op = kOpLsl; |
| 862 | break; |
| 863 | case Instruction::SHR_LONG: |
| 864 | case Instruction::SHR_LONG_2ADDR: |
| 865 | op = kOpAsr; |
| 866 | break; |
| 867 | case Instruction::USHR_LONG: |
| 868 | case Instruction::USHR_LONG_2ADDR: |
| 869 | op = kOpLsr; |
| 870 | break; |
| 871 | default: |
| 872 | LOG(FATAL) << "Unexpected case"; |
| 873 | } |
| 874 | OpRegRegImm(op, rl_result.reg, rl_src1.reg, shift_amount); |
| 875 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 876 | } |
| 877 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 878 | void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 879 | RegLocation rl_src1, RegLocation rl_src2, int flags) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 880 | // Default - bail to non-const handler. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 881 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Goran Jakovljevic | 1095793 | 2015-03-24 18:42:56 +0100 | [diff] [blame] | 884 | void MipsMir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { |
| 885 | if (!cu_->target64) { |
| 886 | Mir2Lir::GenIntToLong(rl_dest, rl_src); |
| 887 | return; |
| 888 | } |
| 889 | rl_src = LoadValue(rl_src, kCoreReg); |
| 890 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 891 | NewLIR3(kMipsSll, rl_result.reg.GetReg(), As64BitReg(rl_src.reg).GetReg(), 0); |
| 892 | StoreValueWide(rl_dest, rl_result); |
| 893 | } |
| 894 | |
| 895 | void MipsMir2Lir::GenConversionCall(QuickEntrypointEnum trampoline, RegLocation rl_dest, |
| 896 | RegLocation rl_src, RegisterClass reg_class) { |
| 897 | FlushAllRegs(); // Send everything to home location. |
| 898 | CallRuntimeHelperRegLocation(trampoline, rl_src, false); |
| 899 | if (rl_dest.wide) { |
| 900 | RegLocation rl_result; |
| 901 | rl_result = GetReturnWide(reg_class); |
| 902 | StoreValueWide(rl_dest, rl_result); |
| 903 | } else { |
| 904 | RegLocation rl_result; |
| 905 | rl_result = GetReturn(reg_class); |
| 906 | StoreValue(rl_dest, rl_result); |
| 907 | } |
| 908 | } |
| 909 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 910 | } // namespace art |