Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "assembler_arm64.h" |
| 18 | #include "base/logging.h" |
| 19 | #include "entrypoints/quick/quick_entrypoints.h" |
| 20 | #include "offsets.h" |
| 21 | #include "thread.h" |
| 22 | #include "utils.h" |
| 23 | |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 24 | using namespace vixl; // NOLINT(build/namespaces) |
| 25 | |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 26 | namespace art { |
| 27 | namespace arm64 { |
| 28 | |
| 29 | #ifdef ___ |
| 30 | #error "ARM64 Assembler macro already defined." |
| 31 | #else |
| 32 | #define ___ vixl_masm_-> |
| 33 | #endif |
| 34 | |
| 35 | void Arm64Assembler::EmitSlowPaths() { |
| 36 | if (!exception_blocks_.empty()) { |
| 37 | for (size_t i = 0; i < exception_blocks_.size(); i++) { |
| 38 | EmitExceptionPoll(exception_blocks_.at(i)); |
| 39 | } |
| 40 | } |
| 41 | ___ FinalizeCode(); |
| 42 | } |
| 43 | |
| 44 | size_t Arm64Assembler::CodeSize() const { |
Alexandre Rames | cee7524 | 2014-10-08 18:41:21 +0100 | [diff] [blame] | 45 | return vixl_masm_->BufferCapacity() - vixl_masm_->RemainingBufferSpace(); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | void Arm64Assembler::FinalizeInstructions(const MemoryRegion& region) { |
| 49 | // Copy the instructions from the buffer. |
Alexandre Rames | cee7524 | 2014-10-08 18:41:21 +0100 | [diff] [blame] | 50 | MemoryRegion from(vixl_masm_->GetStartAddress<void*>(), CodeSize()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 51 | region.CopyFrom(0, from); |
| 52 | } |
| 53 | |
| 54 | void Arm64Assembler::GetCurrentThread(ManagedRegister tr) { |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 55 | ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(TR)); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) { |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 59 | StoreToOffset(TR, SP, offset.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | // See Arm64 PCS Section 5.2.2.1. |
| 63 | void Arm64Assembler::IncreaseFrameSize(size_t adjust) { |
| 64 | CHECK_ALIGNED(adjust, kStackAlignment); |
| 65 | AddConstant(SP, -adjust); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 66 | cfi().AdjustCFAOffset(adjust); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | // See Arm64 PCS Section 5.2.2.1. |
| 70 | void Arm64Assembler::DecreaseFrameSize(size_t adjust) { |
| 71 | CHECK_ALIGNED(adjust, kStackAlignment); |
| 72 | AddConstant(SP, adjust); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 73 | cfi().AdjustCFAOffset(-adjust); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 74 | } |
| 75 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 76 | void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 77 | AddConstant(rd, rd, value, cond); |
| 78 | } |
| 79 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 80 | void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 81 | Condition cond) { |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 82 | if ((cond == al) || (cond == nv)) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 83 | // VIXL macro-assembler handles all variants. |
| 84 | ___ Add(reg_x(rd), reg_x(rn), value); |
| 85 | } else { |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 86 | // temp = rd + value |
| 87 | // rd = cond ? temp : rn |
| 88 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
| 89 | temps.Exclude(reg_x(rd), reg_x(rn)); |
| 90 | vixl::Register temp = temps.AcquireX(); |
| 91 | ___ Add(temp, reg_x(rn), value); |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 92 | ___ Csel(reg_x(rd), temp, reg_x(rd), cond); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 93 | } |
| 94 | } |
| 95 | |
| 96 | void Arm64Assembler::StoreWToOffset(StoreOperandType type, WRegister source, |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 97 | XRegister base, int32_t offset) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 98 | switch (type) { |
| 99 | case kStoreByte: |
| 100 | ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset)); |
| 101 | break; |
| 102 | case kStoreHalfword: |
| 103 | ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset)); |
| 104 | break; |
| 105 | case kStoreWord: |
| 106 | ___ Str(reg_w(source), MEM_OP(reg_x(base), offset)); |
| 107 | break; |
| 108 | default: |
| 109 | LOG(FATAL) << "UNREACHABLE"; |
| 110 | } |
| 111 | } |
| 112 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 113 | void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 114 | CHECK_NE(source, SP); |
| 115 | ___ Str(reg_x(source), MEM_OP(reg_x(base), offset)); |
| 116 | } |
| 117 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 118 | void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 119 | ___ Str(reg_s(source), MEM_OP(reg_x(base), offset)); |
| 120 | } |
| 121 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 122 | void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_t offset) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 123 | ___ Str(reg_d(source), MEM_OP(reg_x(base), offset)); |
| 124 | } |
| 125 | |
| 126 | void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) { |
| 127 | Arm64ManagedRegister src = m_src.AsArm64(); |
| 128 | if (src.IsNoRegister()) { |
| 129 | CHECK_EQ(0u, size); |
| 130 | } else if (src.IsWRegister()) { |
| 131 | CHECK_EQ(4u, size); |
| 132 | StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 133 | } else if (src.IsXRegister()) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 134 | CHECK_EQ(8u, size); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 135 | StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 136 | } else if (src.IsSRegister()) { |
| 137 | StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value()); |
| 138 | } else { |
| 139 | CHECK(src.IsDRegister()) << src; |
| 140 | StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value()); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | void Arm64Assembler::StoreRef(FrameOffset offs, ManagedRegister m_src) { |
| 145 | Arm64ManagedRegister src = m_src.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 146 | CHECK(src.IsXRegister()) << src; |
| 147 | StoreWToOffset(kStoreWord, src.AsOverlappingWRegister(), SP, |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 148 | offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | void Arm64Assembler::StoreRawPtr(FrameOffset offs, ManagedRegister m_src) { |
| 152 | Arm64ManagedRegister src = m_src.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 153 | CHECK(src.IsXRegister()) << src; |
| 154 | StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, |
| 158 | ManagedRegister m_scratch) { |
| 159 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 160 | CHECK(scratch.IsXRegister()) << scratch; |
| 161 | LoadImmediate(scratch.AsXRegister(), imm); |
| 162 | StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 163 | offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 164 | } |
| 165 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 166 | void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 167 | ManagedRegister m_scratch) { |
| 168 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 169 | CHECK(scratch.IsXRegister()) << scratch; |
| 170 | LoadImmediate(scratch.AsXRegister(), imm); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 171 | StoreToOffset(scratch.AsXRegister(), TR, offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 172 | } |
| 173 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 174 | void Arm64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> tr_offs, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 175 | FrameOffset fr_offs, |
| 176 | ManagedRegister m_scratch) { |
| 177 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 178 | CHECK(scratch.IsXRegister()) << scratch; |
| 179 | AddConstant(scratch.AsXRegister(), SP, fr_offs.Int32Value()); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 180 | StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 181 | } |
| 182 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 183 | void Arm64Assembler::StoreStackPointerToThread64(ThreadOffset<8> tr_offs) { |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 184 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
| 185 | vixl::Register temp = temps.AcquireX(); |
| 186 | ___ Mov(temp, reg_x(SP)); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 187 | ___ Str(temp, MEM_OP(reg_x(TR), tr_offs.Int32Value())); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | void Arm64Assembler::StoreSpanning(FrameOffset dest_off, ManagedRegister m_source, |
| 191 | FrameOffset in_off, ManagedRegister m_scratch) { |
| 192 | Arm64ManagedRegister source = m_source.AsArm64(); |
| 193 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 194 | StoreToOffset(source.AsXRegister(), SP, dest_off.Int32Value()); |
| 195 | LoadFromOffset(scratch.AsXRegister(), SP, in_off.Int32Value()); |
| 196 | StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | // Load routines. |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 200 | void Arm64Assembler::LoadImmediate(XRegister dest, int32_t value, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 201 | Condition cond) { |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 202 | if ((cond == al) || (cond == nv)) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 203 | ___ Mov(reg_x(dest), value); |
| 204 | } else { |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 205 | // temp = value |
| 206 | // rd = cond ? temp : rd |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 207 | if (value != 0) { |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 208 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
| 209 | temps.Exclude(reg_x(dest)); |
| 210 | vixl::Register temp = temps.AcquireX(); |
| 211 | ___ Mov(temp, value); |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 212 | ___ Csel(reg_x(dest), temp, reg_x(dest), cond); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 213 | } else { |
Alexandre Rames | ba9388c | 2014-08-22 14:08:36 +0100 | [diff] [blame] | 214 | ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), cond); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 215 | } |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | void Arm64Assembler::LoadWFromOffset(LoadOperandType type, WRegister dest, |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 220 | XRegister base, int32_t offset) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 221 | switch (type) { |
| 222 | case kLoadSignedByte: |
| 223 | ___ Ldrsb(reg_w(dest), MEM_OP(reg_x(base), offset)); |
| 224 | break; |
| 225 | case kLoadSignedHalfword: |
| 226 | ___ Ldrsh(reg_w(dest), MEM_OP(reg_x(base), offset)); |
| 227 | break; |
| 228 | case kLoadUnsignedByte: |
| 229 | ___ Ldrb(reg_w(dest), MEM_OP(reg_x(base), offset)); |
| 230 | break; |
| 231 | case kLoadUnsignedHalfword: |
| 232 | ___ Ldrh(reg_w(dest), MEM_OP(reg_x(base), offset)); |
| 233 | break; |
| 234 | case kLoadWord: |
| 235 | ___ Ldr(reg_w(dest), MEM_OP(reg_x(base), offset)); |
| 236 | break; |
| 237 | default: |
| 238 | LOG(FATAL) << "UNREACHABLE"; |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | // Note: We can extend this member by adding load type info - see |
| 243 | // sign extended A64 load variants. |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 244 | void Arm64Assembler::LoadFromOffset(XRegister dest, XRegister base, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 245 | int32_t offset) { |
| 246 | CHECK_NE(dest, SP); |
| 247 | ___ Ldr(reg_x(dest), MEM_OP(reg_x(base), offset)); |
| 248 | } |
| 249 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 250 | void Arm64Assembler::LoadSFromOffset(SRegister dest, XRegister base, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 251 | int32_t offset) { |
| 252 | ___ Ldr(reg_s(dest), MEM_OP(reg_x(base), offset)); |
| 253 | } |
| 254 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 255 | void Arm64Assembler::LoadDFromOffset(DRegister dest, XRegister base, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 256 | int32_t offset) { |
| 257 | ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset)); |
| 258 | } |
| 259 | |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 260 | void Arm64Assembler::Load(Arm64ManagedRegister dest, XRegister base, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 261 | int32_t offset, size_t size) { |
| 262 | if (dest.IsNoRegister()) { |
| 263 | CHECK_EQ(0u, size) << dest; |
| 264 | } else if (dest.IsWRegister()) { |
| 265 | CHECK_EQ(4u, size) << dest; |
| 266 | ___ Ldr(reg_w(dest.AsWRegister()), MEM_OP(reg_x(base), offset)); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 267 | } else if (dest.IsXRegister()) { |
| 268 | CHECK_NE(dest.AsXRegister(), SP) << dest; |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 269 | if (size == 4u) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 270 | ___ Ldr(reg_w(dest.AsOverlappingWRegister()), MEM_OP(reg_x(base), offset)); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 271 | } else { |
| 272 | CHECK_EQ(8u, size) << dest; |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 273 | ___ Ldr(reg_x(dest.AsXRegister()), MEM_OP(reg_x(base), offset)); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 274 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 275 | } else if (dest.IsSRegister()) { |
| 276 | ___ Ldr(reg_s(dest.AsSRegister()), MEM_OP(reg_x(base), offset)); |
| 277 | } else { |
| 278 | CHECK(dest.IsDRegister()) << dest; |
| 279 | ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset)); |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | void Arm64Assembler::Load(ManagedRegister m_dst, FrameOffset src, size_t size) { |
| 284 | return Load(m_dst.AsArm64(), SP, src.Int32Value(), size); |
| 285 | } |
| 286 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 287 | void Arm64Assembler::LoadFromThread64(ManagedRegister m_dst, ThreadOffset<8> src, size_t size) { |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 288 | return Load(m_dst.AsArm64(), TR, src.Int32Value(), size); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | void Arm64Assembler::LoadRef(ManagedRegister m_dst, FrameOffset offs) { |
| 292 | Arm64ManagedRegister dst = m_dst.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 293 | CHECK(dst.IsXRegister()) << dst; |
| 294 | LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | void Arm64Assembler::LoadRef(ManagedRegister m_dst, ManagedRegister m_base, |
| 298 | MemberOffset offs) { |
| 299 | Arm64ManagedRegister dst = m_dst.AsArm64(); |
| 300 | Arm64ManagedRegister base = m_base.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 301 | CHECK(dst.IsXRegister() && base.IsXRegister()); |
| 302 | LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(), |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 303 | offs.Int32Value()); |
Hiroshi Yamauchi | b88f0b1 | 2014-09-26 14:55:38 -0700 | [diff] [blame] | 304 | if (kPoisonHeapReferences) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 305 | WRegister ref_reg = dst.AsOverlappingWRegister(); |
Hiroshi Yamauchi | b88f0b1 | 2014-09-26 14:55:38 -0700 | [diff] [blame] | 306 | ___ Neg(reg_w(ref_reg), vixl::Operand(reg_w(ref_reg))); |
| 307 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) { |
| 311 | Arm64ManagedRegister dst = m_dst.AsArm64(); |
| 312 | Arm64ManagedRegister base = m_base.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 313 | CHECK(dst.IsXRegister() && base.IsXRegister()); |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 314 | // Remove dst and base form the temp list - higher level API uses IP1, IP0. |
| 315 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 316 | temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister())); |
| 317 | ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 318 | } |
| 319 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 320 | void Arm64Assembler::LoadRawPtrFromThread64(ManagedRegister m_dst, ThreadOffset<8> offs) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 321 | Arm64ManagedRegister dst = m_dst.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 322 | CHECK(dst.IsXRegister()) << dst; |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 323 | LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | // Copying routines. |
| 327 | void Arm64Assembler::Move(ManagedRegister m_dst, ManagedRegister m_src, size_t size) { |
| 328 | Arm64ManagedRegister dst = m_dst.AsArm64(); |
| 329 | Arm64ManagedRegister src = m_src.AsArm64(); |
| 330 | if (!dst.Equals(src)) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 331 | if (dst.IsXRegister()) { |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 332 | if (size == 4) { |
| 333 | CHECK(src.IsWRegister()); |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 334 | ___ Mov(reg_w(dst.AsOverlappingWRegister()), reg_w(src.AsWRegister())); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 335 | } else { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 336 | if (src.IsXRegister()) { |
| 337 | ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsXRegister())); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 338 | } else { |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 339 | ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsOverlappingXRegister())); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 340 | } |
| 341 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 342 | } else if (dst.IsWRegister()) { |
| 343 | CHECK(src.IsWRegister()) << src; |
| 344 | ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister())); |
| 345 | } else if (dst.IsSRegister()) { |
| 346 | CHECK(src.IsSRegister()) << src; |
| 347 | ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister())); |
| 348 | } else { |
| 349 | CHECK(dst.IsDRegister()) << dst; |
| 350 | CHECK(src.IsDRegister()) << src; |
| 351 | ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister())); |
| 352 | } |
| 353 | } |
| 354 | } |
| 355 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 356 | void Arm64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, |
| 357 | ThreadOffset<8> tr_offs, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 358 | ManagedRegister m_scratch) { |
| 359 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 360 | CHECK(scratch.IsXRegister()) << scratch; |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 361 | LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 362 | StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 363 | } |
| 364 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 365 | void Arm64Assembler::CopyRawPtrToThread64(ThreadOffset<8> tr_offs, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 366 | FrameOffset fr_offs, |
| 367 | ManagedRegister m_scratch) { |
| 368 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 369 | CHECK(scratch.IsXRegister()) << scratch; |
| 370 | LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value()); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 371 | StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | void Arm64Assembler::CopyRef(FrameOffset dest, FrameOffset src, |
| 375 | ManagedRegister m_scratch) { |
| 376 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 377 | CHECK(scratch.IsXRegister()) << scratch; |
| 378 | LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 379 | SP, src.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 380 | StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 381 | SP, dest.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 382 | } |
| 383 | |
| 384 | void Arm64Assembler::Copy(FrameOffset dest, FrameOffset src, |
| 385 | ManagedRegister m_scratch, size_t size) { |
| 386 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 387 | CHECK(scratch.IsXRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 388 | CHECK(size == 4 || size == 8) << size; |
| 389 | if (size == 4) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 390 | LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, src.Int32Value()); |
| 391 | StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, dest.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 392 | } else if (size == 8) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 393 | LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value()); |
| 394 | StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 395 | } else { |
| 396 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | void Arm64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, |
| 401 | ManagedRegister m_scratch, size_t size) { |
| 402 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
| 403 | Arm64ManagedRegister base = src_base.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 404 | CHECK(base.IsXRegister()) << base; |
| 405 | CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 406 | CHECK(size == 4 || size == 8) << size; |
| 407 | if (size == 4) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 408 | LoadWFromOffset(kLoadWord, scratch.AsWRegister(), base.AsXRegister(), |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 409 | src_offset.Int32Value()); |
| 410 | StoreWToOffset(kStoreWord, scratch.AsWRegister(), SP, dest.Int32Value()); |
| 411 | } else if (size == 8) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 412 | LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), src_offset.Int32Value()); |
| 413 | StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 414 | } else { |
| 415 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | void Arm64Assembler::Copy(ManagedRegister m_dest_base, Offset dest_offs, FrameOffset src, |
| 420 | ManagedRegister m_scratch, size_t size) { |
| 421 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
| 422 | Arm64ManagedRegister base = m_dest_base.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 423 | CHECK(base.IsXRegister()) << base; |
| 424 | CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 425 | CHECK(size == 4 || size == 8) << size; |
| 426 | if (size == 4) { |
| 427 | LoadWFromOffset(kLoadWord, scratch.AsWRegister(), SP, src.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 428 | StoreWToOffset(kStoreWord, scratch.AsWRegister(), base.AsXRegister(), |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 429 | dest_offs.Int32Value()); |
| 430 | } else if (size == 8) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 431 | LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value()); |
| 432 | StoreToOffset(scratch.AsXRegister(), base.AsXRegister(), dest_offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 433 | } else { |
| 434 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | void Arm64Assembler::Copy(FrameOffset /*dst*/, FrameOffset /*src_base*/, Offset /*src_offset*/, |
| 439 | ManagedRegister /*mscratch*/, size_t /*size*/) { |
| 440 | UNIMPLEMENTED(FATAL) << "Unimplemented Copy() variant"; |
| 441 | } |
| 442 | |
| 443 | void Arm64Assembler::Copy(ManagedRegister m_dest, Offset dest_offset, |
| 444 | ManagedRegister m_src, Offset src_offset, |
| 445 | ManagedRegister m_scratch, size_t size) { |
| 446 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
| 447 | Arm64ManagedRegister src = m_src.AsArm64(); |
| 448 | Arm64ManagedRegister dest = m_dest.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 449 | CHECK(dest.IsXRegister()) << dest; |
| 450 | CHECK(src.IsXRegister()) << src; |
| 451 | CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 452 | CHECK(size == 4 || size == 8) << size; |
| 453 | if (size == 4) { |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 454 | if (scratch.IsWRegister()) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 455 | LoadWFromOffset(kLoadWord, scratch.AsWRegister(), src.AsXRegister(), |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 456 | src_offset.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 457 | StoreWToOffset(kStoreWord, scratch.AsWRegister(), dest.AsXRegister(), |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 458 | dest_offset.Int32Value()); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 459 | } else { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 460 | LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), src.AsXRegister(), |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 461 | src_offset.Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 462 | StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), dest.AsXRegister(), |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 463 | dest_offset.Int32Value()); |
| 464 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 465 | } else if (size == 8) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 466 | LoadFromOffset(scratch.AsXRegister(), src.AsXRegister(), src_offset.Int32Value()); |
| 467 | StoreToOffset(scratch.AsXRegister(), dest.AsXRegister(), dest_offset.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 468 | } else { |
| 469 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | void Arm64Assembler::Copy(FrameOffset /*dst*/, Offset /*dest_offset*/, |
| 474 | FrameOffset /*src*/, Offset /*src_offset*/, |
| 475 | ManagedRegister /*scratch*/, size_t /*size*/) { |
| 476 | UNIMPLEMENTED(FATAL) << "Unimplemented Copy() variant"; |
| 477 | } |
| 478 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 479 | void Arm64Assembler::MemoryBarrier(ManagedRegister m_scratch ATTRIBUTE_UNUSED) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 480 | // TODO: Should we check that m_scratch is IP? - see arm. |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 481 | ___ Dmb(vixl::InnerShareable, vixl::BarrierAll); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 482 | } |
| 483 | |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 484 | void Arm64Assembler::SignExtend(ManagedRegister mreg, size_t size) { |
| 485 | Arm64ManagedRegister reg = mreg.AsArm64(); |
| 486 | CHECK(size == 1 || size == 2) << size; |
| 487 | CHECK(reg.IsWRegister()) << reg; |
| 488 | if (size == 1) { |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 489 | ___ Sxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 490 | } else { |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 491 | ___ Sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 492 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 493 | } |
| 494 | |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 495 | void Arm64Assembler::ZeroExtend(ManagedRegister mreg, size_t size) { |
| 496 | Arm64ManagedRegister reg = mreg.AsArm64(); |
| 497 | CHECK(size == 1 || size == 2) << size; |
| 498 | CHECK(reg.IsWRegister()) << reg; |
| 499 | if (size == 1) { |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 500 | ___ Uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 501 | } else { |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 502 | ___ Uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); |
Andreas Gampe | d110432 | 2014-05-01 14:38:56 -0700 | [diff] [blame] | 503 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | void Arm64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) { |
| 507 | // TODO: not validating references. |
| 508 | } |
| 509 | |
| 510 | void Arm64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { |
| 511 | // TODO: not validating references. |
| 512 | } |
| 513 | |
| 514 | void Arm64Assembler::Call(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) { |
| 515 | Arm64ManagedRegister base = m_base.AsArm64(); |
| 516 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 517 | CHECK(base.IsXRegister()) << base; |
| 518 | CHECK(scratch.IsXRegister()) << scratch; |
| 519 | LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), offs.Int32Value()); |
| 520 | ___ Blr(reg_x(scratch.AsXRegister())); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 521 | } |
| 522 | |
Andreas Gampe | c6ee54e | 2014-03-24 16:45:44 -0700 | [diff] [blame] | 523 | void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) { |
| 524 | Arm64ManagedRegister base = m_base.AsArm64(); |
| 525 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 526 | CHECK(base.IsXRegister()) << base; |
| 527 | CHECK(scratch.IsXRegister()) << scratch; |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 528 | // Remove base and scratch form the temp list - higher level API uses IP1, IP0. |
| 529 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 530 | temps.Exclude(reg_x(base.AsXRegister()), reg_x(scratch.AsXRegister())); |
| 531 | ___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); |
| 532 | ___ Br(reg_x(scratch.AsXRegister())); |
Andreas Gampe | c6ee54e | 2014-03-24 16:45:44 -0700 | [diff] [blame] | 533 | } |
| 534 | |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 535 | void Arm64Assembler::Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) { |
| 536 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 537 | CHECK(scratch.IsXRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 538 | // Call *(*(SP + base) + offset) |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 539 | LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, base.Int32Value()); |
| 540 | LoadFromOffset(scratch.AsXRegister(), scratch.AsXRegister(), offs.Int32Value()); |
| 541 | ___ Blr(reg_x(scratch.AsXRegister())); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 542 | } |
| 543 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 544 | void Arm64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*scratch*/) { |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 545 | UNIMPLEMENTED(FATAL) << "Unimplemented Call() variant"; |
| 546 | } |
| 547 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 548 | void Arm64Assembler::CreateHandleScopeEntry(ManagedRegister m_out_reg, FrameOffset handle_scope_offs, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 549 | ManagedRegister m_in_reg, bool null_allowed) { |
| 550 | Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); |
| 551 | Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 552 | // For now we only hold stale handle scope entries in x registers. |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 553 | CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg; |
| 554 | CHECK(out_reg.IsXRegister()) << out_reg; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 555 | if (null_allowed) { |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 556 | // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is |
| 557 | // the address in the handle scope holding the reference. |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 558 | // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) |
| 559 | if (in_reg.IsNoRegister()) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 560 | LoadWFromOffset(kLoadWord, out_reg.AsOverlappingWRegister(), SP, |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 561 | handle_scope_offs.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 562 | in_reg = out_reg; |
| 563 | } |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 564 | ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 565 | if (!out_reg.Equals(in_reg)) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 566 | LoadImmediate(out_reg.AsXRegister(), 0, eq); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 567 | } |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 568 | AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), ne); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 569 | } else { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 570 | AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), al); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 571 | } |
| 572 | } |
| 573 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 574 | void Arm64Assembler::CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handle_scope_offset, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 575 | ManagedRegister m_scratch, bool null_allowed) { |
| 576 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 577 | CHECK(scratch.IsXRegister()) << scratch; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 578 | if (null_allowed) { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 579 | LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 580 | handle_scope_offset.Int32Value()); |
| 581 | // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is |
| 582 | // the address in the handle scope holding the reference. |
| 583 | // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset) |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 584 | ___ Cmp(reg_w(scratch.AsOverlappingWRegister()), 0); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 585 | // Move this logic in add constants with flags. |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 586 | AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), ne); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 587 | } else { |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 588 | AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), al); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 589 | } |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 590 | StoreToOffset(scratch.AsXRegister(), SP, out_off.Int32Value()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 591 | } |
| 592 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 593 | void Arm64Assembler::LoadReferenceFromHandleScope(ManagedRegister m_out_reg, |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 594 | ManagedRegister m_in_reg) { |
| 595 | Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); |
| 596 | Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 597 | CHECK(out_reg.IsXRegister()) << out_reg; |
| 598 | CHECK(in_reg.IsXRegister()) << in_reg; |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 599 | vixl::Label exit; |
| 600 | if (!out_reg.Equals(in_reg)) { |
| 601 | // FIXME: Who sets the flags here? |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 602 | LoadImmediate(out_reg.AsXRegister(), 0, eq); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 603 | } |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 604 | ___ Cbz(reg_x(in_reg.AsXRegister()), &exit); |
| 605 | LoadFromOffset(out_reg.AsXRegister(), in_reg.AsXRegister(), 0); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 606 | ___ Bind(&exit); |
| 607 | } |
| 608 | |
| 609 | void Arm64Assembler::ExceptionPoll(ManagedRegister m_scratch, size_t stack_adjust) { |
| 610 | CHECK_ALIGNED(stack_adjust, kStackAlignment); |
| 611 | Arm64ManagedRegister scratch = m_scratch.AsArm64(); |
| 612 | Arm64Exception *current_exception = new Arm64Exception(scratch, stack_adjust); |
| 613 | exception_blocks_.push_back(current_exception); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 614 | LoadFromOffset(scratch.AsXRegister(), TR, Thread::ExceptionOffset<8>().Int32Value()); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 615 | ___ Cbnz(reg_x(scratch.AsXRegister()), current_exception->Entry()); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 616 | } |
| 617 | |
| 618 | void Arm64Assembler::EmitExceptionPoll(Arm64Exception *exception) { |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 619 | vixl::UseScratchRegisterScope temps(vixl_masm_); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 620 | temps.Exclude(reg_x(exception->scratch_.AsXRegister())); |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 621 | vixl::Register temp = temps.AcquireX(); |
| 622 | |
| 623 | // Bind exception poll entry. |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 624 | ___ Bind(exception->Entry()); |
| 625 | if (exception->stack_adjust_ != 0) { // Fix up the frame. |
| 626 | DecreaseFrameSize(exception->stack_adjust_); |
| 627 | } |
| 628 | // Pass exception object as argument. |
| 629 | // Don't care about preserving X0 as this won't return. |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 630 | ___ Mov(reg_x(X0), reg_x(exception->scratch_.AsXRegister())); |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 631 | ___ Ldr(temp, MEM_OP(reg_x(TR), QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value())); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 632 | |
Serban Constantinescu | 0f89dac | 2014-05-08 13:52:53 +0100 | [diff] [blame] | 633 | ___ Blr(temp); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 634 | // Call should never return. |
| 635 | ___ Brk(); |
| 636 | } |
| 637 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 638 | static inline dwarf::Reg DWARFReg(CPURegister reg) { |
| 639 | if (reg.IsFPRegister()) { |
| 640 | return dwarf::Reg::Arm64Fp(reg.code()); |
| 641 | } else { |
| 642 | DCHECK_LT(reg.code(), 31u); // X0 - X30. |
| 643 | return dwarf::Reg::Arm64Core(reg.code()); |
| 644 | } |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 645 | } |
| 646 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 647 | void Arm64Assembler::SpillRegisters(vixl::CPURegList registers, int offset) { |
| 648 | int size = registers.RegisterSizeInBytes(); |
| 649 | const Register sp = vixl_masm_->StackPointer(); |
| 650 | while (registers.Count() >= 2) { |
| 651 | const CPURegister& dst0 = registers.PopLowestIndex(); |
| 652 | const CPURegister& dst1 = registers.PopLowestIndex(); |
| 653 | ___ Stp(dst0, dst1, MemOperand(sp, offset)); |
| 654 | cfi_.RelOffset(DWARFReg(dst0), offset); |
| 655 | cfi_.RelOffset(DWARFReg(dst1), offset + size); |
| 656 | offset += 2 * size; |
| 657 | } |
| 658 | if (!registers.IsEmpty()) { |
| 659 | const CPURegister& dst0 = registers.PopLowestIndex(); |
| 660 | ___ Str(dst0, MemOperand(sp, offset)); |
| 661 | cfi_.RelOffset(DWARFReg(dst0), offset); |
| 662 | } |
| 663 | DCHECK(registers.IsEmpty()); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 664 | } |
| 665 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 666 | void Arm64Assembler::UnspillRegisters(vixl::CPURegList registers, int offset) { |
| 667 | int size = registers.RegisterSizeInBytes(); |
| 668 | const Register sp = vixl_masm_->StackPointer(); |
| 669 | while (registers.Count() >= 2) { |
| 670 | const CPURegister& dst0 = registers.PopLowestIndex(); |
| 671 | const CPURegister& dst1 = registers.PopLowestIndex(); |
| 672 | ___ Ldp(dst0, dst1, MemOperand(sp, offset)); |
| 673 | cfi_.Restore(DWARFReg(dst0)); |
| 674 | cfi_.Restore(DWARFReg(dst1)); |
| 675 | offset += 2 * size; |
| 676 | } |
| 677 | if (!registers.IsEmpty()) { |
| 678 | const CPURegister& dst0 = registers.PopLowestIndex(); |
| 679 | ___ Ldr(dst0, MemOperand(sp, offset)); |
| 680 | cfi_.Restore(DWARFReg(dst0)); |
| 681 | } |
| 682 | DCHECK(registers.IsEmpty()); |
| 683 | } |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 684 | |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 685 | void Arm64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 686 | const std::vector<ManagedRegister>& callee_save_regs, |
| 687 | const ManagedRegisterEntrySpills& entry_spills) { |
| 688 | // Setup VIXL CPURegList for callee-saves. |
| 689 | CPURegList core_reg_list(CPURegister::kRegister, kXRegSize, 0); |
| 690 | CPURegList fp_reg_list(CPURegister::kFPRegister, kDRegSize, 0); |
| 691 | for (auto r : callee_save_regs) { |
| 692 | Arm64ManagedRegister reg = r.AsArm64(); |
| 693 | if (reg.IsXRegister()) { |
| 694 | core_reg_list.Combine(reg_x(reg.AsXRegister()).code()); |
| 695 | } else { |
| 696 | DCHECK(reg.IsDRegister()); |
| 697 | fp_reg_list.Combine(reg_d(reg.AsDRegister()).code()); |
| 698 | } |
| 699 | } |
| 700 | size_t core_reg_size = core_reg_list.TotalSizeInBytes(); |
| 701 | size_t fp_reg_size = fp_reg_list.TotalSizeInBytes(); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 702 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 703 | // Increase frame to required size. |
| 704 | DCHECK_ALIGNED(frame_size, kStackAlignment); |
| 705 | DCHECK_GE(frame_size, core_reg_size + fp_reg_size + sizeof(StackReference<mirror::ArtMethod>)); |
Zheng Xu | b551fdc | 2014-07-25 11:49:42 +0800 | [diff] [blame] | 706 | IncreaseFrameSize(frame_size); |
| 707 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 708 | // Save callee-saves. |
| 709 | SpillRegisters(core_reg_list, frame_size - core_reg_size); |
| 710 | SpillRegisters(fp_reg_list, frame_size - core_reg_size - fp_reg_size); |
Sebastien Hertz | 7cde48c | 2015-01-20 16:06:43 +0100 | [diff] [blame] | 711 | |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 712 | DCHECK(core_reg_list.IncludesAliasOf(reg_x(TR))); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 713 | |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 714 | // Write StackReference<Method>. |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 715 | DCHECK(X0 == method_reg.AsArm64().AsXRegister()); |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 716 | DCHECK_EQ(4U, sizeof(StackReference<mirror::ArtMethod>)); |
| 717 | StoreWToOffset(StoreOperandType::kStoreWord, W0, SP, 0); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 718 | |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 719 | // Write out entry spills |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 720 | int32_t offset = frame_size + sizeof(StackReference<mirror::ArtMethod>); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 721 | for (size_t i = 0; i < entry_spills.size(); ++i) { |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 722 | Arm64ManagedRegister reg = entry_spills.at(i).AsArm64(); |
| 723 | if (reg.IsNoRegister()) { |
| 724 | // only increment stack offset. |
| 725 | ManagedRegisterSpill spill = entry_spills.at(i); |
| 726 | offset += spill.getSize(); |
Alexandre Rames | 37c92df | 2014-10-17 14:35:27 +0100 | [diff] [blame] | 727 | } else if (reg.IsXRegister()) { |
| 728 | StoreToOffset(reg.AsXRegister(), SP, offset); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 729 | offset += 8; |
| 730 | } else if (reg.IsWRegister()) { |
| 731 | StoreWToOffset(kStoreWord, reg.AsWRegister(), SP, offset); |
| 732 | offset += 4; |
| 733 | } else if (reg.IsDRegister()) { |
| 734 | StoreDToOffset(reg.AsDRegister(), SP, offset); |
| 735 | offset += 8; |
| 736 | } else if (reg.IsSRegister()) { |
| 737 | StoreSToOffset(reg.AsSRegister(), SP, offset); |
| 738 | offset += 4; |
| 739 | } |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 740 | } |
| 741 | } |
| 742 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 743 | void Arm64Assembler::RemoveFrame(size_t frame_size, |
| 744 | const std::vector<ManagedRegister>& callee_save_regs) { |
| 745 | // Setup VIXL CPURegList for callee-saves. |
| 746 | CPURegList core_reg_list(CPURegister::kRegister, kXRegSize, 0); |
| 747 | CPURegList fp_reg_list(CPURegister::kFPRegister, kDRegSize, 0); |
| 748 | for (auto r : callee_save_regs) { |
| 749 | Arm64ManagedRegister reg = r.AsArm64(); |
| 750 | if (reg.IsXRegister()) { |
| 751 | core_reg_list.Combine(reg_x(reg.AsXRegister()).code()); |
| 752 | } else { |
| 753 | DCHECK(reg.IsDRegister()); |
| 754 | fp_reg_list.Combine(reg_d(reg.AsDRegister()).code()); |
| 755 | } |
| 756 | } |
| 757 | size_t core_reg_size = core_reg_list.TotalSizeInBytes(); |
| 758 | size_t fp_reg_size = fp_reg_list.TotalSizeInBytes(); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 759 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 760 | // For now we only check that the size of the frame is large enough to hold spills and method |
| 761 | // reference. |
| 762 | DCHECK_GE(frame_size, core_reg_size + fp_reg_size + sizeof(StackReference<mirror::ArtMethod>)); |
| 763 | DCHECK_ALIGNED(frame_size, kStackAlignment); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 764 | |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 765 | DCHECK(core_reg_list.IncludesAliasOf(reg_x(TR))); |
Serban Constantinescu | 75b9113 | 2014-04-09 18:39:10 +0100 | [diff] [blame] | 766 | |
Zheng Xu | 69a5030 | 2015-04-14 20:04:41 +0800 | [diff] [blame] | 767 | cfi_.RememberState(); |
| 768 | |
| 769 | // Restore callee-saves. |
| 770 | UnspillRegisters(core_reg_list, frame_size - core_reg_size); |
| 771 | UnspillRegisters(fp_reg_list, frame_size - core_reg_size - fp_reg_size); |
Sebastien Hertz | 7cde48c | 2015-01-20 16:06:43 +0100 | [diff] [blame] | 772 | |
Zheng Xu | b551fdc | 2014-07-25 11:49:42 +0800 | [diff] [blame] | 773 | // Decrease frame size to start of callee saved regs. |
| 774 | DecreaseFrameSize(frame_size); |
| 775 | |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 776 | // Pop callee saved and return to LR. |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 777 | ___ Ret(); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 778 | |
| 779 | // The CFI should be restored for any code that follows the exit block. |
| 780 | cfi_.RestoreState(); |
| 781 | cfi_.DefCFAOffset(frame_size); |
Serban Constantinescu | ed8dd49 | 2014-02-11 14:15:10 +0000 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | } // namespace arm64 |
| 785 | } // namespace art |