Serban Constantinescu | e6622be | 2014-02-27 15:36:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm64.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 21 | #include <sstream> |
Serban Constantinescu | e6622be | 2014-02-27 15:36:47 +0000 | [diff] [blame] | 22 | |
| 23 | #include "base/logging.h" |
| 24 | #include "base/stringprintf.h" |
| 25 | #include "thread.h" |
| 26 | |
| 27 | namespace art { |
| 28 | namespace arm64 { |
| 29 | |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 30 | // This enumeration should mirror the declarations in |
| 31 | // runtime/arch/arm64/registers_arm64.h. We do not include that file to |
| 32 | // avoid a dependency on libart. |
| 33 | enum { |
Serban Constantinescu | 9bd88b0 | 2015-04-22 16:24:46 +0100 | [diff] [blame^] | 34 | TR = 19, |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 35 | IP0 = 16, |
| 36 | IP1 = 17, |
| 37 | FP = 29, |
| 38 | LR = 30 |
| 39 | }; |
| 40 | |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 41 | void CustomDisassembler::AppendRegisterNameToOutput( |
| 42 | const vixl::Instruction* instr, |
| 43 | const vixl::CPURegister& reg) { |
| 44 | USE(instr); |
Alexandre Rames | d737ab3 | 2015-03-06 09:11:12 +0000 | [diff] [blame] | 45 | if (reg.IsRegister() && reg.Is64Bits()) { |
| 46 | if (reg.code() == TR) { |
| 47 | AppendToOutput("tr"); |
| 48 | return; |
| 49 | } else if (reg.code() == LR) { |
| 50 | AppendToOutput("lr"); |
| 51 | return; |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 52 | } |
Alexandre Rames | d737ab3 | 2015-03-06 09:11:12 +0000 | [diff] [blame] | 53 | // Fall through. |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 54 | } |
| 55 | // Print other register names as usual. |
| 56 | Disassembler::AppendRegisterNameToOutput(instr, reg); |
| 57 | } |
| 58 | |
| 59 | void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) { |
| 60 | Disassembler::VisitLoadLiteral(instr); |
| 61 | |
| 62 | if (!read_literals_) { |
| 63 | return; |
| 64 | } |
| 65 | |
Serban Constantinescu | 32f5b4d | 2014-11-25 20:05:46 +0000 | [diff] [blame] | 66 | void* data_address = instr->LiteralAddress<void*>(); |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 67 | vixl::Instr op = instr->Mask(vixl::LoadLiteralMask); |
| 68 | |
| 69 | switch (op) { |
| 70 | case vixl::LDR_w_lit: |
| 71 | case vixl::LDR_x_lit: |
| 72 | case vixl::LDRSW_x_lit: { |
| 73 | int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address) |
| 74 | : *reinterpret_cast<int32_t*>(data_address); |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 75 | AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data); |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 76 | break; |
| 77 | } |
| 78 | case vixl::LDR_s_lit: |
| 79 | case vixl::LDR_d_lit: { |
| 80 | double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address) |
| 81 | : *reinterpret_cast<double*>(data_address); |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 82 | AppendToOutput(" (%g)", data); |
Alexandre Rames | a37d925 | 2014-10-27 11:28:14 +0000 | [diff] [blame] | 83 | break; |
| 84 | } |
| 85 | default: |
| 86 | break; |
| 87 | } |
| 88 | } |
| 89 | |
Zheng Xu | a34e760 | 2015-02-03 12:03:15 +0800 | [diff] [blame] | 90 | void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) { |
| 91 | Disassembler::VisitLoadStoreUnsignedOffset(instr); |
| 92 | |
| 93 | if (instr->Rn() == TR) { |
| 94 | int64_t offset = instr->ImmLSUnsigned() << instr->SizeLS(); |
| 95 | std::ostringstream tmp_stream; |
| 96 | Thread::DumpThreadOffset<8>(tmp_stream, static_cast<uint32_t>(offset)); |
| 97 | AppendToOutput(" (%s)", tmp_stream.str().c_str()); |
| 98 | } |
| 99 | } |
| 100 | |
Serban Constantinescu | e6622be | 2014-02-27 15:36:47 +0000 | [diff] [blame] | 101 | size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) { |
Alexandre Rames | fef019c | 2014-10-10 17:14:18 +0100 | [diff] [blame] | 102 | const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin); |
| 103 | decoder.Decode(instr); |
Alexandre Rames | d737ab3 | 2015-03-06 09:11:12 +0000 | [diff] [blame] | 104 | os << FormatInstructionPointer(begin) |
Alexandre Rames | fef019c | 2014-10-10 17:14:18 +0100 | [diff] [blame] | 105 | << StringPrintf(": %08x\t%s\n", instr->InstructionBits(), disasm.GetOutput()); |
Serban Constantinescu | e6622be | 2014-02-27 15:36:47 +0000 | [diff] [blame] | 106 | return vixl::kInstructionSize; |
| 107 | } |
| 108 | |
| 109 | void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 110 | for (const uint8_t* cur = begin; cur < end; cur += vixl::kInstructionSize) { |
| 111 | Dump(os, cur); |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | } // namespace arm64 |
| 116 | } // namespace art |