blob: 058b89c499e6a9216b526e79d58f14c578f63e4c [file] [log] [blame]
Brian Carlstrom7940e442013-07-12 13:46:57 -07001/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17/* This file contains register alloction support. */
18
19#include "dex/compiler_ir.h"
20#include "dex/compiler_internals.h"
21#include "mir_to_lir-inl.h"
22
23namespace art {
24
25/*
26 * Free all allocated temps in the temp pools. Note that this does
27 * not affect the "liveness" of a temp register, which will stay
28 * live until it is either explicitly killed or reallocated.
29 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -070030void Mir2Lir::ResetRegPool() {
buzbeebd663de2013-09-10 15:41:31 -070031 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_);
32 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) {
buzbee091cc402014-03-31 10:14:40 -070033 info->MarkFree();
Brian Carlstrom7940e442013-07-12 13:46:57 -070034 }
35 // Reset temp tracking sanity check.
36 if (kIsDebugBuild) {
37 live_sreg_ = INVALID_SREG;
38 }
39}
40
buzbee091cc402014-03-31 10:14:40 -070041Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, uint64_t mask)
buzbee30adc732014-05-09 15:10:18 -070042 : reg_(r), is_temp_(false), wide_value_(false), dirty_(false), aliased_(false), partner_(r),
buzbeeba574512014-05-12 15:13:16 -070043 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr),
44 def_end_(nullptr), alias_chain_(nullptr) {
buzbee091cc402014-03-31 10:14:40 -070045 switch (r.StorageSize()) {
46 case 0: storage_mask_ = 0xffffffff; break;
47 case 4: storage_mask_ = 0x00000001; break;
48 case 8: storage_mask_ = 0x00000003; break;
49 case 16: storage_mask_ = 0x0000000f; break;
50 case 32: storage_mask_ = 0x000000ff; break;
51 case 64: storage_mask_ = 0x0000ffff; break;
52 case 128: storage_mask_ = 0xffffffff; break;
Brian Carlstrom7940e442013-07-12 13:46:57 -070053 }
buzbee091cc402014-03-31 10:14:40 -070054 used_storage_ = r.Valid() ? ~storage_mask_ : storage_mask_;
buzbee30adc732014-05-09 15:10:18 -070055 liveness_ = used_storage_;
Brian Carlstrom7940e442013-07-12 13:46:57 -070056}
57
buzbee091cc402014-03-31 10:14:40 -070058Mir2Lir::RegisterPool::RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena,
59 const std::vector<RegStorage>& core_regs,
buzbeeb01bf152014-05-13 15:59:07 -070060 const std::vector<RegStorage>& core64_regs,
buzbee091cc402014-03-31 10:14:40 -070061 const std::vector<RegStorage>& sp_regs,
62 const std::vector<RegStorage>& dp_regs,
63 const std::vector<RegStorage>& reserved_regs,
buzbeeb01bf152014-05-13 15:59:07 -070064 const std::vector<RegStorage>& reserved64_regs,
buzbee091cc402014-03-31 10:14:40 -070065 const std::vector<RegStorage>& core_temps,
buzbeeb01bf152014-05-13 15:59:07 -070066 const std::vector<RegStorage>& core64_temps,
buzbee091cc402014-03-31 10:14:40 -070067 const std::vector<RegStorage>& sp_temps,
68 const std::vector<RegStorage>& dp_temps) :
buzbeeb01bf152014-05-13 15:59:07 -070069 core_regs_(arena, core_regs.size()), next_core_reg_(0),
70 core64_regs_(arena, core64_regs.size()), next_core64_reg_(0),
71 sp_regs_(arena, sp_regs.size()), next_sp_reg_(0),
72 dp_regs_(arena, dp_regs.size()), next_dp_reg_(0), m2l_(m2l) {
buzbee091cc402014-03-31 10:14:40 -070073 // Initialize the fast lookup map.
74 m2l_->reginfo_map_.Reset();
buzbeeba574512014-05-12 15:13:16 -070075 if (kIsDebugBuild) {
76 m2l_->reginfo_map_.Resize(RegStorage::kMaxRegs);
77 for (unsigned i = 0; i < RegStorage::kMaxRegs; i++) {
78 m2l_->reginfo_map_.Insert(nullptr);
79 }
80 } else {
81 m2l_->reginfo_map_.SetSize(RegStorage::kMaxRegs);
buzbee091cc402014-03-31 10:14:40 -070082 }
83
84 // Construct the register pool.
85 for (RegStorage reg : core_regs) {
86 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
87 m2l_->reginfo_map_.Put(reg.GetReg(), info);
88 core_regs_.Insert(info);
89 }
buzbeeb01bf152014-05-13 15:59:07 -070090 for (RegStorage reg : core64_regs) {
91 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
92 m2l_->reginfo_map_.Put(reg.GetReg(), info);
93 core64_regs_.Insert(info);
94 }
buzbee091cc402014-03-31 10:14:40 -070095 for (RegStorage reg : sp_regs) {
96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
97 m2l_->reginfo_map_.Put(reg.GetReg(), info);
98 sp_regs_.Insert(info);
99 }
100 for (RegStorage reg : dp_regs) {
101 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg));
102 m2l_->reginfo_map_.Put(reg.GetReg(), info);
103 dp_regs_.Insert(info);
104 }
105
106 // Keep special registers from being allocated.
107 for (RegStorage reg : reserved_regs) {
108 m2l_->MarkInUse(reg);
109 }
buzbeeb01bf152014-05-13 15:59:07 -0700110 for (RegStorage reg : reserved64_regs) {
111 m2l_->MarkInUse(reg);
112 }
buzbee091cc402014-03-31 10:14:40 -0700113
114 // Mark temp regs - all others not in use can be used for promotion
115 for (RegStorage reg : core_temps) {
116 m2l_->MarkTemp(reg);
117 }
buzbeeb01bf152014-05-13 15:59:07 -0700118 for (RegStorage reg : core64_temps) {
119 m2l_->MarkTemp(reg);
120 }
buzbee091cc402014-03-31 10:14:40 -0700121 for (RegStorage reg : sp_temps) {
122 m2l_->MarkTemp(reg);
123 }
124 for (RegStorage reg : dp_temps) {
125 m2l_->MarkTemp(reg);
126 }
127
128 // Add an entry for InvalidReg with zero'd mask.
129 RegisterInfo* invalid_reg = new (arena) RegisterInfo(RegStorage::InvalidReg(), 0);
130 m2l_->reginfo_map_.Put(RegStorage::InvalidReg().GetReg(), invalid_reg);
131}
132
133void Mir2Lir::DumpRegPool(GrowableArray<RegisterInfo*>* regs) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700134 LOG(INFO) << "================================================";
buzbee091cc402014-03-31 10:14:40 -0700135 GrowableArray<RegisterInfo*>::Iterator it(regs);
136 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700137 LOG(INFO) << StringPrintf(
buzbee091cc402014-03-31 10:14:40 -0700138 "R[%d:%d:%c]: T:%d, U:%d, W:%d, p:%d, LV:%d, D:%d, SR:%d, DEF:%d",
139 info->GetReg().GetReg(), info->GetReg().GetRegNum(), info->GetReg().IsFloat() ? 'f' : 'c',
140 info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(),
141 info->IsDirty(), info->SReg(), info->DefStart() != nullptr);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700142 }
143 LOG(INFO) << "================================================";
144}
145
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700146void Mir2Lir::DumpCoreRegPool() {
buzbee091cc402014-03-31 10:14:40 -0700147 DumpRegPool(&reg_pool_->core_regs_);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700148}
149
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700150void Mir2Lir::DumpFpRegPool() {
buzbee091cc402014-03-31 10:14:40 -0700151 DumpRegPool(&reg_pool_->sp_regs_);
152 DumpRegPool(&reg_pool_->dp_regs_);
153}
154
155void Mir2Lir::DumpRegPools() {
156 LOG(INFO) << "Core registers";
157 DumpCoreRegPool();
158 LOG(INFO) << "FP registers";
159 DumpFpRegPool();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700160}
161
buzbee2700f7e2014-03-07 09:46:20 -0800162void Mir2Lir::Clobber(RegStorage reg) {
buzbeeba574512014-05-12 15:13:16 -0700163 if (UNLIKELY(reg.IsPair())) {
buzbee30adc732014-05-09 15:10:18 -0700164 DCHECK(!GetRegInfo(reg.GetLow())->IsAliased());
buzbeeba574512014-05-12 15:13:16 -0700165 Clobber(reg.GetLow());
buzbee30adc732014-05-09 15:10:18 -0700166 DCHECK(!GetRegInfo(reg.GetHigh())->IsAliased());
buzbeeba574512014-05-12 15:13:16 -0700167 Clobber(reg.GetHigh());
buzbee2700f7e2014-03-07 09:46:20 -0800168 } else {
buzbee30adc732014-05-09 15:10:18 -0700169 RegisterInfo* info = GetRegInfo(reg);
buzbeeba574512014-05-12 15:13:16 -0700170 if (info->IsTemp() && !info->IsDead()) {
buzbee082833c2014-05-17 23:16:26 -0700171 if (info->GetReg() != info->Partner()) {
172 ClobberBody(GetRegInfo(info->Partner()));
173 }
buzbeeba574512014-05-12 15:13:16 -0700174 ClobberBody(info);
175 if (info->IsAliased()) {
buzbee642fe342014-05-23 16:04:08 -0700176 ClobberAliases(info, info->StorageMask());
buzbeeba574512014-05-12 15:13:16 -0700177 } else {
178 RegisterInfo* master = info->Master();
179 if (info != master) {
180 ClobberBody(info->Master());
buzbee642fe342014-05-23 16:04:08 -0700181 ClobberAliases(info->Master(), info->StorageMask());
buzbeeba574512014-05-12 15:13:16 -0700182 }
183 }
buzbee30adc732014-05-09 15:10:18 -0700184 }
buzbee2700f7e2014-03-07 09:46:20 -0800185 }
186}
187
buzbee642fe342014-05-23 16:04:08 -0700188void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask) {
buzbeeba574512014-05-12 15:13:16 -0700189 for (RegisterInfo* alias = info->GetAliasChain(); alias != nullptr;
190 alias = alias->GetAliasChain()) {
191 DCHECK(!alias->IsAliased()); // Only the master should be marked as alised.
buzbee642fe342014-05-23 16:04:08 -0700192 // Only clobber if we have overlap.
193 if ((alias->StorageMask() & clobber_mask) != 0) {
194 ClobberBody(alias);
195 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700196 }
197}
198
199/*
200 * Break the association between a Dalvik vreg and a physical temp register of either register
201 * class.
202 * TODO: Ideally, the public version of this code should not exist. Besides its local usage
203 * in the register utilities, is is also used by code gen routines to work around a deficiency in
204 * local register allocation, which fails to distinguish between the "in" and "out" identities
205 * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg
206 * is used both as the source and destination register of an operation in which the type
207 * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is
208 * addressed.
209 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700210void Mir2Lir::ClobberSReg(int s_reg) {
buzbee091cc402014-03-31 10:14:40 -0700211 if (s_reg != INVALID_SREG) {
buzbee30adc732014-05-09 15:10:18 -0700212 if (kIsDebugBuild && s_reg == live_sreg_) {
213 live_sreg_ = INVALID_SREG;
214 }
215 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_);
216 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) {
217 if (info->SReg() == s_reg) {
buzbee082833c2014-05-17 23:16:26 -0700218 if (info->GetReg() != info->Partner()) {
219 // Dealing with a pair - clobber the other half.
220 DCHECK(!info->IsAliased());
221 ClobberBody(GetRegInfo(info->Partner()));
222 }
buzbeeba574512014-05-12 15:13:16 -0700223 ClobberBody(info);
buzbee30adc732014-05-09 15:10:18 -0700224 if (info->IsAliased()) {
buzbee642fe342014-05-23 16:04:08 -0700225 ClobberAliases(info, info->StorageMask());
buzbee30adc732014-05-09 15:10:18 -0700226 }
buzbee091cc402014-03-31 10:14:40 -0700227 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700228 }
229 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700230}
231
232/*
233 * SSA names associated with the initial definitions of Dalvik
234 * registers are the same as the Dalvik register number (and
235 * thus take the same position in the promotion_map. However,
236 * the special Method* and compiler temp resisters use negative
237 * v_reg numbers to distinguish them and can have an arbitrary
238 * ssa name (above the last original Dalvik register). This function
239 * maps SSA names to positions in the promotion_map array.
240 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700241int Mir2Lir::SRegToPMap(int s_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700242 DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs());
243 DCHECK_GE(s_reg, 0);
244 int v_reg = mir_graph_->SRegToVReg(s_reg);
245 if (v_reg >= 0) {
246 DCHECK_LT(v_reg, cu_->num_dalvik_registers);
247 return v_reg;
248 } else {
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -0800249 /*
250 * It must be the case that the v_reg for temporary is less than or equal to the
251 * base reg for temps. For that reason, "position" must be zero or positive.
252 */
253 unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg));
254
255 // The temporaries are placed after dalvik registers in the promotion map
256 DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps());
257 return cu_->num_dalvik_registers + position;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700258 }
259}
260
buzbee091cc402014-03-31 10:14:40 -0700261// TODO: refactor following Alloc/Record routines - much commonality.
buzbee2700f7e2014-03-07 09:46:20 -0800262void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700263 int p_map_idx = SRegToPMap(s_reg);
264 int v_reg = mir_graph_->SRegToVReg(s_reg);
buzbee091cc402014-03-31 10:14:40 -0700265 int reg_num = reg.GetRegNum();
266 GetRegInfo(reg)->MarkInUse();
buzbee2700f7e2014-03-07 09:46:20 -0800267 core_spill_mask_ |= (1 << reg_num);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700268 // Include reg for later sort
buzbee2700f7e2014-03-07 09:46:20 -0800269 core_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1)));
Brian Carlstrom7940e442013-07-12 13:46:57 -0700270 num_core_spills_++;
271 promotion_map_[p_map_idx].core_location = kLocPhysReg;
buzbee2700f7e2014-03-07 09:46:20 -0800272 promotion_map_[p_map_idx].core_reg = reg_num;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700273}
274
buzbee091cc402014-03-31 10:14:40 -0700275/* Reserve a callee-save register. Return InvalidReg if none available */
buzbee2700f7e2014-03-07 09:46:20 -0800276RegStorage Mir2Lir::AllocPreservedCoreReg(int s_reg) {
277 RegStorage res;
buzbee091cc402014-03-31 10:14:40 -0700278 GrowableArray<RegisterInfo*>::Iterator it(&reg_pool_->core_regs_);
279 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
280 if (!info->IsTemp() && !info->InUse()) {
281 res = info->GetReg();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700282 RecordCorePromotion(res, s_reg);
283 break;
284 }
285 }
286 return res;
287}
288
buzbee091cc402014-03-31 10:14:40 -0700289void Mir2Lir::RecordSinglePromotion(RegStorage reg, int s_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700290 int p_map_idx = SRegToPMap(s_reg);
291 int v_reg = mir_graph_->SRegToVReg(s_reg);
buzbee091cc402014-03-31 10:14:40 -0700292 GetRegInfo(reg)->MarkInUse();
293 MarkPreservedSingle(v_reg, reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700294 promotion_map_[p_map_idx].fp_location = kLocPhysReg;
buzbee091cc402014-03-31 10:14:40 -0700295 promotion_map_[p_map_idx].FpReg = reg.GetReg();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700296}
297
buzbee091cc402014-03-31 10:14:40 -0700298// Reserve a callee-save sp single register.
buzbee2700f7e2014-03-07 09:46:20 -0800299RegStorage Mir2Lir::AllocPreservedSingle(int s_reg) {
300 RegStorage res;
buzbee091cc402014-03-31 10:14:40 -0700301 GrowableArray<RegisterInfo*>::Iterator it(&reg_pool_->sp_regs_);
302 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
303 if (!info->IsTemp() && !info->InUse()) {
304 res = info->GetReg();
305 RecordSinglePromotion(res, s_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700306 break;
307 }
308 }
309 return res;
310}
311
buzbee091cc402014-03-31 10:14:40 -0700312void Mir2Lir::RecordDoublePromotion(RegStorage reg, int s_reg) {
313 int p_map_idx = SRegToPMap(s_reg);
314 int v_reg = mir_graph_->SRegToVReg(s_reg);
315 GetRegInfo(reg)->MarkInUse();
316 MarkPreservedDouble(v_reg, reg);
317 promotion_map_[p_map_idx].fp_location = kLocPhysReg;
318 promotion_map_[p_map_idx].FpReg = reg.GetReg();
319}
320
321// Reserve a callee-save dp solo register.
buzbee2700f7e2014-03-07 09:46:20 -0800322RegStorage Mir2Lir::AllocPreservedDouble(int s_reg) {
323 RegStorage res;
buzbee091cc402014-03-31 10:14:40 -0700324 GrowableArray<RegisterInfo*>::Iterator it(&reg_pool_->dp_regs_);
325 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
326 if (!info->IsTemp() && !info->InUse()) {
327 res = info->GetReg();
328 RecordDoublePromotion(res, s_reg);
329 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700330 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700331 }
332 return res;
333}
334
buzbee091cc402014-03-31 10:14:40 -0700335
336RegStorage Mir2Lir::AllocTempBody(GrowableArray<RegisterInfo*> &regs, int* next_temp, bool required) {
337 int num_regs = regs.Size();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700338 int next = *next_temp;
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700339 for (int i = 0; i< num_regs; i++) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700340 if (next >= num_regs)
341 next = 0;
buzbee091cc402014-03-31 10:14:40 -0700342 RegisterInfo* info = regs.Get(next);
buzbee30adc732014-05-09 15:10:18 -0700343 // Try to allocate a register that doesn't hold a live value.
buzbee082833c2014-05-17 23:16:26 -0700344 if (info->IsTemp() && !info->InUse() && info->IsDead()) {
buzbee091cc402014-03-31 10:14:40 -0700345 Clobber(info->GetReg());
346 info->MarkInUse();
buzbee30adc732014-05-09 15:10:18 -0700347 /*
348 * NOTE: "wideness" is an attribute of how the container is used, not its physical size.
349 * The caller will set wideness as appropriate.
350 */
buzbee091cc402014-03-31 10:14:40 -0700351 info->SetIsWide(false);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700352 *next_temp = next + 1;
buzbee091cc402014-03-31 10:14:40 -0700353 return info->GetReg();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700354 }
355 next++;
356 }
357 next = *next_temp;
buzbee30adc732014-05-09 15:10:18 -0700358 // No free non-live regs. Anything we can kill?
Brian Carlstrom38f85e42013-07-18 14:45:22 -0700359 for (int i = 0; i< num_regs; i++) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700360 if (next >= num_regs)
361 next = 0;
buzbee091cc402014-03-31 10:14:40 -0700362 RegisterInfo* info = regs.Get(next);
363 if (info->IsTemp() && !info->InUse()) {
buzbee30adc732014-05-09 15:10:18 -0700364 // Got one. Kill it.
365 ClobberSReg(info->SReg());
buzbee091cc402014-03-31 10:14:40 -0700366 Clobber(info->GetReg());
367 info->MarkInUse();
buzbee082833c2014-05-17 23:16:26 -0700368 if (info->IsWide()) {
369 RegisterInfo* partner = GetRegInfo(info->Partner());
370 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum());
371 DCHECK(partner->IsWide());
372 info->SetIsWide(false);
373 partner->SetIsWide(false);
374 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700375 *next_temp = next + 1;
buzbee091cc402014-03-31 10:14:40 -0700376 return info->GetReg();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700377 }
378 next++;
379 }
380 if (required) {
381 CodegenDump();
buzbee091cc402014-03-31 10:14:40 -0700382 DumpRegPools();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700383 LOG(FATAL) << "No free temp registers";
384 }
buzbee2700f7e2014-03-07 09:46:20 -0800385 return RegStorage::InvalidReg(); // No register available
Brian Carlstrom7940e442013-07-12 13:46:57 -0700386}
387
Brian Carlstrom7940e442013-07-12 13:46:57 -0700388/* Return a temp if one is available, -1 otherwise */
buzbee2700f7e2014-03-07 09:46:20 -0800389RegStorage Mir2Lir::AllocFreeTemp() {
buzbee091cc402014-03-31 10:14:40 -0700390 return AllocTempBody(reg_pool_->core_regs_, &reg_pool_->next_core_reg_, false);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700391}
392
buzbee2700f7e2014-03-07 09:46:20 -0800393RegStorage Mir2Lir::AllocTemp() {
buzbee091cc402014-03-31 10:14:40 -0700394 return AllocTempBody(reg_pool_->core_regs_, &reg_pool_->next_core_reg_, true);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700395}
396
buzbeeb01bf152014-05-13 15:59:07 -0700397RegStorage Mir2Lir::AllocTempWide() {
398 RegStorage res;
399 if (reg_pool_->core64_regs_.Size() != 0) {
400 res = AllocTempBody(reg_pool_->core64_regs_, &reg_pool_->next_core64_reg_, true);
401 } else {
402 RegStorage low_reg = AllocTemp();
403 RegStorage high_reg = AllocTemp();
404 res = RegStorage::MakeRegPair(low_reg, high_reg);
405 }
406 return res;
407}
408
Matteo Franchin0955f7e2014-05-23 17:32:52 +0100409RegStorage Mir2Lir::AllocTempWord() {
buzbeed9f4c522014-05-29 16:03:42 -0700410 // FIXME: temporary workaround. For bring-up purposes, x86_64 needs the ability
411 // to allocate wide values as a pair of core registers. However, we can't hold
412 // a reference in a register pair. This workaround will be removed when the
413 // reference handling code is reworked, or x86_64 backend starts using wide core
414 // registers - whichever happens first.
415 if (cu_->instruction_set == kX86_64) {
416 return AllocTemp();
417 } else {
418 return (Is64BitInstructionSet(cu_->instruction_set)) ? AllocTempWide() : AllocTemp();
419 }
Matteo Franchin0955f7e2014-05-23 17:32:52 +0100420}
421
buzbee091cc402014-03-31 10:14:40 -0700422RegStorage Mir2Lir::AllocTempSingle() {
423 RegStorage res = AllocTempBody(reg_pool_->sp_regs_, &reg_pool_->next_sp_reg_, true);
424 DCHECK(res.IsSingle()) << "Reg: 0x" << std::hex << res.GetRawBits();
425 return res;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700426}
427
buzbee091cc402014-03-31 10:14:40 -0700428RegStorage Mir2Lir::AllocTempDouble() {
429 RegStorage res = AllocTempBody(reg_pool_->dp_regs_, &reg_pool_->next_dp_reg_, true);
430 DCHECK(res.IsDouble()) << "Reg: 0x" << std::hex << res.GetRawBits();
431 return res;
432}
433
buzbeeb01bf152014-05-13 15:59:07 -0700434RegStorage Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) {
435 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
436 return AllocTempDouble();
437 }
438 return AllocTempWide();
439}
440
441RegStorage Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) {
442 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) {
443 return AllocTempSingle();
444 }
445 return AllocTemp();
446}
447
buzbee091cc402014-03-31 10:14:40 -0700448RegStorage Mir2Lir::FindLiveReg(GrowableArray<RegisterInfo*> &regs, int s_reg) {
449 RegStorage res;
450 GrowableArray<RegisterInfo*>::Iterator it(&regs);
451 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
452 if ((info->SReg() == s_reg) && info->IsLive()) {
453 res = info->GetReg();
454 break;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700455 }
456 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700457 return res;
458}
459
buzbee091cc402014-03-31 10:14:40 -0700460RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) {
461 RegStorage reg;
462 // TODO: might be worth a sanity check here to verify at most 1 live reg per s_reg.
463 if ((reg_class == kAnyReg) || (reg_class == kFPReg)) {
464 reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700465 }
buzbee091cc402014-03-31 10:14:40 -0700466 if (!reg.Valid() && (reg_class != kFPReg)) {
Serban Constantinescued65c5e2014-05-22 15:10:18 +0100467 if (Is64BitInstructionSet(cu_->instruction_set)) {
468 reg = FindLiveReg(wide ? reg_pool_->core64_regs_ : reg_pool_->core_regs_, s_reg);
469 } else {
470 reg = FindLiveReg(reg_pool_->core_regs_, s_reg);
471 }
buzbee091cc402014-03-31 10:14:40 -0700472 }
473 if (reg.Valid()) {
buzbee30adc732014-05-09 15:10:18 -0700474 if (wide && !reg.IsFloat() && !Is64BitInstructionSet(cu_->instruction_set)) {
475 // Only allow reg pairs for core regs on 32-bit targets.
buzbee091cc402014-03-31 10:14:40 -0700476 RegStorage high_reg = FindLiveReg(reg_pool_->core_regs_, s_reg + 1);
477 if (high_reg.Valid()) {
buzbee091cc402014-03-31 10:14:40 -0700478 reg = RegStorage::MakeRegPair(reg, high_reg);
479 MarkWide(reg);
480 } else {
buzbee30adc732014-05-09 15:10:18 -0700481 // Only half available.
buzbee091cc402014-03-31 10:14:40 -0700482 reg = RegStorage::InvalidReg();
483 }
484 }
buzbee30adc732014-05-09 15:10:18 -0700485 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) {
486 // Width mismatch - don't try to reuse.
487 reg = RegStorage::InvalidReg();
488 }
489 }
490 if (reg.Valid()) {
491 if (reg.IsPair()) {
492 RegisterInfo* info_low = GetRegInfo(reg.GetLow());
493 RegisterInfo* info_high = GetRegInfo(reg.GetHigh());
494 if (info_low->IsTemp()) {
495 info_low->MarkInUse();
496 }
497 if (info_high->IsTemp()) {
498 info_high->MarkInUse();
499 }
500 } else {
buzbee091cc402014-03-31 10:14:40 -0700501 RegisterInfo* info = GetRegInfo(reg);
502 if (info->IsTemp()) {
503 info->MarkInUse();
504 }
505 }
buzbee30adc732014-05-09 15:10:18 -0700506 } else {
507 // Either not found, or something didn't match up. Clobber to prevent any stale instances.
508 ClobberSReg(s_reg);
509 if (wide) {
510 ClobberSReg(s_reg + 1);
buzbee091cc402014-03-31 10:14:40 -0700511 }
512 }
513 return reg;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700514}
515
buzbee2700f7e2014-03-07 09:46:20 -0800516void Mir2Lir::FreeTemp(RegStorage reg) {
517 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700518 FreeTemp(reg.GetLow());
519 FreeTemp(reg.GetHigh());
buzbee2700f7e2014-03-07 09:46:20 -0800520 } else {
buzbee091cc402014-03-31 10:14:40 -0700521 RegisterInfo* p = GetRegInfo(reg);
522 if (p->IsTemp()) {
523 p->MarkFree();
524 p->SetIsWide(false);
525 p->SetPartner(reg);
526 }
buzbee2700f7e2014-03-07 09:46:20 -0800527 }
528}
529
buzbee082833c2014-05-17 23:16:26 -0700530void Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) {
531 DCHECK(rl_keep.wide);
532 DCHECK(rl_free.wide);
533 int free_low = rl_free.reg.GetLowReg();
534 int free_high = rl_free.reg.GetHighReg();
535 int keep_low = rl_keep.reg.GetLowReg();
536 int keep_high = rl_keep.reg.GetHighReg();
537 if ((free_low != keep_low) && (free_low != keep_high) &&
538 (free_high != keep_low) && (free_high != keep_high)) {
539 // No overlap, free both
540 FreeTemp(rl_free.reg);
541 }
542}
543
buzbee262b2992014-03-27 11:22:43 -0700544bool Mir2Lir::IsLive(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700545 bool res;
buzbee2700f7e2014-03-07 09:46:20 -0800546 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700547 RegisterInfo* p_lo = GetRegInfo(reg.GetLow());
548 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh());
buzbee30adc732014-05-09 15:10:18 -0700549 DCHECK_EQ(p_lo->IsLive(), p_hi->IsLive());
buzbee091cc402014-03-31 10:14:40 -0700550 res = p_lo->IsLive() || p_hi->IsLive();
buzbee2700f7e2014-03-07 09:46:20 -0800551 } else {
buzbee091cc402014-03-31 10:14:40 -0700552 RegisterInfo* p = GetRegInfo(reg);
553 res = p->IsLive();
buzbee2700f7e2014-03-07 09:46:20 -0800554 }
buzbee091cc402014-03-31 10:14:40 -0700555 return res;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700556}
557
buzbee262b2992014-03-27 11:22:43 -0700558bool Mir2Lir::IsTemp(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700559 bool res;
buzbee2700f7e2014-03-07 09:46:20 -0800560 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700561 RegisterInfo* p_lo = GetRegInfo(reg.GetLow());
562 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh());
563 res = p_lo->IsTemp() || p_hi->IsTemp();
buzbee2700f7e2014-03-07 09:46:20 -0800564 } else {
buzbee091cc402014-03-31 10:14:40 -0700565 RegisterInfo* p = GetRegInfo(reg);
566 res = p->IsTemp();
buzbee2700f7e2014-03-07 09:46:20 -0800567 }
buzbee091cc402014-03-31 10:14:40 -0700568 return res;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700569}
570
buzbee262b2992014-03-27 11:22:43 -0700571bool Mir2Lir::IsPromoted(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700572 bool res;
buzbee2700f7e2014-03-07 09:46:20 -0800573 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700574 RegisterInfo* p_lo = GetRegInfo(reg.GetLow());
575 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh());
576 res = !p_lo->IsTemp() || !p_hi->IsTemp();
buzbee2700f7e2014-03-07 09:46:20 -0800577 } else {
buzbee091cc402014-03-31 10:14:40 -0700578 RegisterInfo* p = GetRegInfo(reg);
579 res = !p->IsTemp();
buzbee2700f7e2014-03-07 09:46:20 -0800580 }
buzbee091cc402014-03-31 10:14:40 -0700581 return res;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700582}
583
buzbee2700f7e2014-03-07 09:46:20 -0800584bool Mir2Lir::IsDirty(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700585 bool res;
buzbee2700f7e2014-03-07 09:46:20 -0800586 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700587 RegisterInfo* p_lo = GetRegInfo(reg.GetLow());
588 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh());
589 res = p_lo->IsDirty() || p_hi->IsDirty();
buzbee2700f7e2014-03-07 09:46:20 -0800590 } else {
buzbee091cc402014-03-31 10:14:40 -0700591 RegisterInfo* p = GetRegInfo(reg);
592 res = p->IsDirty();
buzbee2700f7e2014-03-07 09:46:20 -0800593 }
buzbee091cc402014-03-31 10:14:40 -0700594 return res;
buzbee2700f7e2014-03-07 09:46:20 -0800595}
596
Brian Carlstrom7940e442013-07-12 13:46:57 -0700597/*
598 * Similar to AllocTemp(), but forces the allocation of a specific
599 * register. No check is made to see if the register was previously
600 * allocated. Use with caution.
601 */
buzbee2700f7e2014-03-07 09:46:20 -0800602void Mir2Lir::LockTemp(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700603 DCHECK(IsTemp(reg));
604 if (reg.IsPair()) {
605 RegisterInfo* p_lo = GetRegInfo(reg.GetLow());
606 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh());
607 p_lo->MarkInUse();
buzbee30adc732014-05-09 15:10:18 -0700608 p_lo->MarkDead();
buzbee091cc402014-03-31 10:14:40 -0700609 p_hi->MarkInUse();
buzbee30adc732014-05-09 15:10:18 -0700610 p_hi->MarkDead();
buzbee091cc402014-03-31 10:14:40 -0700611 } else {
612 RegisterInfo* p = GetRegInfo(reg);
613 p->MarkInUse();
buzbee30adc732014-05-09 15:10:18 -0700614 p->MarkDead();
buzbee091cc402014-03-31 10:14:40 -0700615 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700616}
617
buzbee2700f7e2014-03-07 09:46:20 -0800618void Mir2Lir::ResetDef(RegStorage reg) {
buzbee091cc402014-03-31 10:14:40 -0700619 if (reg.IsPair()) {
620 GetRegInfo(reg.GetLow())->ResetDefBody();
621 GetRegInfo(reg.GetHigh())->ResetDefBody();
622 } else {
623 GetRegInfo(reg)->ResetDefBody();
624 }
buzbee2700f7e2014-03-07 09:46:20 -0800625}
626
buzbee091cc402014-03-31 10:14:40 -0700627void Mir2Lir::NullifyRange(RegStorage reg, int s_reg) {
628 RegisterInfo* info = nullptr;
629 RegStorage rs = reg.IsPair() ? reg.GetLow() : reg;
630 if (IsTemp(rs)) {
631 info = GetRegInfo(reg);
632 }
633 if ((info != nullptr) && (info->DefStart() != nullptr) && (info->DefEnd() != nullptr)) {
634 DCHECK_EQ(info->SReg(), s_reg); // Make sure we're on the same page.
635 for (LIR* p = info->DefStart();; p = p->next) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700636 NopLIR(p);
buzbee091cc402014-03-31 10:14:40 -0700637 if (p == info->DefEnd()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700638 break;
buzbee091cc402014-03-31 10:14:40 -0700639 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700640 }
641 }
642}
643
644/*
645 * Mark the beginning and end LIR of a def sequence. Note that
646 * on entry start points to the LIR prior to the beginning of the
647 * sequence.
648 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700649void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700650 DCHECK(!rl.wide);
651 DCHECK(start && start->next);
652 DCHECK(finish);
buzbee091cc402014-03-31 10:14:40 -0700653 RegisterInfo* p = GetRegInfo(rl.reg);
654 p->SetDefStart(start->next);
655 p->SetDefEnd(finish);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700656}
657
658/*
659 * Mark the beginning and end LIR of a def sequence. Note that
660 * on entry start points to the LIR prior to the beginning of the
661 * sequence.
662 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700663void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700664 DCHECK(rl.wide);
665 DCHECK(start && start->next);
666 DCHECK(finish);
buzbee091cc402014-03-31 10:14:40 -0700667 RegisterInfo* p;
668 if (rl.reg.IsPair()) {
669 p = GetRegInfo(rl.reg.GetLow());
670 ResetDef(rl.reg.GetHigh()); // Only track low of pair
671 } else {
672 p = GetRegInfo(rl.reg);
673 }
674 p->SetDefStart(start->next);
675 p->SetDefEnd(finish);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700676}
677
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700678RegLocation Mir2Lir::WideToNarrow(RegLocation rl) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700679 DCHECK(rl.wide);
680 if (rl.location == kLocPhysReg) {
buzbee091cc402014-03-31 10:14:40 -0700681 if (rl.reg.IsPair()) {
682 RegisterInfo* info_lo = GetRegInfo(rl.reg.GetLow());
683 RegisterInfo* info_hi = GetRegInfo(rl.reg.GetHigh());
684 if (info_lo->IsTemp()) {
685 info_lo->SetIsWide(false);
686 info_lo->ResetDefBody();
687 }
688 if (info_hi->IsTemp()) {
689 info_hi->SetIsWide(false);
690 info_hi->ResetDefBody();
691 }
692 rl.reg = rl.reg.GetLow();
buzbee30adc732014-05-09 15:10:18 -0700693 } else {
694 /*
695 * TODO: If not a pair, we can't just drop the high register. On some targets, we may be
696 * able to re-cast the 64-bit register as 32 bits, so it might be worthwhile to revisit
697 * this code. Will probably want to make this a virtual function.
698 */
699 // Can't narrow 64-bit register. Clobber.
700 if (GetRegInfo(rl.reg)->IsTemp()) {
701 Clobber(rl.reg);
702 FreeTemp(rl.reg);
703 }
704 rl.location = kLocDalvikFrame;
Brian Carlstrom7940e442013-07-12 13:46:57 -0700705 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700706 }
707 rl.wide = false;
708 return rl;
709}
710
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700711void Mir2Lir::ResetDefLoc(RegLocation rl) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700712 DCHECK(!rl.wide);
buzbee091cc402014-03-31 10:14:40 -0700713 if (IsTemp(rl.reg) && !(cu_->disable_opt & (1 << kSuppressLoads))) {
714 NullifyRange(rl.reg, rl.s_reg_low);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700715 }
buzbee091cc402014-03-31 10:14:40 -0700716 ResetDef(rl.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700717}
718
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700719void Mir2Lir::ResetDefLocWide(RegLocation rl) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700720 DCHECK(rl.wide);
buzbee091cc402014-03-31 10:14:40 -0700721 // If pair, only track low reg of pair.
722 RegStorage rs = rl.reg.IsPair() ? rl.reg.GetLow() : rl.reg;
723 if (IsTemp(rs) && !(cu_->disable_opt & (1 << kSuppressLoads))) {
724 NullifyRange(rs, rl.s_reg_low);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700725 }
buzbee091cc402014-03-31 10:14:40 -0700726 ResetDef(rs);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700727}
728
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700729void Mir2Lir::ResetDefTracking() {
buzbee091cc402014-03-31 10:14:40 -0700730 GrowableArray<RegisterInfo*>::Iterator core_it(&reg_pool_->core_regs_);
731 for (RegisterInfo* info = core_it.Next(); info != nullptr; info = core_it.Next()) {
732 info->ResetDefBody();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700733 }
buzbee091cc402014-03-31 10:14:40 -0700734 GrowableArray<RegisterInfo*>::Iterator sp_it(&reg_pool_->core_regs_);
735 for (RegisterInfo* info = sp_it.Next(); info != nullptr; info = sp_it.Next()) {
736 info->ResetDefBody();
737 }
738 GrowableArray<RegisterInfo*>::Iterator dp_it(&reg_pool_->core_regs_);
739 for (RegisterInfo* info = dp_it.Next(); info != nullptr; info = dp_it.Next()) {
740 info->ResetDefBody();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700741 }
742}
743
buzbeeba574512014-05-12 15:13:16 -0700744void Mir2Lir::ClobberAllTemps() {
buzbeebd663de2013-09-10 15:41:31 -0700745 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_);
746 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) {
buzbee30adc732014-05-09 15:10:18 -0700747 ClobberBody(info);
buzbee091cc402014-03-31 10:14:40 -0700748 }
749}
750
751void Mir2Lir::FlushRegWide(RegStorage reg) {
752 if (reg.IsPair()) {
753 RegisterInfo* info1 = GetRegInfo(reg.GetLow());
754 RegisterInfo* info2 = GetRegInfo(reg.GetHigh());
755 DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() &&
756 (info1->Partner() == info2->GetReg()) && (info2->Partner() == info1->GetReg()));
757 if ((info1->IsLive() && info1->IsDirty()) || (info2->IsLive() && info2->IsDirty())) {
758 if (!(info1->IsTemp() && info2->IsTemp())) {
759 /* Should not happen. If it does, there's a problem in eval_loc */
760 LOG(FATAL) << "Long half-temp, half-promoted";
761 }
762
763 info1->SetIsDirty(false);
764 info2->SetIsDirty(false);
765 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) {
766 info1 = info2;
767 }
768 int v_reg = mir_graph_->SRegToVReg(info1->SReg());
Vladimir Marko455759b2014-05-06 20:49:36 +0100769 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64);
buzbee091cc402014-03-31 10:14:40 -0700770 }
771 } else {
772 RegisterInfo* info = GetRegInfo(reg);
773 if (info->IsLive() && info->IsDirty()) {
774 info->SetIsDirty(false);
775 int v_reg = mir_graph_->SRegToVReg(info->SReg());
Vladimir Marko455759b2014-05-06 20:49:36 +0100776 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64);
buzbee091cc402014-03-31 10:14:40 -0700777 }
778 }
779}
780
781void Mir2Lir::FlushReg(RegStorage reg) {
782 DCHECK(!reg.IsPair());
783 RegisterInfo* info = GetRegInfo(reg);
784 if (info->IsLive() && info->IsDirty()) {
785 info->SetIsDirty(false);
786 int v_reg = mir_graph_->SRegToVReg(info->SReg());
787 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, kWord);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700788 }
789}
790
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800791void Mir2Lir::FlushSpecificReg(RegisterInfo* info) {
buzbee091cc402014-03-31 10:14:40 -0700792 if (info->IsWide()) {
793 FlushRegWide(info->GetReg());
Razvan A Lupusoru614c2b42014-01-28 17:05:21 -0800794 } else {
buzbee091cc402014-03-31 10:14:40 -0700795 FlushReg(info->GetReg());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700796 }
797}
798
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700799void Mir2Lir::FlushAllRegs() {
buzbee091cc402014-03-31 10:14:40 -0700800 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_);
801 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
buzbeeba574512014-05-12 15:13:16 -0700802 if (info->IsDirty() && info->IsLive()) {
buzbee091cc402014-03-31 10:14:40 -0700803 FlushSpecificReg(info);
804 }
buzbee30adc732014-05-09 15:10:18 -0700805 info->MarkDead();
buzbee091cc402014-03-31 10:14:40 -0700806 info->SetIsWide(false);
807 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700808}
809
810
buzbee2700f7e2014-03-07 09:46:20 -0800811bool Mir2Lir::RegClassMatches(int reg_class, RegStorage reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700812 if (reg_class == kAnyReg) {
813 return true;
814 } else if (reg_class == kCoreReg) {
buzbee091cc402014-03-31 10:14:40 -0700815 return !reg.IsFloat();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700816 } else {
buzbee091cc402014-03-31 10:14:40 -0700817 return reg.IsFloat();
Brian Carlstrom7940e442013-07-12 13:46:57 -0700818 }
819}
820
buzbee091cc402014-03-31 10:14:40 -0700821void Mir2Lir::MarkLive(RegLocation loc) {
822 RegStorage reg = loc.reg;
buzbee082833c2014-05-17 23:16:26 -0700823 if (!IsTemp(reg)) {
824 return;
825 }
buzbee091cc402014-03-31 10:14:40 -0700826 int s_reg = loc.s_reg_low;
buzbee082833c2014-05-17 23:16:26 -0700827 if (s_reg == INVALID_SREG) {
828 // Can't be live if no associated sreg.
829 if (reg.IsPair()) {
830 GetRegInfo(reg.GetLow())->MarkDead();
831 GetRegInfo(reg.GetHigh())->MarkDead();
832 } else {
833 GetRegInfo(reg)->MarkDead();
buzbee091cc402014-03-31 10:14:40 -0700834 }
buzbee082833c2014-05-17 23:16:26 -0700835 } else {
836 if (reg.IsPair()) {
837 RegisterInfo* info_lo = GetRegInfo(reg.GetLow());
838 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh());
839 if (info_lo->IsLive() && (info_lo->SReg() == s_reg) && info_hi->IsLive() &&
840 (info_hi->SReg() == s_reg)) {
841 return; // Already live.
842 }
843 ClobberSReg(s_reg);
844 ClobberSReg(s_reg + 1);
845 info_lo->MarkLive(s_reg);
846 info_hi->MarkLive(s_reg + 1);
847 } else {
848 RegisterInfo* info = GetRegInfo(reg);
849 if (info->IsLive() && (info->SReg() == s_reg)) {
850 return; // Already live.
851 }
852 ClobberSReg(s_reg);
853 if (loc.wide) {
854 ClobberSReg(s_reg + 1);
855 }
856 info->MarkLive(s_reg);
857 }
858 if (loc.wide) {
859 MarkWide(reg);
860 } else {
861 MarkNarrow(reg);
862 }
buzbee091cc402014-03-31 10:14:40 -0700863 }
Brian Carlstrom7940e442013-07-12 13:46:57 -0700864}
865
buzbee2700f7e2014-03-07 09:46:20 -0800866void Mir2Lir::MarkTemp(RegStorage reg) {
867 DCHECK(!reg.IsPair());
Brian Carlstrom7940e442013-07-12 13:46:57 -0700868 RegisterInfo* info = GetRegInfo(reg);
buzbee091cc402014-03-31 10:14:40 -0700869 tempreg_info_.Insert(info);
870 info->SetIsTemp(true);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700871}
872
buzbee2700f7e2014-03-07 09:46:20 -0800873void Mir2Lir::UnmarkTemp(RegStorage reg) {
874 DCHECK(!reg.IsPair());
buzbee091cc402014-03-31 10:14:40 -0700875 RegisterInfo* info = GetRegInfo(reg);
876 tempreg_info_.Delete(info);
877 info->SetIsTemp(false);
buzbee2700f7e2014-03-07 09:46:20 -0800878}
879
buzbee091cc402014-03-31 10:14:40 -0700880void Mir2Lir::MarkWide(RegStorage reg) {
881 if (reg.IsPair()) {
882 RegisterInfo* info_lo = GetRegInfo(reg.GetLow());
883 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh());
buzbee082833c2014-05-17 23:16:26 -0700884 // Unpair any old partners.
885 if (info_lo->IsWide() && info_lo->Partner() != info_hi->GetReg()) {
886 GetRegInfo(info_lo->Partner())->SetIsWide(false);
887 }
888 if (info_hi->IsWide() && info_hi->Partner() != info_lo->GetReg()) {
889 GetRegInfo(info_hi->Partner())->SetIsWide(false);
890 }
buzbee091cc402014-03-31 10:14:40 -0700891 info_lo->SetIsWide(true);
892 info_hi->SetIsWide(true);
893 info_lo->SetPartner(reg.GetHigh());
894 info_hi->SetPartner(reg.GetLow());
buzbee2700f7e2014-03-07 09:46:20 -0800895 } else {
buzbee091cc402014-03-31 10:14:40 -0700896 RegisterInfo* info = GetRegInfo(reg);
897 info->SetIsWide(true);
898 info->SetPartner(reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700899 }
900}
901
buzbee082833c2014-05-17 23:16:26 -0700902void Mir2Lir::MarkNarrow(RegStorage reg) {
903 DCHECK(!reg.IsPair());
904 RegisterInfo* info = GetRegInfo(reg);
905 info->SetIsWide(false);
906 info->SetPartner(reg);
907}
908
buzbee091cc402014-03-31 10:14:40 -0700909void Mir2Lir::MarkClean(RegLocation loc) {
910 if (loc.reg.IsPair()) {
911 RegisterInfo* info = GetRegInfo(loc.reg.GetLow());
912 info->SetIsDirty(false);
913 info = GetRegInfo(loc.reg.GetHigh());
914 info->SetIsDirty(false);
915 } else {
916 RegisterInfo* info = GetRegInfo(loc.reg);
917 info->SetIsDirty(false);
918 }
919}
920
921// FIXME: need to verify rules/assumptions about how wide values are treated in 64BitSolos.
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700922void Mir2Lir::MarkDirty(RegLocation loc) {
Brian Carlstrom7940e442013-07-12 13:46:57 -0700923 if (loc.home) {
924 // If already home, can't be dirty
925 return;
926 }
buzbee091cc402014-03-31 10:14:40 -0700927 if (loc.reg.IsPair()) {
928 RegisterInfo* info = GetRegInfo(loc.reg.GetLow());
929 info->SetIsDirty(true);
930 info = GetRegInfo(loc.reg.GetHigh());
931 info->SetIsDirty(true);
buzbee2700f7e2014-03-07 09:46:20 -0800932 } else {
buzbee091cc402014-03-31 10:14:40 -0700933 RegisterInfo* info = GetRegInfo(loc.reg);
934 info->SetIsDirty(true);
Brian Carlstrom7940e442013-07-12 13:46:57 -0700935 }
936}
937
buzbee2700f7e2014-03-07 09:46:20 -0800938void Mir2Lir::MarkInUse(RegStorage reg) {
939 if (reg.IsPair()) {
buzbee091cc402014-03-31 10:14:40 -0700940 GetRegInfo(reg.GetLow())->MarkInUse();
941 GetRegInfo(reg.GetHigh())->MarkInUse();
buzbee2700f7e2014-03-07 09:46:20 -0800942 } else {
buzbee091cc402014-03-31 10:14:40 -0700943 GetRegInfo(reg)->MarkInUse();
buzbee2700f7e2014-03-07 09:46:20 -0800944 }
945}
946
Brian Carlstrom2ce745c2013-07-17 17:44:30 -0700947bool Mir2Lir::CheckCorePoolSanity() {
buzbee082833c2014-05-17 23:16:26 -0700948 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_);
buzbee091cc402014-03-31 10:14:40 -0700949 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) {
buzbee082833c2014-05-17 23:16:26 -0700950 if (info->IsTemp() && info->IsLive() && info->IsWide()) {
951 RegStorage my_reg = info->GetReg();
buzbee091cc402014-03-31 10:14:40 -0700952 int my_sreg = info->SReg();
953 RegStorage partner_reg = info->Partner();
954 RegisterInfo* partner = GetRegInfo(partner_reg);
Brian Carlstrom6f485c62013-07-18 15:35:35 -0700955 DCHECK(partner != NULL);
buzbee091cc402014-03-31 10:14:40 -0700956 DCHECK(partner->IsWide());
957 DCHECK_EQ(my_reg.GetReg(), partner->Partner().GetReg());
buzbee082833c2014-05-17 23:16:26 -0700958 DCHECK(partner->IsLive());
buzbee091cc402014-03-31 10:14:40 -0700959 int partner_sreg = partner->SReg();
Brian Carlstrom6f485c62013-07-18 15:35:35 -0700960 if (my_sreg == INVALID_SREG) {
961 DCHECK_EQ(partner_sreg, INVALID_SREG);
962 } else {
963 int diff = my_sreg - partner_sreg;
buzbee091cc402014-03-31 10:14:40 -0700964 DCHECK((diff == 0) || (diff == -1) || (diff == 1));
Brian Carlstrom6f485c62013-07-18 15:35:35 -0700965 }
966 }
buzbee082833c2014-05-17 23:16:26 -0700967 if (info->Master() != info) {
968 // Aliased.
969 if (info->IsLive() && (info->SReg() != INVALID_SREG)) {
970 // If I'm live, master should not be live, but should show liveness in alias set.
971 DCHECK_EQ(info->Master()->SReg(), INVALID_SREG);
972 DCHECK(!info->Master()->IsDead());
buzbee082833c2014-05-17 23:16:26 -0700973 }
buzbee642fe342014-05-23 16:04:08 -0700974// TODO: Add checks in !info->IsDead() case to ensure every live bit is owned by exactly 1 reg.
buzbee082833c2014-05-17 23:16:26 -0700975 }
976 if (info->IsAliased()) {
977 // Has child aliases.
978 DCHECK_EQ(info->Master(), info);
979 if (info->IsLive() && (info->SReg() != INVALID_SREG)) {
980 // Master live, no child should be dead - all should show liveness in set.
981 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) {
982 DCHECK(!p->IsDead());
983 DCHECK_EQ(p->SReg(), INVALID_SREG);
984 }
985 } else if (!info->IsDead()) {
986 // Master not live, one or more aliases must be.
987 bool live_alias = false;
988 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) {
989 live_alias |= p->IsLive();
990 }
991 DCHECK(live_alias);
992 }
993 }
994 if (info->IsLive() && (info->SReg() == INVALID_SREG)) {
995 // If not fully live, should have INVALID_SREG and def's should be null.
996 DCHECK(info->DefStart() == nullptr);
997 DCHECK(info->DefEnd() == nullptr);
Brian Carlstrom6f485c62013-07-18 15:35:35 -0700998 }
999 }
1000 return true;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001001}
1002
1003/*
1004 * Return an updated location record with current in-register status.
1005 * If the value lives in live temps, reflect that fact. No code
1006 * is generated. If the live value is part of an older pair,
1007 * clobber both low and high.
1008 * TUNING: clobbering both is a bit heavy-handed, but the alternative
1009 * is a bit complex when dealing with FP regs. Examine code to see
1010 * if it's worthwhile trying to be more clever here.
1011 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001012RegLocation Mir2Lir::UpdateLoc(RegLocation loc) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001013 DCHECK(!loc.wide);
1014 DCHECK(CheckCorePoolSanity());
1015 if (loc.location != kLocPhysReg) {
1016 DCHECK((loc.location == kLocDalvikFrame) ||
1017 (loc.location == kLocCompilerTemp));
buzbee091cc402014-03-31 10:14:40 -07001018 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, false);
1019 if (reg.Valid()) {
1020 bool match = true;
1021 RegisterInfo* info = GetRegInfo(reg);
1022 match &= !reg.IsPair();
1023 match &= !info->IsWide();
1024 if (match) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001025 loc.location = kLocPhysReg;
buzbee091cc402014-03-31 10:14:40 -07001026 loc.reg = reg;
1027 } else {
1028 Clobber(reg);
1029 FreeTemp(reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001030 }
1031 }
1032 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001033 return loc;
1034}
1035
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001036RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001037 DCHECK(loc.wide);
1038 DCHECK(CheckCorePoolSanity());
1039 if (loc.location != kLocPhysReg) {
1040 DCHECK((loc.location == kLocDalvikFrame) ||
1041 (loc.location == kLocCompilerTemp));
buzbee091cc402014-03-31 10:14:40 -07001042 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true);
1043 if (reg.Valid()) {
1044 bool match = true;
1045 if (reg.IsPair()) {
1046 // If we've got a register pair, make sure that it was last used as the same pair.
1047 RegisterInfo* info_lo = GetRegInfo(reg.GetLow());
1048 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh());
1049 match &= info_lo->IsWide();
1050 match &= info_hi->IsWide();
1051 match &= (info_lo->Partner() == info_hi->GetReg());
1052 match &= (info_hi->Partner() == info_lo->GetReg());
1053 } else {
1054 RegisterInfo* info = GetRegInfo(reg);
1055 match &= info->IsWide();
1056 match &= (info->GetReg() == info->Partner());
1057 }
1058 if (match) {
1059 loc.location = kLocPhysReg;
1060 loc.reg = reg;
1061 } else {
1062 Clobber(reg);
1063 FreeTemp(reg);
1064 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001065 }
1066 }
1067 return loc;
1068}
1069
Brian Carlstrom7940e442013-07-12 13:46:57 -07001070/* For use in cases we don't know (or care) width */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001071RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001072 if (loc.wide)
1073 return UpdateLocWide(loc);
1074 else
1075 return UpdateLoc(loc);
1076}
1077
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001078RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001079 DCHECK(loc.wide);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001080
1081 loc = UpdateLocWide(loc);
1082
1083 /* If already in registers, we can assume proper form. Right reg class? */
1084 if (loc.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -08001085 if (!RegClassMatches(reg_class, loc.reg)) {
Vladimir Marko0dc242d2014-05-12 16:22:14 +01001086 // Wrong register class. Reallocate and transfer ownership.
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001087 RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class);
buzbee082833c2014-05-17 23:16:26 -07001088 // Clobber the old regs.
buzbee2700f7e2014-03-07 09:46:20 -08001089 Clobber(loc.reg);
buzbee082833c2014-05-17 23:16:26 -07001090 // ...and mark the new ones live.
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001091 loc.reg = new_regs;
buzbee091cc402014-03-31 10:14:40 -07001092 MarkWide(loc.reg);
buzbee082833c2014-05-17 23:16:26 -07001093 MarkLive(loc);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001094 }
1095 return loc;
1096 }
1097
1098 DCHECK_NE(loc.s_reg_low, INVALID_SREG);
1099 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG);
1100
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001101 loc.reg = AllocTypedTempWide(loc.fp, reg_class);
buzbee091cc402014-03-31 10:14:40 -07001102 MarkWide(loc.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001103
Brian Carlstrom7940e442013-07-12 13:46:57 -07001104 if (update) {
1105 loc.location = kLocPhysReg;
buzbee091cc402014-03-31 10:14:40 -07001106 MarkLive(loc);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001107 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001108 return loc;
1109}
1110
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001111RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) {
buzbee091cc402014-03-31 10:14:40 -07001112 if (loc.wide) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001113 return EvalLocWide(loc, reg_class, update);
buzbee091cc402014-03-31 10:14:40 -07001114 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001115
1116 loc = UpdateLoc(loc);
1117
1118 if (loc.location == kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -08001119 if (!RegClassMatches(reg_class, loc.reg)) {
Vladimir Marko0dc242d2014-05-12 16:22:14 +01001120 // Wrong register class. Reallocate and transfer ownership.
buzbee2700f7e2014-03-07 09:46:20 -08001121 RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class);
buzbee082833c2014-05-17 23:16:26 -07001122 // Clobber the old reg.
buzbee2700f7e2014-03-07 09:46:20 -08001123 Clobber(loc.reg);
buzbee082833c2014-05-17 23:16:26 -07001124 // ...and mark the new one live.
buzbee2700f7e2014-03-07 09:46:20 -08001125 loc.reg = new_reg;
buzbee082833c2014-05-17 23:16:26 -07001126 MarkLive(loc);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001127 }
1128 return loc;
1129 }
1130
1131 DCHECK_NE(loc.s_reg_low, INVALID_SREG);
1132
buzbee2700f7e2014-03-07 09:46:20 -08001133 loc.reg = AllocTypedTemp(loc.fp, reg_class);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001134
1135 if (update) {
1136 loc.location = kLocPhysReg;
buzbee091cc402014-03-31 10:14:40 -07001137 MarkLive(loc);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001138 }
1139 return loc;
1140}
1141
1142/* USE SSA names to count references of base Dalvik v_regs. */
buzbeec729a6b2013-09-14 16:04:31 -07001143void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001144 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) {
1145 RegLocation loc = mir_graph_->reg_location_[i];
1146 RefCounts* counts = loc.fp ? fp_counts : core_counts;
1147 int p_map_idx = SRegToPMap(loc.s_reg_low);
buzbeec729a6b2013-09-14 16:04:31 -07001148 if (loc.fp) {
1149 if (loc.wide) {
1150 // Treat doubles as a unit, using upper half of fp_counts array.
1151 counts[p_map_idx + num_regs].count += mir_graph_->GetUseCount(i);
1152 i++;
1153 } else {
1154 counts[p_map_idx].count += mir_graph_->GetUseCount(i);
1155 }
1156 } else if (!IsInexpensiveConstant(loc)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001157 counts[p_map_idx].count += mir_graph_->GetUseCount(i);
1158 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001159 }
1160}
1161
1162/* qsort callback function, sort descending */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001163static int SortCounts(const void *val1, const void *val2) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001164 const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1);
1165 const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2);
Brian Carlstrom4b8c13e2013-08-23 18:10:32 -07001166 // Note that we fall back to sorting on reg so we get stable output
1167 // on differing qsort implementations (such as on host and target or
1168 // between local host and build servers).
1169 return (op1->count == op2->count)
1170 ? (op1->s_reg - op2->s_reg)
1171 : (op1->count < op2->count ? 1 : -1);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001172}
1173
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001174void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001175 LOG(INFO) << msg;
1176 for (int i = 0; i < size; i++) {
buzbeec729a6b2013-09-14 16:04:31 -07001177 if ((arr[i].s_reg & STARTING_DOUBLE_SREG) != 0) {
1178 LOG(INFO) << "s_reg[D" << (arr[i].s_reg & ~STARTING_DOUBLE_SREG) << "]: " << arr[i].count;
1179 } else {
1180 LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count;
1181 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001182 }
1183}
1184
1185/*
1186 * Note: some portions of this code required even if the kPromoteRegs
1187 * optimization is disabled.
1188 */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001189void Mir2Lir::DoPromotion() {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001190 int dalvik_regs = cu_->num_dalvik_registers;
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -08001191 int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps();
Brian Carlstrom7940e442013-07-12 13:46:57 -07001192 const int promotion_threshold = 1;
buzbeed69835d2014-02-03 14:40:27 -08001193 // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp
1194 promotion_map_ = static_cast<PromotionMap*>
Vladimir Marko83cc7ae2014-02-12 18:02:05 +00001195 (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001196
1197 // Allow target code to add any special registers
1198 AdjustSpillMask();
1199
1200 /*
1201 * Simple register promotion. Just do a static count of the uses
1202 * of Dalvik registers. Note that we examine the SSA names, but
1203 * count based on original Dalvik register name. Count refs
1204 * separately based on type in order to give allocation
1205 * preference to fp doubles - which must be allocated sequential
buzbeec729a6b2013-09-14 16:04:31 -07001206 * physical single fp registers starting with an even-numbered
Brian Carlstrom7940e442013-07-12 13:46:57 -07001207 * reg.
1208 * TUNING: replace with linear scan once we have the ability
1209 * to describe register live ranges for GC.
1210 */
1211 RefCounts *core_regs =
Mathieu Chartierf6c4b3b2013-08-24 16:11:37 -07001212 static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * num_regs,
Vladimir Marko83cc7ae2014-02-12 18:02:05 +00001213 kArenaAllocRegAlloc));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001214 RefCounts *FpRegs =
buzbeec729a6b2013-09-14 16:04:31 -07001215 static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * num_regs * 2,
Vladimir Marko83cc7ae2014-02-12 18:02:05 +00001216 kArenaAllocRegAlloc));
Brian Carlstrom7940e442013-07-12 13:46:57 -07001217 // Set ssa names for original Dalvik registers
1218 for (int i = 0; i < dalvik_regs; i++) {
1219 core_regs[i].s_reg = FpRegs[i].s_reg = i;
1220 }
Razvan A Lupusoruda7a69b2014-01-08 15:09:50 -08001221
1222 // Set ssa names for compiler temporaries
1223 for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) {
1224 CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx);
1225 core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low;
1226 FpRegs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low;
1227 FpRegs[num_regs + dalvik_regs + ct_idx].s_reg = ct->s_reg_low;
buzbeec729a6b2013-09-14 16:04:31 -07001228 }
1229
1230 // Duplicate in upper half to represent possible fp double starting sregs.
1231 for (int i = 0; i < num_regs; i++) {
1232 FpRegs[num_regs + i].s_reg = FpRegs[i].s_reg | STARTING_DOUBLE_SREG;
Brian Carlstrom7940e442013-07-12 13:46:57 -07001233 }
1234
1235 // Sum use counts of SSA regs by original Dalvik vreg.
buzbeec729a6b2013-09-14 16:04:31 -07001236 CountRefs(core_regs, FpRegs, num_regs);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001237
Brian Carlstrom7940e442013-07-12 13:46:57 -07001238
1239 // Sort the count arrays
1240 qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts);
buzbeec729a6b2013-09-14 16:04:31 -07001241 qsort(FpRegs, num_regs * 2, sizeof(RefCounts), SortCounts);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001242
1243 if (cu_->verbose) {
1244 DumpCounts(core_regs, num_regs, "Core regs after sort");
buzbeec729a6b2013-09-14 16:04:31 -07001245 DumpCounts(FpRegs, num_regs * 2, "Fp regs after sort");
Brian Carlstrom7940e442013-07-12 13:46:57 -07001246 }
1247
1248 if (!(cu_->disable_opt & (1 << kPromoteRegs))) {
1249 // Promote FpRegs
buzbeec729a6b2013-09-14 16:04:31 -07001250 for (int i = 0; (i < (num_regs * 2)) && (FpRegs[i].count >= promotion_threshold); i++) {
1251 int p_map_idx = SRegToPMap(FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG);
1252 if ((FpRegs[i].s_reg & STARTING_DOUBLE_SREG) != 0) {
1253 if ((promotion_map_[p_map_idx].fp_location != kLocPhysReg) &&
1254 (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg)) {
1255 int low_sreg = FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG;
1256 // Ignore result - if can't alloc double may still be able to alloc singles.
1257 AllocPreservedDouble(low_sreg);
1258 }
1259 } else if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -08001260 RegStorage reg = AllocPreservedSingle(FpRegs[i].s_reg);
1261 if (!reg.Valid()) {
buzbeec729a6b2013-09-14 16:04:31 -07001262 break; // No more left.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001263 }
1264 }
1265 }
1266
1267 // Promote core regs
1268 for (int i = 0; (i < num_regs) &&
1269 (core_regs[i].count >= promotion_threshold); i++) {
1270 int p_map_idx = SRegToPMap(core_regs[i].s_reg);
1271 if (promotion_map_[p_map_idx].core_location !=
1272 kLocPhysReg) {
buzbee2700f7e2014-03-07 09:46:20 -08001273 RegStorage reg = AllocPreservedCoreReg(core_regs[i].s_reg);
1274 if (!reg.Valid()) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001275 break; // No more left
1276 }
1277 }
1278 }
1279 }
1280
1281 // Now, update SSA names to new home locations
1282 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) {
1283 RegLocation *curr = &mir_graph_->reg_location_[i];
1284 int p_map_idx = SRegToPMap(curr->s_reg_low);
1285 if (!curr->wide) {
1286 if (curr->fp) {
1287 if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) {
1288 curr->location = kLocPhysReg;
buzbee2700f7e2014-03-07 09:46:20 -08001289 curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].FpReg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001290 curr->home = true;
1291 }
1292 } else {
1293 if (promotion_map_[p_map_idx].core_location == kLocPhysReg) {
1294 curr->location = kLocPhysReg;
buzbee2700f7e2014-03-07 09:46:20 -08001295 curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].core_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001296 curr->home = true;
1297 }
1298 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001299 } else {
1300 if (curr->high_word) {
1301 continue;
1302 }
1303 if (curr->fp) {
1304 if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) &&
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001305 (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg)) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001306 int low_reg = promotion_map_[p_map_idx].FpReg;
1307 int high_reg = promotion_map_[p_map_idx+1].FpReg;
1308 // Doubles require pair of singles starting at even reg
buzbee091cc402014-03-31 10:14:40 -07001309 // TODO: move target-specific restrictions out of here.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001310 if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) {
1311 curr->location = kLocPhysReg;
buzbee091cc402014-03-31 10:14:40 -07001312 if (cu_->instruction_set == kThumb2) {
1313 curr->reg = RegStorage::FloatSolo64(RegStorage::RegNum(low_reg) >> 1);
1314 } else {
1315 curr->reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg);
1316 }
Brian Carlstrom7940e442013-07-12 13:46:57 -07001317 curr->home = true;
1318 }
1319 }
1320 } else {
1321 if ((promotion_map_[p_map_idx].core_location == kLocPhysReg)
1322 && (promotion_map_[p_map_idx+1].core_location ==
1323 kLocPhysReg)) {
1324 curr->location = kLocPhysReg;
Bill Buzbee00e1ec62014-02-27 23:44:13 +00001325 curr->reg = RegStorage(RegStorage::k64BitPair, promotion_map_[p_map_idx].core_reg,
1326 promotion_map_[p_map_idx+1].core_reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001327 curr->home = true;
1328 }
1329 }
1330 }
1331 }
1332 if (cu_->verbose) {
1333 DumpPromotionMap();
1334 }
1335}
1336
1337/* Returns sp-relative offset in bytes for a VReg */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001338int Mir2Lir::VRegOffset(int v_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001339 return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_,
Nicolas Geoffray42fcd982014-04-22 11:03:52 +00001340 fp_spill_mask_, frame_size_, v_reg,
1341 cu_->instruction_set);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001342}
1343
1344/* Returns sp-relative offset in bytes for a SReg */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001345int Mir2Lir::SRegOffset(int s_reg) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001346 return VRegOffset(mir_graph_->SRegToVReg(s_reg));
1347}
1348
1349/* Mark register usage state and return long retloc */
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001350RegLocation Mir2Lir::GetReturnWide(bool is_double) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001351 RegLocation gpr_res = LocCReturnWide();
1352 RegLocation fpr_res = LocCReturnDouble();
1353 RegLocation res = is_double ? fpr_res : gpr_res;
buzbee082833c2014-05-17 23:16:26 -07001354 Clobber(res.reg);
1355 LockTemp(res.reg);
1356 MarkWide(res.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001357 return res;
1358}
1359
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001360RegLocation Mir2Lir::GetReturn(bool is_float) {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001361 RegLocation gpr_res = LocCReturn();
1362 RegLocation fpr_res = LocCReturnFloat();
1363 RegLocation res = is_float ? fpr_res : gpr_res;
buzbee091cc402014-03-31 10:14:40 -07001364 Clobber(res.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001365 if (cu_->instruction_set == kMips) {
buzbee091cc402014-03-31 10:14:40 -07001366 MarkInUse(res.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001367 } else {
buzbee091cc402014-03-31 10:14:40 -07001368 LockTemp(res.reg);
Brian Carlstrom7940e442013-07-12 13:46:57 -07001369 }
1370 return res;
1371}
1372
Brian Carlstrom2ce745c2013-07-17 17:44:30 -07001373void Mir2Lir::SimpleRegAlloc() {
Brian Carlstrom7940e442013-07-12 13:46:57 -07001374 DoPromotion();
1375
1376 if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) {
1377 LOG(INFO) << "After Promotion";
1378 mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs());
1379 }
1380
1381 /* Set the frame size */
1382 frame_size_ = ComputeFrameSize();
1383}
1384
1385/*
1386 * Get the "real" sreg number associated with an s_reg slot. In general,
1387 * s_reg values passed through codegen are the SSA names created by
1388 * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location
1389 * array. However, renaming is accomplished by simply replacing RegLocation
1390 * entries in the reglocation[] array. Therefore, when location
1391 * records for operands are first created, we need to ask the locRecord
1392 * identified by the dataflow pass what it's new name is.
1393 */
1394int Mir2Lir::GetSRegHi(int lowSreg) {
1395 return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1;
1396}
1397
buzbee091cc402014-03-31 10:14:40 -07001398bool Mir2Lir::LiveOut(int s_reg) {
Brian Carlstrom7934ac22013-07-26 10:54:15 -07001399 // For now.
Brian Carlstrom7940e442013-07-12 13:46:57 -07001400 return true;
1401}
1402
Brian Carlstrom7940e442013-07-12 13:46:57 -07001403} // namespace art