Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
| 19 | #include "stringprintf.h" |
| 20 | |
| 21 | #include <iostream> |
| 22 | |
| 23 | namespace art { |
| 24 | namespace arm { |
| 25 | |
| 26 | DisassemblerArm::DisassemblerArm() { |
| 27 | } |
| 28 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 29 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 30 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 31 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 32 | DumpArm(os, cur); |
| 33 | } |
| 34 | } else { |
| 35 | // remove thumb specifier bits |
| 36 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 37 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 38 | for (const uint8_t* cur = begin; cur < end;) { |
| 39 | cur += DumpThumb16(os, cur); |
| 40 | } |
| 41 | } |
| 42 | } |
| 43 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 44 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 45 | "eq", // 0000 - equal |
| 46 | "ne", // 0001 - not-equal |
| 47 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 48 | "cc", // 0011 - carry-clear, less than |
| 49 | "mi", // 0100 - minus, negative |
| 50 | "pl", // 0101 - plus, positive or zero |
| 51 | "vs", // 0110 - overflow |
| 52 | "vc", // 0111 - no overflow |
| 53 | "hi", // 1000 - unsigned higher |
| 54 | "ls", // 1001 - unsigned lower or same |
| 55 | "ge", // 1010 - signed greater than or equal |
| 56 | "lt", // 1011 - signed less than |
| 57 | "gt", // 1100 - signed greater than |
| 58 | "le", // 1101 - signed less than or equal |
| 59 | "", // 1110 - always |
| 60 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 64 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 65 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 66 | } else { |
| 67 | os << "Unexpected condition: " << cond; |
| 68 | } |
| 69 | } |
| 70 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 71 | void DisassemblerArm::DumpReg(std::ostream& os, uint32_t reg) { |
| 72 | switch (reg) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 73 | case 13: os << "sp"; break; |
| 74 | case 14: os << "lr"; break; |
| 75 | case 15: os << "pc"; break; |
| 76 | default: os << "r" << reg; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 80 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
| 81 | os << imm32 << " (" << reinterpret_cast<const void*>(instr_ptr + imm32) << ")"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 85 | return ptr[0] | (ptr[1] << 8); |
| 86 | } |
| 87 | |
| 88 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 89 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 90 | } |
| 91 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 92 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 93 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 94 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 95 | }; |
| 96 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame^] | 97 | static const char* kThumbDataProcessingOperations[] = { |
| 98 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 99 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 100 | }; |
| 101 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 102 | struct ArmRegister { |
| 103 | ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
| 104 | uint32_t r; |
| 105 | }; |
| 106 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 107 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 108 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 109 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 110 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 111 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 112 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 113 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 114 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 115 | } |
| 116 | return os; |
| 117 | } |
| 118 | |
| 119 | struct Rd : ArmRegister { |
| 120 | Rd(uint32_t instruction) : ArmRegister((instruction >> 12) & 0xf) {} |
| 121 | }; |
| 122 | typedef Rd Rt; |
| 123 | struct Rn : ArmRegister { |
| 124 | Rn(uint32_t instruction) : ArmRegister((instruction >> 16) & 0xf) {} |
| 125 | }; |
| 126 | |
| 127 | struct Rm { |
| 128 | Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
| 129 | uint32_t shift; |
| 130 | ArmRegister rm; |
| 131 | }; |
| 132 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 133 | os << r.rm; |
| 134 | if (r.shift != 0) { |
| 135 | os << "-shift-" << r.shift; // TODO |
| 136 | } |
| 137 | return os; |
| 138 | } |
| 139 | |
| 140 | struct Imm12 { |
| 141 | Imm12(uint32_t instruction) : rotate((instruction >> 8) & 0xf), imm(instruction & 0xff) {} |
| 142 | uint32_t rotate; |
| 143 | uint32_t imm; |
| 144 | }; |
| 145 | std::ostream& operator<<(std::ostream& os, const Imm12& rhs) { |
| 146 | uint32_t imm = (rhs.imm >> (2 * rhs.rotate)) | (rhs.imm << (32 - (2 * rhs.rotate))); |
| 147 | os << "#" << imm; |
| 148 | return os; |
| 149 | } |
| 150 | |
| 151 | struct RegisterList { |
| 152 | RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
| 153 | uint32_t register_list; |
| 154 | }; |
| 155 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 156 | if (rhs.register_list == 0) { |
| 157 | os << "<no register list?>"; |
| 158 | return os; |
| 159 | } |
| 160 | bool first = true; |
| 161 | for (size_t i = 0; i < 16; i++) { |
| 162 | if ((rhs.register_list & (1 << i)) != 0) { |
| 163 | if (first) { |
| 164 | os << "{"; |
| 165 | first = false; |
| 166 | } else { |
| 167 | os << ", "; |
| 168 | } |
| 169 | os << ArmRegister(i); |
| 170 | } |
| 171 | } |
| 172 | os << "}"; |
| 173 | return os; |
| 174 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 175 | |
| 176 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 177 | uint32_t instruction = ReadU32(instr_ptr); |
| 178 | uint32_t cond = (instruction >> 28) & 0xf; |
| 179 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 180 | std::ostringstream opcode; |
| 181 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 182 | switch (op1) { |
| 183 | case 0: |
| 184 | case 1: // Data processing instructions. |
| 185 | { |
| 186 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 187 | opcode << (((instruction >> 5) & 1) ? "blx" : "bx"); |
| 188 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 189 | break; |
| 190 | } |
| 191 | bool i = (instruction & (1 << 25)) != 0; |
| 192 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 193 | opcode << kDataProcessingOperations[(instruction >> 21) & 0xf] |
| 194 | << kConditionCodeNames[cond] |
| 195 | << (s ? "s" : ""); |
| 196 | args << Rd(instruction) << ", "; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 197 | if (i) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 198 | args << Rn(instruction) << ", " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 199 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 200 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 201 | } |
| 202 | } |
| 203 | break; |
| 204 | case 2: // Load/store word and unsigned byte. |
| 205 | { |
| 206 | bool p = (instruction & (1 << 24)) != 0; |
| 207 | bool b = (instruction & (1 << 22)) != 0; |
| 208 | bool w = (instruction & (1 << 21)) != 0; |
| 209 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 210 | opcode << (l ? "ldr" : "str") << (b ? "b" : "") << kConditionCodeNames[cond]; |
| 211 | args << Rt(instruction) << ", "; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 212 | if (Rn(instruction).r == 0xf) { |
| 213 | UNIMPLEMENTED(FATAL) << "literals"; |
| 214 | } else { |
| 215 | bool wback = !p || w; |
| 216 | if (p && !wback) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 217 | args << "[" << Rn(instruction) << ", " << Imm12(instruction) << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 218 | } else if (p && wback) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 219 | args << "[" << Rn(instruction) << ", " << Imm12(instruction) << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 220 | } else if (!p && wback) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 221 | args << "[" << Rn(instruction) << "], " << Imm12(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 222 | } else { |
| 223 | LOG(FATAL) << p << " " << w; |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | break; |
| 228 | case 4: // Load/store multiple. |
| 229 | { |
| 230 | bool p = (instruction & (1 << 24)) != 0; |
| 231 | bool u = (instruction & (1 << 23)) != 0; |
| 232 | bool w = (instruction & (1 << 21)) != 0; |
| 233 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 234 | opcode << (l ? "ldm" : "stm") |
| 235 | << (u ? 'i' : 'd') |
| 236 | << (p ? 'b' : 'a') |
| 237 | << kConditionCodeNames[cond]; |
| 238 | args << Rn(instruction) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 239 | } |
| 240 | break; |
| 241 | default: |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 242 | opcode << "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 243 | break; |
| 244 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 245 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
| 246 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instruction, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 250 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 251 | // |111|1 1|1000000|0000|1111110000000000| |
| 252 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 253 | // |---|---|-------|----|----------------| |
| 254 | // |332|2 2|2222222|1111|1111110000000000| |
| 255 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 256 | // |---|---|-------|----|----------------| |
| 257 | // |111|op1| op2 | | | |
| 258 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 259 | if (op1 == 0) { |
| 260 | return DumpThumb16(os, instr_ptr); |
| 261 | } |
| 262 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 263 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 264 | std::ostringstream opcode; |
| 265 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 266 | switch (op1) { |
| 267 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 268 | break; |
| 269 | case 1: |
| 270 | switch (op2) { |
| 271 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0A: case 0x0B: |
| 272 | case 0x10: case 0x11: case 0x12: case 0x13: case 0x18: case 0x19: case 0x1A: case 0x1B: { |
| 273 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 274 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 275 | // |---|--|--|--|-|--|----|----------------| |
| 276 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 277 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 278 | // |---|--|--|--|-|--|----|----------------| |
| 279 | // |111|01|00|op|0|WL| Rn | | |
| 280 | // |111|01| op2 | | | |
| 281 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 282 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 283 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 284 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 285 | uint32_t op = (instr >> 23) & 3; |
| 286 | uint32_t W = (instr >> 21) & 1; |
| 287 | uint32_t L = (instr >> 20) & 1; |
| 288 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 289 | if (op == 1 || op == 2) { |
| 290 | if (op == 1) { |
| 291 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 292 | opcode << "stm"; |
| 293 | DumpReg(args, Rn); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 294 | if (W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 295 | args << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 296 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 297 | args << "!, "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 298 | } |
| 299 | } else { |
| 300 | if (Rn != 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 301 | opcode << "ldm"; |
| 302 | DumpReg(args, Rn); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 303 | if (W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 304 | args << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 305 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 306 | args << "!, "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 307 | } |
| 308 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 309 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 310 | } |
| 311 | } |
| 312 | } else { |
| 313 | if (L == 0) { |
| 314 | if (Rn != 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 315 | opcode << "stmdb"; |
| 316 | DumpReg(args, Rn); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 317 | if (W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 318 | args << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 319 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 320 | args << "!, "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 321 | } |
| 322 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 323 | opcode << "push"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 324 | } |
| 325 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 326 | opcode << "ldmdb"; |
| 327 | DumpReg(args, Rn); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 328 | if (W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 329 | args << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 330 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 331 | args << "!, "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 332 | } |
| 333 | } |
| 334 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 335 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 336 | } |
| 337 | break; |
| 338 | } |
| 339 | default: |
| 340 | break; |
| 341 | } |
| 342 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 343 | case 2: |
| 344 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 345 | // Data-processing (modified immediate) |
| 346 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 347 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 348 | // |---|--|--|----|-|----|-|---|----|--------| |
| 349 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 350 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 351 | // |---|--|--|----|-|----|-|---|----|--------| |
| 352 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 353 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
| 354 | // 111 10 00 0110 0 0000 1 000 0000 10101101 - f0c080ad |
| 355 | uint32_t i = (instr >> 26) & 1; |
| 356 | uint32_t op3 = (instr >> 21) & 0xF; |
| 357 | uint32_t S = (instr >> 20) & 1; |
| 358 | uint32_t Rn = (instr >> 16) & 0xF; |
| 359 | uint32_t imm3 = (instr >> 12) & 7; |
| 360 | uint32_t Rd = (instr >> 8) & 0xF; |
| 361 | uint32_t imm8 = instr & 0xFF; |
| 362 | int32_t imm32 = (i << 12) | (imm3 << 8) | imm8; |
| 363 | switch (op3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 364 | case 0x0: opcode << "and"; break; |
| 365 | case 0x1: opcode << "bic"; break; |
| 366 | case 0x2: opcode << "orr"; break; |
| 367 | case 0x3: opcode << "orn"; break; |
| 368 | case 0x4: opcode << "eor"; break; |
| 369 | case 0x8: opcode << "add"; break; |
| 370 | case 0xA: opcode << "adc"; break; |
| 371 | case 0xB: opcode << "sbc"; break; |
| 372 | case 0xD: opcode << "sub"; break; |
| 373 | case 0xE: opcode << "rsb"; break; |
| 374 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 375 | } |
| 376 | if (S == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 377 | opcode << "s"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 378 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 379 | DumpReg(args, Rd); |
| 380 | args << ", "; |
| 381 | DumpReg(args, Rn); |
| 382 | args << ", ThumbExpand(" << imm32 << ")"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 383 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 384 | // Data-processing (plain binary immediate) |
| 385 | // |111|11|10|00000|0000|1|111110000000000| |
| 386 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 387 | // |---|--|--|-----|----|-|---------------| |
| 388 | // |332|22|22|22222|1111|1|111110000000000| |
| 389 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 390 | // |---|--|--|-----|----|-|---------------| |
| 391 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 392 | uint32_t op3 = (instr >> 20) & 0x1F; |
| 393 | uint32_t Rn = (instr >> 16) & 0xF; |
| 394 | switch (op3) { |
| 395 | case 0x04: { |
| 396 | // MOVW Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
| 397 | uint32_t Rd = (instr >> 8) & 0xF; |
| 398 | uint32_t i = (instr >> 26) & 1; |
| 399 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 400 | uint32_t imm8 = instr & 0xFF; |
| 401 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 402 | opcode << "movw"; |
| 403 | DumpReg(args, Rd); |
| 404 | args << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 405 | break; |
| 406 | } |
| 407 | case 0x0A: { |
| 408 | // SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
| 409 | uint32_t Rd = (instr >> 8) & 0xF; |
| 410 | uint32_t i = (instr >> 26) & 1; |
| 411 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 412 | uint32_t imm8 = instr & 0xFF; |
| 413 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 414 | opcode << "sub.w"; |
| 415 | DumpReg(args, Rd); |
| 416 | args << ", "; |
| 417 | DumpReg(args, Rn); |
| 418 | args << ", #" << imm12; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 419 | break; |
| 420 | } |
| 421 | default: |
| 422 | break; |
| 423 | } |
| 424 | } else { |
| 425 | // Branches and miscellaneous control |
| 426 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 427 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 428 | // |---|--|-------|----|-|---|----|--------| |
| 429 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 430 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 431 | // |---|--|-------|----|-|---|----|--------| |
| 432 | // |111|10| op2 | |1|op3|op4 | | |
| 433 | |
| 434 | uint32_t op3 = (instr >> 12) & 7; |
| 435 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 436 | switch (op3) { |
| 437 | case 0: |
| 438 | if ((op2 & 0x38) != 0x38) { |
| 439 | // Conditional branch |
| 440 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 441 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 442 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 443 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 444 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 445 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 446 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 447 | uint32_t S = (instr >> 26) & 1; |
| 448 | uint32_t J2 = (instr >> 11) & 1; |
| 449 | uint32_t J1 = (instr >> 13) & 1; |
| 450 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 451 | uint32_t imm11 = instr & 0x7FF; |
| 452 | uint32_t cond = (instr >> 22) & 0xF; |
| 453 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 454 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 455 | opcode << "b"; |
| 456 | DumpCond(opcode, cond); |
| 457 | opcode << ".w"; |
| 458 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 459 | } |
| 460 | break; |
| 461 | case 2: |
| 462 | case 1: case 3: |
| 463 | break; |
| 464 | case 4: case 6: case 5: case 7: { |
| 465 | // BL, BLX (immediate) |
| 466 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 467 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 468 | // |---|--|-|----------|--|--|-|--|-----------| |
| 469 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 470 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 471 | // |---|--|-|----------|--|--|-|--|-----------| |
| 472 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 473 | uint32_t S = (instr >> 26) & 1; |
| 474 | uint32_t J2 = (instr >> 11) & 1; |
| 475 | uint32_t L = (instr >> 12) & 1; |
| 476 | uint32_t J1 = (instr >> 13) & 1; |
| 477 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 478 | uint32_t imm11 = instr & 0x7FF; |
| 479 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 480 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 481 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 482 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 483 | } |
| 484 | uint32_t I1 = ~(J1 ^ S); |
| 485 | uint32_t I2 = ~(J2 ^ S); |
| 486 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 487 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 488 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 489 | break; |
| 490 | } |
| 491 | } |
| 492 | } |
| 493 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 494 | case 3: |
| 495 | switch (op2) { |
| 496 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 497 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 498 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 499 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 500 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 501 | // |---|--|---|---|-|----|----|------|------| |
| 502 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 503 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 504 | // |---|--|---|---|-|----|----|------|------| |
| 505 | // |111|11|000|op3|0| | | op4 | | |
| 506 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 507 | uint32_t op3 = (instr >> 21) & 7; |
| 508 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 509 | switch (op3) { |
| 510 | case 0x2: case 0x6: { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 511 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
| 512 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 513 | uint32_t Rn = (instr >> 16) & 0xF; |
| 514 | uint32_t Rt = (instr >> 12) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 515 | if (op3 == 2) { |
| 516 | uint32_t P = (instr >> 10) & 1; |
| 517 | uint32_t U = (instr >> 9) & 1; |
| 518 | uint32_t W = (instr >> 8) & 1; |
| 519 | uint32_t imm8 = instr & 0xFF; |
| 520 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 521 | if (Rn == 13 && P == 1 && U == 0 && W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 522 | opcode << "push"; |
| 523 | DumpReg(args, Rt); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 524 | } else if (Rn == 15 || (P == 0 && W == 0)) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 525 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 526 | } else { |
| 527 | if (P == 1 && U == 1 && W == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 528 | opcode << "strt"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 529 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 530 | opcode << "str"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 531 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 532 | DumpReg(args, Rt); |
| 533 | args << ", ["; |
| 534 | DumpReg(args, Rn); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 535 | if (P == 0 && W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 536 | args << "], #" << imm32; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 537 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 538 | args << ", #" << imm32 << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 539 | if (W == 1) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 540 | args << "!"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 541 | } |
| 542 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 543 | } |
| 544 | } else if (op3 == 6) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 545 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 546 | opcode << "str.w"; |
| 547 | DumpReg(args, Rt); |
| 548 | args << ", ["; |
| 549 | DumpReg(args, Rn); |
| 550 | args << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 551 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 552 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 553 | } |
| 554 | } |
| 555 | |
| 556 | break; |
| 557 | } |
| 558 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 559 | // Load word |
| 560 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 561 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 562 | // |---|--|--|---|--|-|----|----|------|------| |
| 563 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 564 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 565 | // |---|--|--|---|--|-|----|----|------|------| |
| 566 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 567 | // |111|11| op2 | | | imm12 | |
| 568 | uint32_t op3 = (instr >> 23) & 3; |
| 569 | uint32_t op4 = (instr >> 6) & 0x3F; |
| 570 | uint32_t Rn = (instr >> 16) & 0xF; |
| 571 | uint32_t Rt = (instr >> 12) & 0xF; |
| 572 | if (op3 == 1 || Rn == 15) { |
| 573 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 574 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 575 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 576 | opcode << "ldr.w"; |
| 577 | DumpReg(args, Rt); |
| 578 | args << ", ["; |
| 579 | DumpReg(args, Rn); |
| 580 | args << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 581 | } else if (op4 == 0) { |
| 582 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 583 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 584 | uint32_t rm = instr & 0xF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 585 | opcode << "ldr.w"; |
| 586 | DumpReg(args, Rt); |
| 587 | args << ", ["; |
| 588 | DumpReg(args, Rn); |
| 589 | args << ", "; |
| 590 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 591 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 592 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 593 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 594 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 595 | } else { |
| 596 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 597 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 598 | opcode << "ldrt"; |
| 599 | DumpReg(args, Rt); |
| 600 | args << ", ["; |
| 601 | DumpReg(args, Rn); |
| 602 | args << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 603 | } |
| 604 | break; |
| 605 | } |
| 606 | } |
| 607 | default: |
| 608 | break; |
| 609 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 610 | os << StringPrintf("\t\t\t%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 611 | return 4; |
| 612 | } |
| 613 | |
| 614 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 615 | uint16_t instr = ReadU16(instr_ptr); |
| 616 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 617 | if (is_32bit) { |
| 618 | return DumpThumb32(os, instr_ptr); |
| 619 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 620 | std::ostringstream opcode; |
| 621 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 622 | uint16_t opcode1 = instr >> 10; |
| 623 | if (opcode1 < 0x10) { |
| 624 | // shift (immediate), add, subtract, move, and compare |
| 625 | uint16_t opcode2 = instr >> 9; |
| 626 | switch (opcode2) { |
| 627 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 628 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 629 | // Logical shift left - 00 000xx xxxxxxxxx |
| 630 | // Logical shift right - 00 001xx xxxxxxxxx |
| 631 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 632 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 633 | uint16_t rm = (instr >> 3) & 7; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 634 | uint16_t Rd = instr & 7; |
| 635 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 636 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 637 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 638 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 639 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 640 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 641 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 642 | DumpReg(args, Rd); |
| 643 | args << ", "; |
| 644 | DumpReg(args, rm); |
| 645 | args << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 646 | break; |
| 647 | } |
| 648 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 649 | // Add register - 00 01100 mmm nnn ddd |
| 650 | // Sub register - 00 01101 mmm nnn ddd |
| 651 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 652 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 653 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
| 654 | uint16_t Rn = (instr >> 3) & 7; |
| 655 | uint16_t Rd = instr & 7; |
| 656 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 657 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 658 | } else { |
| 659 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 660 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 661 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 662 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 663 | } |
| 664 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 665 | DumpReg(args, Rd); |
| 666 | args << ", "; |
| 667 | DumpReg(args, Rn); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 668 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 669 | args << ", "; |
| 670 | DumpReg(args, imm3_or_Rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 671 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 672 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 673 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 674 | break; |
| 675 | } |
| 676 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 677 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 678 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 679 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 680 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 681 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 682 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 683 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
| 684 | uint16_t Rn = (instr >> 8) & 7; |
| 685 | uint16_t imm8 = instr & 0xFF; |
| 686 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 687 | case 4: opcode << "movs"; break; |
| 688 | case 5: opcode << "cmp"; break; |
| 689 | case 6: opcode << "adds"; break; |
| 690 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 691 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 692 | DumpReg(args, Rn); |
| 693 | args << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 694 | break; |
| 695 | } |
| 696 | default: |
| 697 | break; |
| 698 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame^] | 699 | } else if (opcode1 == 0x10) { |
| 700 | // Data-processing |
| 701 | uint16_t opcode2 = (instr >> 6) & 0xF; |
| 702 | uint16_t rm = (instr >> 3) & 0x7; |
| 703 | uint16_t rdn = instr & 7; |
| 704 | opcode << kThumbDataProcessingOperations[opcode2]; |
| 705 | DumpReg(args, rdn); |
| 706 | args << ", "; |
| 707 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 708 | } else if (opcode1 == 0x11) { |
| 709 | // Special data instructions and branch and exchange |
| 710 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 711 | switch (opcode2) { |
| 712 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 713 | // Add low registers - 010001 0000 xxxxxx |
| 714 | // Add high registers - 010001 0001/001x xxxxxx |
| 715 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 716 | uint16_t rm = (instr >> 3) & 0xF; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 717 | uint16_t Rdn = instr & 7; |
| 718 | uint16_t DN_Rdn = (DN << 3) | Rdn; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 719 | opcode << "add"; |
| 720 | DumpReg(args, DN_Rdn); |
| 721 | args << ", "; |
| 722 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 723 | break; |
| 724 | } |
| 725 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 726 | // Move low registers - 010001 1000 xxxxxx |
| 727 | // Move high registers - 010001 1001/101x xxxxxx |
| 728 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 729 | uint16_t rm = (instr >> 3) & 0xF; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 730 | uint16_t Rdn = instr & 7; |
| 731 | uint16_t DN_Rdn = (DN << 3) | Rdn; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 732 | opcode << "mov"; |
| 733 | DumpReg(args, DN_Rdn); |
| 734 | args << ", "; |
| 735 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 736 | break; |
| 737 | } |
| 738 | case 0x5: case 0x6: case 0x7: { |
| 739 | // Compare high registers - 010001 0101/011x xxxxxx |
| 740 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 741 | uint16_t rm = (instr >> 3) & 0xF; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 742 | uint16_t Rn = instr & 7; |
| 743 | uint16_t N_Rn = (N << 3) | Rn; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 744 | opcode << "cmp"; |
| 745 | DumpReg(args, N_Rn); |
| 746 | args << ", "; |
| 747 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 748 | break; |
| 749 | } |
| 750 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 751 | // Branch and exchange - 010001 110x xxxxxx |
| 752 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 753 | uint16_t rm = instr >> 3 & 0xF; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 754 | if ((opcode2 & 0x2) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 755 | opcode << "bx"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 756 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 757 | opcode << "blx"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 758 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 759 | DumpReg(args, rm); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 760 | break; |
| 761 | } |
| 762 | default: |
| 763 | break; |
| 764 | } |
| 765 | } else if ((instr & 0xF000) == 0xB000) { |
| 766 | // Miscellaneous 16-bit instructions |
| 767 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 768 | switch (opcode2) { |
| 769 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 770 | // Add immediate to SP - 1011 00000 ii iiiii |
| 771 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 772 | int imm7 = instr & 0x7F; |
| 773 | if ((opcode2 & 4) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 774 | opcode << "add"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 775 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 776 | opcode << "sub"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 777 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 778 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 779 | break; |
| 780 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 781 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 782 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 783 | // If-Then, and hints |
| 784 | uint16_t opA = (instr >> 4) & 0xF; |
| 785 | uint16_t opB = instr & 0xF; |
| 786 | if (opB == 0) { |
| 787 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 788 | case 0: opcode << "nop"; break; |
| 789 | case 1: opcode << "yield"; break; |
| 790 | case 2: opcode << "wfe"; break; |
| 791 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 792 | default: break; |
| 793 | } |
| 794 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 795 | opcode << "it"; |
| 796 | args << reinterpret_cast<void*>(opB) << " "; |
| 797 | DumpCond(args, opA); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 798 | } |
| 799 | break; |
| 800 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 801 | default: |
| 802 | break; |
| 803 | } |
| 804 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 805 | ((instr & 0xE000) == 0x8000)) { |
| 806 | // Load/store single data item |
| 807 | uint16_t opA = instr >> 12; |
| 808 | //uint16_t opB = (instr >> 9) & 7; |
| 809 | switch (opA) { |
| 810 | case 0x6: { |
| 811 | // STR Rt, Rn, #imm - 01100 iiiii nnn ttt |
| 812 | // LDR Rt, Rn, #imm - 01101 iiiii nnn ttt |
| 813 | uint16_t imm5 = (instr >> 6) & 0x1F; |
| 814 | uint16_t Rn = (instr >> 3) & 7; |
| 815 | uint16_t Rt = instr & 7; |
| 816 | if ((instr & 0x800) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 817 | opcode << "str"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 818 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 819 | opcode << "ldr"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 820 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 821 | DumpReg(args, Rt); |
| 822 | args << ", ["; |
| 823 | DumpReg(args, Rn); |
| 824 | args << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 825 | break; |
| 826 | } |
| 827 | case 0x9: { |
| 828 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 829 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 830 | uint16_t imm8 = instr & 0xFF; |
| 831 | uint16_t Rt = (instr >> 8) & 7; |
| 832 | if ((instr & 0x800) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 833 | opcode << "str"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 834 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 835 | opcode << "ldr"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 836 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 837 | DumpReg(args, Rt); |
| 838 | args << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 839 | break; |
| 840 | } |
| 841 | default: |
| 842 | break; |
| 843 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 844 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 845 | uint16_t imm11 = instr & 0x7FFF; |
| 846 | int32_t imm32 = imm11 << 1; |
| 847 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 848 | opcode << "b"; |
| 849 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 850 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 851 | os << StringPrintf("\t\t\t%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 852 | } |
| 853 | return 2; |
| 854 | } |
| 855 | |
| 856 | } // namespace arm |
| 857 | } // namespace art |