Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "mir_to_lir.h" |
| 21 | |
| 22 | #include "dex/compiler_internals.h" |
| 23 | |
| 24 | namespace art { |
| 25 | |
| 26 | /* Mark a temp register as dead. Does not affect allocation state. */ |
| 27 | inline void Mir2Lir::ClobberBody(RegisterInfo* p) { |
| 28 | if (p->is_temp) { |
| 29 | DCHECK(!(p->live && p->dirty)) << "Live & dirty temp in clobber"; |
| 30 | p->live = false; |
| 31 | p->s_reg = INVALID_SREG; |
| 32 | p->def_start = NULL; |
| 33 | p->def_end = NULL; |
| 34 | if (p->pair) { |
| 35 | p->pair = false; |
buzbee | 56c7178 | 2013-09-05 17:13:19 -0700 | [diff] [blame] | 36 | p = GetRegInfo(p->partner); |
| 37 | p->pair = false; |
| 38 | p->live = false; |
| 39 | p->s_reg = INVALID_SREG; |
| 40 | p->def_start = NULL; |
| 41 | p->def_end = NULL; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 42 | } |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | inline LIR* Mir2Lir::RawLIR(int dalvik_offset, int opcode, int op0, |
| 47 | int op1, int op2, int op3, int op4, LIR* target) { |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 48 | LIR* insn = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), ArenaAllocator::kAllocLIR)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | insn->dalvik_offset = dalvik_offset; |
| 50 | insn->opcode = opcode; |
| 51 | insn->operands[0] = op0; |
| 52 | insn->operands[1] = op1; |
| 53 | insn->operands[2] = op2; |
| 54 | insn->operands[3] = op3; |
| 55 | insn->operands[4] = op4; |
| 56 | insn->target = target; |
| 57 | SetupResourceMasks(insn); |
| 58 | if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || |
| 59 | (opcode == kPseudoExportedPC)) { |
| 60 | // Always make labels scheduling barriers |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 61 | DCHECK(!insn->flags.use_def_invalid); |
| 62 | insn->u.m.use_mask = insn->u.m.def_mask = ENCODE_ALL; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 63 | } |
| 64 | return insn; |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * The following are building blocks to construct low-level IRs with 0 - 4 |
| 69 | * operands. |
| 70 | */ |
| 71 | inline LIR* Mir2Lir::NewLIR0(int opcode) { |
| 72 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) |
| 73 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 74 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 75 | << current_dalvik_offset_; |
| 76 | LIR* insn = RawLIR(current_dalvik_offset_, opcode); |
| 77 | AppendLIR(insn); |
| 78 | return insn; |
| 79 | } |
| 80 | |
| 81 | inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) { |
| 82 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_UNARY_OP)) |
| 83 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 84 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 85 | << current_dalvik_offset_; |
| 86 | LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest); |
| 87 | AppendLIR(insn); |
| 88 | return insn; |
| 89 | } |
| 90 | |
| 91 | inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) { |
| 92 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_BINARY_OP)) |
| 93 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 94 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 95 | << current_dalvik_offset_; |
| 96 | LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1); |
| 97 | AppendLIR(insn); |
| 98 | return insn; |
| 99 | } |
| 100 | |
| 101 | inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { |
| 102 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_TERTIARY_OP)) |
| 103 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 104 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 105 | << current_dalvik_offset_; |
| 106 | LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2); |
| 107 | AppendLIR(insn); |
| 108 | return insn; |
| 109 | } |
| 110 | |
| 111 | inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { |
| 112 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP)) |
| 113 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 114 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 115 | << current_dalvik_offset_; |
| 116 | LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info); |
| 117 | AppendLIR(insn); |
| 118 | return insn; |
| 119 | } |
| 120 | |
| 121 | inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, |
| 122 | int info2) { |
| 123 | DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_QUIN_OP)) |
| 124 | << GetTargetInstName(opcode) << " " << opcode << " " |
| 125 | << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " |
| 126 | << current_dalvik_offset_; |
| 127 | LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2); |
| 128 | AppendLIR(insn); |
| 129 | return insn; |
| 130 | } |
| 131 | |
| 132 | /* |
| 133 | * Mark the corresponding bit(s). |
| 134 | */ |
| 135 | inline void Mir2Lir::SetupRegMask(uint64_t* mask, int reg) { |
| 136 | *mask |= GetRegMaskCommon(reg); |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * Set up the proper fields in the resource mask |
| 141 | */ |
| 142 | inline void Mir2Lir::SetupResourceMasks(LIR* lir) { |
| 143 | int opcode = lir->opcode; |
| 144 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 145 | if ((opcode < 0) && (opcode != kPseudoBarrier)) { |
| 146 | lir->flags.fixup = kFixupLabel; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 147 | return; |
| 148 | } |
| 149 | |
| 150 | uint64_t flags = GetTargetInstFlags(opcode); |
| 151 | |
| 152 | if (flags & NEEDS_FIXUP) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 153 | // Note: target-specific setup may specialize the fixup kind. |
| 154 | lir->flags.fixup = kFixupLabel; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | /* Get the starting size of the instruction's template */ |
| 158 | lir->flags.size = GetInsnSize(lir); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 159 | estimated_native_code_size_ += lir->flags.size; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 160 | /* Set up the mask for resources that are updated */ |
| 161 | if (flags & (IS_LOAD | IS_STORE)) { |
| 162 | /* Default to heap - will catch specialized classes later */ |
| 163 | SetMemRefType(lir, flags & IS_LOAD, kHeapRef); |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * Conservatively assume the branch here will call out a function that in |
| 168 | * turn will trash everything. |
| 169 | */ |
| 170 | if (flags & IS_BRANCH) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 171 | lir->u.m.def_mask = lir->u.m.use_mask = ENCODE_ALL; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 172 | return; |
| 173 | } |
| 174 | |
| 175 | if (flags & REG_DEF0) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 176 | SetupRegMask(&lir->u.m.def_mask, lir->operands[0]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | if (flags & REG_DEF1) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 180 | SetupRegMask(&lir->u.m.def_mask, lir->operands[1]); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 181 | } |
| 182 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 183 | if (flags & REG_USE0) { |
| 184 | SetupRegMask(&lir->u.m.use_mask, lir->operands[0]); |
| 185 | } |
| 186 | |
| 187 | if (flags & REG_USE1) { |
| 188 | SetupRegMask(&lir->u.m.use_mask, lir->operands[1]); |
| 189 | } |
| 190 | |
| 191 | if (flags & REG_USE2) { |
| 192 | SetupRegMask(&lir->u.m.use_mask, lir->operands[2]); |
| 193 | } |
| 194 | |
| 195 | if (flags & REG_USE3) { |
| 196 | SetupRegMask(&lir->u.m.use_mask, lir->operands[3]); |
| 197 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 198 | |
| 199 | if (flags & SETS_CCODES) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 200 | lir->u.m.def_mask |= ENCODE_CCODE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | if (flags & USES_CCODES) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 204 | lir->u.m.use_mask |= ENCODE_CCODE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | // Handle target-specific actions |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame^] | 208 | SetupTargetResourceMasks(lir, flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 209 | } |
| 210 | |
buzbee | bd663de | 2013-09-10 15:41:31 -0700 | [diff] [blame] | 211 | inline art::Mir2Lir::RegisterInfo* Mir2Lir::GetRegInfo(int reg) { |
| 212 | DCHECK(reginfo_map_.Get(reg) != NULL); |
| 213 | return reginfo_map_.Get(reg); |
| 214 | } |
| 215 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 216 | } // namespace art |
| 217 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 218 | #endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ |