Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |
| 19 | |
| 20 | #include "arm64_lir.h" |
| 21 | #include "dex/compiler_internals.h" |
| 22 | |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 23 | #include <map> |
| 24 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 25 | namespace art { |
| 26 | |
Andreas Gampe | 4b537a8 | 2014-06-30 22:24:53 -0700 | [diff] [blame] | 27 | class Arm64Mir2Lir FINAL : public Mir2Lir { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 28 | protected: |
| 29 | // TODO: consolidate 64-bit target support. |
| 30 | class InToRegStorageMapper { |
| 31 | public: |
Zheng Xu | 949cd97 | 2014-06-23 18:33:08 +0800 | [diff] [blame] | 32 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 33 | virtual ~InToRegStorageMapper() {} |
| 34 | }; |
| 35 | |
| 36 | class InToRegStorageArm64Mapper : public InToRegStorageMapper { |
| 37 | public: |
| 38 | InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} |
| 39 | virtual ~InToRegStorageArm64Mapper() {} |
Zheng Xu | 949cd97 | 2014-06-23 18:33:08 +0800 | [diff] [blame] | 40 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 41 | private: |
| 42 | int cur_core_reg_; |
| 43 | int cur_fp_reg_; |
| 44 | }; |
| 45 | |
| 46 | class InToRegStorageMapping { |
| 47 | public: |
| 48 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 49 | initialized_(false) {} |
| 50 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 51 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 52 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 53 | RegStorage Get(int in_position); |
| 54 | bool IsInitialized() { return initialized_; } |
| 55 | private: |
| 56 | std::map<int, RegStorage> mapping_; |
| 57 | int max_mapped_in_; |
| 58 | bool is_there_stack_mapped_; |
| 59 | bool initialized_; |
| 60 | }; |
| 61 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 62 | public: |
| 63 | Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
| 64 | |
| 65 | // Required for target - codegen helpers. |
| 66 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
Matteo Franchin | c61b3c9 | 2014-06-18 11:52:47 +0100 | [diff] [blame] | 67 | RegLocation rl_dest, int lit) OVERRIDE; |
| 68 | bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, |
| 69 | RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 70 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 71 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 72 | RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; |
| 73 | RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 74 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 75 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
| 76 | LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 77 | VolatileKind is_volatile) |
| 78 | OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 79 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 80 | OpSize size) OVERRIDE; |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 81 | LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 82 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 83 | RegStorage r_dest, OpSize size) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 84 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 85 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 86 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 87 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
| 88 | LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, |
| 89 | VolatileKind is_volatile) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 90 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 91 | OpSize size) OVERRIDE; |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 92 | LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 93 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 94 | RegStorage r_src, OpSize size) OVERRIDE; |
Zheng Xu | 7c1c263 | 2014-06-17 18:17:31 +0800 | [diff] [blame] | 95 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; |
| 96 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
| 97 | int offset, int check_value, LIR* target) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 98 | |
| 99 | // Required for target - register utilities. |
Andreas Gampe | 4b537a8 | 2014-06-30 22:24:53 -0700 | [diff] [blame] | 100 | RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; |
| 101 | RegStorage TargetReg(SpecialTargetRegister symbolic_reg, bool is_wide) OVERRIDE { |
| 102 | RegStorage reg = TargetReg(symbolic_reg); |
| 103 | if (is_wide) { |
| 104 | return (reg.Is64Bit()) ? reg : As64BitReg(reg); |
| 105 | } else { |
| 106 | return (reg.Is32Bit()) ? reg : As32BitReg(reg); |
| 107 | } |
| 108 | } |
| 109 | RegStorage TargetRefReg(SpecialTargetRegister symbolic_reg) OVERRIDE { |
| 110 | RegStorage reg = TargetReg(symbolic_reg); |
| 111 | return (reg.Is64Bit() ? reg : As64BitReg(reg)); |
| 112 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 113 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
| 114 | RegLocation GetReturnAlt(); |
| 115 | RegLocation GetReturnWideAlt(); |
| 116 | RegLocation LocCReturn(); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 117 | RegLocation LocCReturnRef(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 118 | RegLocation LocCReturnDouble(); |
| 119 | RegLocation LocCReturnFloat(); |
| 120 | RegLocation LocCReturnWide(); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 121 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 122 | void AdjustSpillMask(); |
| 123 | void ClobberCallerSave(); |
| 124 | void FreeCallTemps(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 125 | void LockCallTemps(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 126 | void CompilerInitializeRegAlloc(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 127 | |
| 128 | // Required for target - miscellaneous. |
| 129 | void AssembleLIR(); |
| 130 | uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); |
| 131 | int AssignInsnOffsets(); |
| 132 | void AssignOffsets(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 133 | uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 134 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 135 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 136 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 137 | const char* GetTargetInstFmt(int opcode); |
| 138 | const char* GetTargetInstName(int opcode); |
| 139 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 140 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 141 | uint64_t GetTargetInstFlags(int opcode); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 142 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 143 | bool IsUnconditionalBranch(LIR* lir); |
| 144 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 145 | // Check support for volatile load/store of a given size. |
| 146 | bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; |
| 147 | // Get the register class for load/store of a field. |
| 148 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
| 149 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 150 | // Required for target - Dalvik-level generators. |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 151 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 152 | RegLocation lr_shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 153 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 154 | RegLocation rl_src1, RegLocation rl_src2); |
| 155 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
| 156 | RegLocation rl_index, RegLocation rl_dest, int scale); |
| 157 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 158 | RegLocation rl_src, int scale, bool card_mark); |
| 159 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 160 | RegLocation rl_src1, RegLocation rl_shift); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 161 | void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 162 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 163 | RegLocation rl_src2); |
| 164 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 165 | RegLocation rl_src2); |
| 166 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 167 | RegLocation rl_src2); |
| 168 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 169 | RegLocation rl_src2); |
| 170 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 171 | RegLocation rl_src2); |
| 172 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 173 | RegLocation rl_src2); |
| 174 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
| 175 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
| 176 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 177 | bool GenInlinedSqrt(CallInfo* info); |
| 178 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 179 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
Serban Constantinescu | 169489b | 2014-06-11 16:43:35 +0100 | [diff] [blame] | 180 | bool GenInlinedAbsLong(CallInfo* info); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 181 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); |
| 182 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 183 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 184 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 185 | RegLocation rl_src2); |
| 186 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 187 | RegLocation rl_src2); |
| 188 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 189 | RegLocation rl_src2); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 190 | void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 191 | RegLocation rl_src2, bool is_div); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 192 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 193 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
| 194 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| 195 | void GenDivZeroCheckWide(RegStorage reg); |
| 196 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 197 | void GenExitSequence(); |
| 198 | void GenSpecialExitSequence(); |
| 199 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); |
| 200 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 201 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 202 | void GenSelect(BasicBlock* bb, MIR* mir); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 203 | bool GenMemBarrier(MemBarrierKind barrier_kind); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 204 | void GenMonitorEnter(int opt_flags, RegLocation rl_src); |
| 205 | void GenMonitorExit(int opt_flags, RegLocation rl_src); |
| 206 | void GenMoveException(RegLocation rl_dest); |
| 207 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 208 | int first_bit, int second_bit); |
| 209 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 210 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
| 211 | void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 212 | void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 213 | |
| 214 | uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2); |
| 215 | void UnSpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); |
| 216 | void SpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 217 | void UnSpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); |
| 218 | void SpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 219 | |
| 220 | // Required for target - single operation generators. |
| 221 | LIR* OpUnconditionalBranch(LIR* target); |
| 222 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 223 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
| 224 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
| 225 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 226 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 227 | LIR* OpIT(ConditionCode cond, const char* guide); |
| 228 | void OpEndIT(LIR* it); |
| 229 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 230 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 231 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
| 232 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 233 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 234 | LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 235 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 236 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 237 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 238 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 239 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 240 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
Zheng Xu | e2eb29e | 2014-06-12 10:22:33 +0800 | [diff] [blame] | 241 | LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 242 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 243 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
| 244 | LIR* OpTestSuspend(LIR* target); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 245 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; |
| 246 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 247 | LIR* OpVldm(RegStorage r_base, int count); |
| 248 | LIR* OpVstm(RegStorage r_base, int count); |
| 249 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 250 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 251 | void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; |
| 252 | void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 253 | |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 254 | LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 255 | LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 256 | LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, |
| 257 | int shift); |
Andreas Gampe | 47b31aa | 2014-06-19 01:10:07 -0700 | [diff] [blame] | 258 | LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, |
| 259 | A64RegExtEncodings ext, uint8_t amount); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame] | 260 | LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); |
Stuart Monteith | f8ec48e | 2014-06-06 17:05:08 +0100 | [diff] [blame] | 261 | LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 262 | static const ArmEncodingMap EncodingMap[kA64Last]; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 263 | int EncodeShift(int code, int amount); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 264 | int EncodeExtend(int extend_type, int amount); |
| 265 | bool IsExtendEncoding(int encoded_value); |
| 266 | int EncodeLogicalImmediate(bool is_wide, uint64_t value); |
| 267 | uint64_t DecodeLogicalImmediate(bool is_wide, int value); |
| 268 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 269 | ArmConditionCode ArmConditionEncoding(ConditionCode code); |
| 270 | bool InexpensiveConstantInt(int32_t value); |
| 271 | bool InexpensiveConstantFloat(int32_t value); |
| 272 | bool InexpensiveConstantLong(int64_t value); |
| 273 | bool InexpensiveConstantDouble(int64_t value); |
| 274 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 275 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 276 | |
| 277 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 278 | NextCallInsn next_call_insn, |
| 279 | const MethodReference& target_method, |
| 280 | uint32_t vtable_idx, |
| 281 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 282 | bool skip_this); |
| 283 | |
| 284 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 285 | NextCallInsn next_call_insn, |
| 286 | const MethodReference& target_method, |
| 287 | uint32_t vtable_idx, |
| 288 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 289 | bool skip_this); |
| 290 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 291 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 292 | private: |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 293 | /** |
| 294 | * @brief Given register xNN (dNN), returns register wNN (sNN). |
| 295 | * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). |
| 296 | * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). |
| 297 | * @see As64BitReg |
| 298 | */ |
| 299 | RegStorage As32BitReg(RegStorage reg) { |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 300 | DCHECK(!reg.IsPair()); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 301 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 302 | if (kFailOnSizeError) { |
| 303 | LOG(FATAL) << "Expected 64b register"; |
| 304 | } else { |
| 305 | LOG(WARNING) << "Expected 64b register"; |
| 306 | return reg; |
| 307 | } |
| 308 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 309 | RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, |
| 310 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 311 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) |
| 312 | ->GetReg().GetReg(), |
| 313 | ret_val.GetReg()); |
| 314 | return ret_val; |
| 315 | } |
| 316 | |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 317 | RegStorage Check32BitReg(RegStorage reg) { |
| 318 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 319 | if (kFailOnSizeError) { |
| 320 | LOG(FATAL) << "Checked for 32b register"; |
| 321 | } else { |
| 322 | LOG(WARNING) << "Checked for 32b register"; |
| 323 | return As32BitReg(reg); |
| 324 | } |
| 325 | } |
| 326 | return reg; |
| 327 | } |
| 328 | |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 329 | /** |
| 330 | * @brief Given register wNN (sNN), returns register xNN (dNN). |
| 331 | * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). |
| 332 | * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). |
| 333 | * @see As32BitReg |
| 334 | */ |
| 335 | RegStorage As64BitReg(RegStorage reg) { |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 336 | DCHECK(!reg.IsPair()); |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 337 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { |
| 338 | if (kFailOnSizeError) { |
| 339 | LOG(FATAL) << "Expected 32b register"; |
| 340 | } else { |
| 341 | LOG(WARNING) << "Expected 32b register"; |
| 342 | return reg; |
| 343 | } |
| 344 | } |
Matteo Franchin | 5acc8b0 | 2014-06-05 15:10:35 +0100 | [diff] [blame] | 345 | RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, |
| 346 | reg.GetRawBits() & RegStorage::kRegTypeMask); |
| 347 | DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) |
| 348 | ->GetReg().GetReg(), |
| 349 | ret_val.GetReg()); |
| 350 | return ret_val; |
| 351 | } |
| 352 | |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 353 | RegStorage Check64BitReg(RegStorage reg) { |
| 354 | if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { |
| 355 | if (kFailOnSizeError) { |
| 356 | LOG(FATAL) << "Checked for 64b register"; |
| 357 | } else { |
| 358 | LOG(WARNING) << "Checked for 64b register"; |
| 359 | return As64BitReg(reg); |
| 360 | } |
| 361 | } |
| 362 | return reg; |
| 363 | } |
| 364 | |
Matteo Franchin | c41e6dc | 2014-06-13 19:16:28 +0100 | [diff] [blame] | 365 | LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); |
| 366 | LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 367 | void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 368 | void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); |
| 369 | void AssignDataOffsets(); |
| 370 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 371 | bool is_div, bool check_zero); |
| 372 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 373 | }; |
| 374 | |
| 375 | } // namespace art |
| 376 | |
| 377 | #endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ |