Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
Andreas Gampe | 0b9203e | 2015-01-22 20:39:27 -0800 | [diff] [blame] | 20 | |
| 21 | #include "base/logging.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 23 | #include "dex/reg_storage_eq.h" |
Mingyao Yang | 98d1cc8 | 2014-05-15 17:02:16 -0700 | [diff] [blame] | 24 | #include "mirror/art_method.h" |
Ian Rogers | 7e70b00 | 2014-10-08 11:47:24 -0700 | [diff] [blame] | 25 | #include "mirror/array-inl.h" |
Andreas Gampe | 7e49992 | 2015-01-06 08:28:12 -0800 | [diff] [blame] | 26 | #include "utils.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | #include "x86_lir.h" |
| 28 | |
| 29 | namespace art { |
| 30 | |
| 31 | /* |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 32 | * Compare two 64-bit values |
| 33 | * x = y return 0 |
| 34 | * x < y return -1 |
| 35 | * x > y return 1 |
| 36 | */ |
| 37 | void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 38 | RegLocation rl_src2) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 39 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 40 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 41 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 42 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 43 | RegStorage temp_reg = AllocTemp(); |
Serguei Katkov | 1c55703 | 2014-06-23 13:23:38 +0700 | [diff] [blame] | 44 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 45 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 |
| 46 | NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 |
| 47 | NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); |
| 48 | NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
Serguei Katkov | 0498223 | 2014-06-20 18:17:16 +0700 | [diff] [blame] | 49 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 50 | StoreValue(rl_dest, rl_result); |
| 51 | FreeTemp(temp_reg); |
| 52 | return; |
| 53 | } |
| 54 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 55 | // Prepare for explicit register usage |
| 56 | ExplicitTempRegisterLock(this, 4, &rs_r0, &rs_r1, &rs_r2, &rs_r3); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 57 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 58 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 59 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 60 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 61 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 62 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 63 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 64 | NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 |
| 65 | NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 66 | OpReg(kOpNeg, rs_r2); // r2 = -r2 |
| 67 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 68 | NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 69 | NewLIR2(kX86Movzx8RR, r0, r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 70 | OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 71 | RegLocation rl_result = LocCReturn(); |
| 72 | StoreValue(rl_dest, rl_result); |
| 73 | } |
| 74 | |
| 75 | X86ConditionCode X86ConditionEncoding(ConditionCode cond) { |
| 76 | switch (cond) { |
| 77 | case kCondEq: return kX86CondEq; |
| 78 | case kCondNe: return kX86CondNe; |
| 79 | case kCondCs: return kX86CondC; |
| 80 | case kCondCc: return kX86CondNc; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 81 | case kCondUlt: return kX86CondC; |
| 82 | case kCondUge: return kX86CondNc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 83 | case kCondMi: return kX86CondS; |
| 84 | case kCondPl: return kX86CondNs; |
| 85 | case kCondVs: return kX86CondO; |
| 86 | case kCondVc: return kX86CondNo; |
| 87 | case kCondHi: return kX86CondA; |
| 88 | case kCondLs: return kX86CondBe; |
| 89 | case kCondGe: return kX86CondGe; |
| 90 | case kCondLt: return kX86CondL; |
| 91 | case kCondGt: return kX86CondG; |
| 92 | case kCondLe: return kX86CondLe; |
| 93 | case kCondAl: |
| 94 | case kCondNv: LOG(FATAL) << "Should not reach here"; |
| 95 | } |
| 96 | return kX86CondO; |
| 97 | } |
| 98 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 99 | LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 100 | NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 101 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 102 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , |
| 103 | cc); |
| 104 | branch->target = target; |
| 105 | return branch; |
| 106 | } |
| 107 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 108 | LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 109 | int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { |
| 111 | // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 112 | NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 113 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 114 | if (reg.Is64Bit()) { |
| 115 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value); |
| 116 | } else { |
| 117 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); |
| 118 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 119 | } |
| 120 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 121 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); |
| 122 | branch->target = target; |
| 123 | return branch; |
| 124 | } |
| 125 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 126 | LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 127 | // If src or dest is a pair, we'll be using low reg. |
| 128 | if (r_dest.IsPair()) { |
| 129 | r_dest = r_dest.GetLow(); |
| 130 | } |
| 131 | if (r_src.IsPair()) { |
| 132 | r_src = r_src.GetLow(); |
| 133 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 134 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 135 | return OpFpRegCopy(r_dest, r_src); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 136 | LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 137 | r_dest.GetReg(), r_src.GetReg()); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 138 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | res->flags.is_nop = true; |
| 140 | } |
| 141 | return res; |
| 142 | } |
| 143 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 144 | void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 145 | if (r_dest != r_src) { |
| 146 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 147 | AppendLIR(res); |
| 148 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 149 | } |
| 150 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 151 | void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 152 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 153 | bool dest_fp = r_dest.IsFloat(); |
| 154 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 155 | if (dest_fp) { |
| 156 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 157 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 158 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 159 | // TODO: Prevent this from happening in the code. The result is often |
| 160 | // unused or could have been loaded more easily from memory. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 161 | if (!r_src.IsPair()) { |
| 162 | DCHECK(!r_dest.IsPair()); |
| 163 | NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); |
| 164 | } else { |
| 165 | NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); |
| 166 | RegStorage r_tmp = AllocTempDouble(); |
| 167 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); |
| 168 | NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); |
| 169 | FreeTemp(r_tmp); |
| 170 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 171 | } |
| 172 | } else { |
| 173 | if (src_fp) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 174 | if (!r_dest.IsPair()) { |
| 175 | DCHECK(!r_src.IsPair()); |
| 176 | NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 177 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 178 | NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); |
| 179 | RegStorage temp_reg = AllocTempDouble(); |
| 180 | NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); |
| 181 | NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); |
| 182 | NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); |
| 183 | } |
| 184 | } else { |
| 185 | DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); |
| 186 | if (!r_src.IsPair()) { |
| 187 | // Just copy the register directly. |
| 188 | OpRegCopy(r_dest, r_src); |
| 189 | } else { |
| 190 | // Handle overlap |
| 191 | if (r_src.GetHighReg() == r_dest.GetLowReg() && |
| 192 | r_src.GetLowReg() == r_dest.GetHighReg()) { |
| 193 | // Deal with cycles. |
| 194 | RegStorage temp_reg = AllocTemp(); |
| 195 | OpRegCopy(temp_reg, r_dest.GetHigh()); |
| 196 | OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); |
| 197 | OpRegCopy(r_dest.GetLow(), temp_reg); |
| 198 | FreeTemp(temp_reg); |
| 199 | } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 200 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 201 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 202 | } else { |
| 203 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 204 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 205 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 206 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 207 | } |
| 208 | } |
| 209 | } |
| 210 | } |
| 211 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 212 | void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 213 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 214 | RegisterClass dest_reg_class) { |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 215 | DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); |
| 216 | DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); |
| 217 | |
| 218 | // We really need this check for correctness, otherwise we will need to do more checks in |
| 219 | // non zero/one case |
| 220 | if (true_val == false_val) { |
| 221 | LoadConstantNoClobber(rs_dest, true_val); |
| 222 | return; |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 223 | } |
| 224 | |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 225 | const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); |
| 226 | |
| 227 | const bool zero_one_case = (true_val == 0 && false_val == 1) || (true_val == 1 && false_val == 0); |
| 228 | if (zero_one_case && IsByteRegister(rs_dest)) { |
| 229 | if (!dest_intersect) { |
| 230 | LoadConstantNoClobber(rs_dest, 0); |
| 231 | } |
| 232 | OpRegReg(kOpCmp, left_op, right_op); |
| 233 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
| 234 | NewLIR2(kX86Set8R, rs_dest.GetReg(), |
| 235 | X86ConditionEncoding(true_val == 1 ? code : FlipComparisonOrder(code))); |
| 236 | if (dest_intersect) { |
| 237 | NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 238 | } |
| 239 | } else { |
| 240 | // Be careful rs_dest can be changed only after cmp because it can be the same as one of ops |
| 241 | // and it cannot use xor because it makes cc flags to be dirty |
| 242 | RegStorage temp_reg = AllocTypedTemp(false, dest_reg_class, false); |
| 243 | if (temp_reg.Valid()) { |
| 244 | if (false_val == 0 && dest_intersect) { |
| 245 | code = FlipComparisonOrder(code); |
| 246 | std::swap(true_val, false_val); |
| 247 | } |
| 248 | if (!dest_intersect) { |
| 249 | LoadConstantNoClobber(rs_dest, false_val); |
| 250 | } |
| 251 | LoadConstantNoClobber(temp_reg, true_val); |
| 252 | OpRegReg(kOpCmp, left_op, right_op); |
| 253 | if (dest_intersect) { |
| 254 | LoadConstantNoClobber(rs_dest, false_val); |
| 255 | DCHECK(!last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
| 256 | } |
| 257 | OpCondRegReg(kOpCmov, code, rs_dest, temp_reg); |
| 258 | FreeTemp(temp_reg); |
| 259 | } else { |
| 260 | // slow path |
| 261 | LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr); |
| 262 | LoadConstantNoClobber(rs_dest, false_val); |
| 263 | LIR* that_is_it = NewLIR1(kX86Jmp8, 0); |
| 264 | LIR* true_case = NewLIR0(kPseudoTargetLabel); |
| 265 | cmp_branch->target = true_case; |
| 266 | LoadConstantNoClobber(rs_dest, true_val); |
| 267 | LIR* end = NewLIR0(kPseudoTargetLabel); |
| 268 | that_is_it->target = end; |
| 269 | } |
| 270 | } |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 271 | } |
| 272 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 273 | void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 274 | UNUSED(bb); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 275 | RegLocation rl_result; |
| 276 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 277 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 278 | // Avoid using float regs here. |
| 279 | RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; |
| 280 | RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 281 | ConditionCode ccode = mir->meta.ccode; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 282 | |
| 283 | // The kMirOpSelect has two variants, one for constants and one for moves. |
| 284 | const bool is_constant_case = (mir->ssa_rep->num_uses == 1); |
| 285 | |
| 286 | if (is_constant_case) { |
| 287 | int true_val = mir->dalvikInsn.vB; |
| 288 | int false_val = mir->dalvikInsn.vC; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 289 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 290 | // simplest strange case |
| 291 | if (true_val == false_val) { |
| 292 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
| 293 | LoadConstantNoClobber(rl_result.reg, true_val); |
| 294 | } else { |
| 295 | // TODO: use GenSelectConst32 and handle additional opcode patterns such as |
| 296 | // "cmp; setcc; movzx" or "cmp; sbb r0,r0; and r0,$mask; add r0,$literal". |
| 297 | rl_src = LoadValue(rl_src, src_reg_class); |
| 298 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
| 299 | /* |
| 300 | * For ccode == kCondEq: |
| 301 | * |
| 302 | * 1) When the true case is zero and result_reg is not same as src_reg: |
| 303 | * xor result_reg, result_reg |
| 304 | * cmp $0, src_reg |
| 305 | * mov t1, $false_case |
| 306 | * cmovnz result_reg, t1 |
| 307 | * 2) When the false case is zero and result_reg is not same as src_reg: |
| 308 | * xor result_reg, result_reg |
| 309 | * cmp $0, src_reg |
| 310 | * mov t1, $true_case |
| 311 | * cmovz result_reg, t1 |
| 312 | * 3) All other cases (we do compare first to set eflags): |
| 313 | * cmp $0, src_reg |
| 314 | * mov result_reg, $false_case |
| 315 | * mov t1, $true_case |
| 316 | * cmovz result_reg, t1 |
| 317 | */ |
| 318 | // FIXME: depending on how you use registers you could get a false != mismatch when dealing |
| 319 | // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). |
| 320 | const bool result_reg_same_as_src = |
| 321 | (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum()); |
| 322 | const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); |
| 323 | const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); |
| 324 | const bool catch_all_case = !(true_zero_case || false_zero_case); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 325 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 326 | if (true_zero_case || false_zero_case) { |
| 327 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
| 328 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 329 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 330 | if (true_zero_case || false_zero_case || catch_all_case) { |
| 331 | OpRegImm(kOpCmp, rl_src.reg, 0); |
| 332 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 333 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 334 | if (catch_all_case) { |
| 335 | OpRegImm(kOpMov, rl_result.reg, false_val); |
| 336 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 337 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 338 | if (true_zero_case || false_zero_case || catch_all_case) { |
| 339 | ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; |
| 340 | int immediateForTemp = true_zero_case ? false_val : true_val; |
| 341 | RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); |
| 342 | OpRegImm(kOpMov, temp1_reg, immediateForTemp); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 343 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 344 | OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 345 | |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 346 | FreeTemp(temp1_reg); |
| 347 | } |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 348 | } |
| 349 | } else { |
Jean Christophe Beyler | 3f51e7d | 2014-09-04 08:34:28 -0700 | [diff] [blame] | 350 | rl_src = LoadValue(rl_src, src_reg_class); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 351 | RegLocation rl_true = mir_graph_->GetSrc(mir, 1); |
| 352 | RegLocation rl_false = mir_graph_->GetSrc(mir, 2); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 353 | rl_true = LoadValue(rl_true, result_reg_class); |
| 354 | rl_false = LoadValue(rl_false, result_reg_class); |
| 355 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 356 | |
| 357 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 358 | * For ccode == kCondEq: |
| 359 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 360 | * 1) When true case is already in place: |
| 361 | * cmp $0, src_reg |
| 362 | * cmovnz result_reg, false_reg |
| 363 | * 2) When false case is already in place: |
| 364 | * cmp $0, src_reg |
| 365 | * cmovz result_reg, true_reg |
| 366 | * 3) When neither cases are in place: |
| 367 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 368 | * mov result_reg, false_reg |
| 369 | * cmovz result_reg, true_reg |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 370 | */ |
| 371 | |
| 372 | // kMirOpSelect is generated just for conditional cases when comparison is done with zero. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 373 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 374 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 375 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 376 | OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 377 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 378 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 379 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 380 | OpRegCopy(rl_result.reg, rl_false.reg); |
| 381 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 382 | } |
| 383 | } |
| 384 | |
| 385 | StoreValue(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 389 | LIR* taken = &block_label_list_[bb->taken]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 390 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 391 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 392 | ConditionCode ccode = mir->meta.ccode; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 393 | |
| 394 | if (rl_src1.is_const) { |
| 395 | std::swap(rl_src1, rl_src2); |
| 396 | ccode = FlipComparisonOrder(ccode); |
| 397 | } |
| 398 | if (rl_src2.is_const) { |
| 399 | // Do special compare/branch against simple const operand |
| 400 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 401 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 402 | return; |
| 403 | } |
| 404 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 405 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 406 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 407 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 408 | |
| 409 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 410 | OpCondBranch(ccode, taken); |
| 411 | return; |
| 412 | } |
| 413 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 414 | // Prepare for explicit register usage |
| 415 | ExplicitTempRegisterLock(this, 4, &rs_r0, &rs_r1, &rs_r2, &rs_r3); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 416 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 417 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 418 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 419 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 420 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 421 | // Swap operands and condition code to prevent use of zero flag. |
| 422 | if (ccode == kCondLe || ccode == kCondGt) { |
| 423 | // Compute (r3:r2) = (r3:r2) - (r1:r0) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 424 | OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 |
| 425 | OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 426 | } else { |
| 427 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 428 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 429 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 430 | } |
| 431 | switch (ccode) { |
| 432 | case kCondEq: |
| 433 | case kCondNe: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 434 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 435 | break; |
| 436 | case kCondLe: |
| 437 | ccode = kCondGe; |
| 438 | break; |
| 439 | case kCondGt: |
| 440 | ccode = kCondLt; |
| 441 | break; |
| 442 | case kCondLt: |
| 443 | case kCondGe: |
| 444 | break; |
| 445 | default: |
| 446 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 447 | } |
| 448 | OpCondBranch(ccode, taken); |
| 449 | } |
| 450 | |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 451 | void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 452 | int64_t val, ConditionCode ccode) { |
| 453 | int32_t val_lo = Low32Bits(val); |
| 454 | int32_t val_hi = High32Bits(val); |
| 455 | LIR* taken = &block_label_list_[bb->taken]; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 456 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 457 | bool is_equality_test = ccode == kCondEq || ccode == kCondNe; |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 458 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 459 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 460 | if (is_equality_test && val == 0) { |
| 461 | // We can simplify of comparing for ==, != to 0. |
| 462 | NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg()); |
| 463 | } else if (is_equality_test && val_hi == 0 && val_lo > 0) { |
| 464 | OpRegImm(kOpCmp, rl_src1.reg, val_lo); |
| 465 | } else { |
| 466 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 467 | LoadConstantWide(tmp, val); |
| 468 | OpRegReg(kOpCmp, rl_src1.reg, tmp); |
| 469 | FreeTemp(tmp); |
| 470 | } |
| 471 | OpCondBranch(ccode, taken); |
| 472 | return; |
| 473 | } |
| 474 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 475 | if (is_equality_test && val != 0) { |
| 476 | rl_src1 = ForceTempWide(rl_src1); |
| 477 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 478 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 479 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 480 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 481 | if (is_equality_test) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 482 | // We can simplify of comparing for ==, != to 0. |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 483 | if (val == 0) { |
| 484 | if (IsTemp(low_reg)) { |
| 485 | OpRegReg(kOpOr, low_reg, high_reg); |
| 486 | // We have now changed it; ignore the old values. |
| 487 | Clobber(rl_src1.reg); |
| 488 | } else { |
| 489 | RegStorage t_reg = AllocTemp(); |
| 490 | OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); |
| 491 | FreeTemp(t_reg); |
| 492 | } |
| 493 | OpCondBranch(ccode, taken); |
| 494 | return; |
| 495 | } |
| 496 | |
| 497 | // Need to compute the actual value for ==, !=. |
| 498 | OpRegImm(kOpSub, low_reg, val_lo); |
| 499 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 500 | OpRegReg(kOpOr, high_reg, low_reg); |
| 501 | Clobber(rl_src1.reg); |
| 502 | } else if (ccode == kCondLe || ccode == kCondGt) { |
| 503 | // Swap operands and condition code to prevent use of zero flag. |
| 504 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 505 | LoadConstantWide(tmp, val); |
| 506 | OpRegReg(kOpSub, tmp.GetLow(), low_reg); |
| 507 | OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); |
| 508 | ccode = (ccode == kCondLe) ? kCondGe : kCondLt; |
| 509 | FreeTemp(tmp); |
| 510 | } else { |
| 511 | // We can use a compare for the low word to set CF. |
| 512 | OpRegImm(kOpCmp, low_reg, val_lo); |
| 513 | if (IsTemp(high_reg)) { |
| 514 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 515 | // We have now changed it; ignore the old values. |
| 516 | Clobber(rl_src1.reg); |
| 517 | } else { |
| 518 | // mov temp_reg, high_reg; sbb temp_reg, high_constant |
| 519 | RegStorage t_reg = AllocTemp(); |
| 520 | OpRegCopy(t_reg, high_reg); |
| 521 | NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); |
| 522 | FreeTemp(t_reg); |
| 523 | } |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 524 | } |
| 525 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 526 | OpCondBranch(ccode, taken); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 527 | } |
| 528 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 529 | void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 530 | // It does not make sense to calculate magic and shift for zero divisor. |
| 531 | DCHECK_NE(divisor, 0); |
| 532 | |
| 533 | /* According to H.S.Warren's Hacker's Delight Chapter 10 and |
| 534 | * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 535 | * The magic number M and shift S can be calculated in the following way: |
| 536 | * Let nc be the most positive value of numerator(n) such that nc = kd - 1, |
| 537 | * where divisor(d) >=2. |
| 538 | * Let nc be the most negative value of numerator(n) such that nc = kd + 1, |
| 539 | * where divisor(d) <= -2. |
| 540 | * Thus nc can be calculated like: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 541 | * nc = exp + exp % d - 1, where d >= 2 and exp = 2^31 for int or 2^63 for long |
| 542 | * nc = -exp + (exp + 1) % d, where d >= 2 and exp = 2^31 for int or 2^63 for long |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 543 | * |
| 544 | * So the shift p is the smallest p satisfying |
| 545 | * 2^p > nc * (d - 2^p % d), where d >= 2 |
| 546 | * 2^p > nc * (d + 2^p % d), where d <= -2. |
| 547 | * |
| 548 | * the magic number M is calcuated by |
| 549 | * M = (2^p + d - 2^p % d) / d, where d >= 2 |
| 550 | * M = (2^p - d - 2^p % d) / d, where d <= -2. |
| 551 | * |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 552 | * Notice that p is always bigger than or equal to 32/64, so we just return 32-p/64-p as |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 553 | * the shift number S. |
| 554 | */ |
| 555 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 556 | int64_t p = (is_long) ? 63 : 31; |
| 557 | const uint64_t exp = (is_long) ? 0x8000000000000000ULL : 0x80000000U; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 558 | |
| 559 | // Initialize the computations. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 560 | uint64_t abs_d = (divisor >= 0) ? divisor : -divisor; |
| 561 | uint64_t tmp = exp + ((is_long) ? static_cast<uint64_t>(divisor) >> 63 : |
| 562 | static_cast<uint32_t>(divisor) >> 31); |
| 563 | uint64_t abs_nc = tmp - 1 - tmp % abs_d; |
| 564 | uint64_t quotient1 = exp / abs_nc; |
| 565 | uint64_t remainder1 = exp % abs_nc; |
| 566 | uint64_t quotient2 = exp / abs_d; |
| 567 | uint64_t remainder2 = exp % abs_d; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 568 | |
| 569 | /* |
| 570 | * To avoid handling both positive and negative divisor, Hacker's Delight |
| 571 | * introduces a method to handle these 2 cases together to avoid duplication. |
| 572 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 573 | uint64_t delta; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 574 | do { |
| 575 | p++; |
| 576 | quotient1 = 2 * quotient1; |
| 577 | remainder1 = 2 * remainder1; |
| 578 | if (remainder1 >= abs_nc) { |
| 579 | quotient1++; |
| 580 | remainder1 = remainder1 - abs_nc; |
| 581 | } |
| 582 | quotient2 = 2 * quotient2; |
| 583 | remainder2 = 2 * remainder2; |
| 584 | if (remainder2 >= abs_d) { |
| 585 | quotient2++; |
| 586 | remainder2 = remainder2 - abs_d; |
| 587 | } |
| 588 | delta = abs_d - remainder2; |
| 589 | } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); |
| 590 | |
| 591 | magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 592 | |
| 593 | if (!is_long) { |
| 594 | magic = static_cast<int>(magic); |
| 595 | } |
| 596 | |
| 597 | shift = (is_long) ? p - 64 : p - 32; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 598 | } |
| 599 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 600 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 601 | UNUSED(rl_dest, reg_lo, lit, is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 602 | LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 603 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 604 | } |
| 605 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 606 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, |
| 607 | int imm, bool is_div) { |
| 608 | // Use a multiply (and fixup) to perform an int div/rem by a constant. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 609 | RegLocation rl_result; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 610 | |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 611 | if (imm == 1) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 612 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 613 | if (is_div) { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 614 | // x / 1 == x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 615 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 616 | } else { |
| 617 | // x % 1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 618 | LoadConstantNoClobber(rl_result.reg, 0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 619 | } |
| 620 | } else if (imm == -1) { // handle 0x80000000 / -1 special case. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 621 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 622 | if (is_div) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 623 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 624 | |
| 625 | // Check if numerator is 0 |
| 626 | OpRegImm(kOpCmp, rl_result.reg, 0); |
| 627 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 628 | |
| 629 | // handle 0x80000000 / -1 |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 630 | OpRegImm(kOpCmp, rl_result.reg, 0x80000000); |
| 631 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 632 | |
| 633 | // for x != MIN_INT, x / -1 == -x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 634 | NewLIR1(kX86Neg32R, rl_result.reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 635 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 636 | // EAX already contains the right value (0x80000000), |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 637 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 638 | branch->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 639 | } else { |
| 640 | // x % -1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 641 | LoadConstantNoClobber(rl_result.reg, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 642 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 643 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 644 | // Division using shifting. |
| 645 | rl_src = LoadValue(rl_src, kCoreReg); |
| 646 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 647 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 648 | RegStorage rs_temp = AllocTypedTemp(false, kCoreReg); |
| 649 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 650 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 651 | |
| 652 | // Check if numerator is 0 |
| 653 | OpRegImm(kOpCmp, rl_src.reg, 0); |
| 654 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 655 | LoadConstantNoClobber(rl_result.reg, 0); |
| 656 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 657 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 658 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 659 | NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); |
| 660 | NewLIR2(kX86Test32RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 661 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
Andreas Gampe | 7e49992 | 2015-01-06 08:28:12 -0800 | [diff] [blame] | 662 | int shift_amount = CTZ(imm); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 663 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 664 | if (imm < 0) { |
| 665 | OpReg(kOpNeg, rl_result.reg); |
| 666 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 667 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 668 | } else { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 669 | CHECK(imm <= -2 || imm >= 2); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 670 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 671 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 672 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 673 | int64_t magic; |
| 674 | int shift; |
| 675 | CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 676 | |
| 677 | /* |
| 678 | * For imm >= 2, |
| 679 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 680 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 681 | * For imm <= -2, |
| 682 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 683 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 684 | * We implement this algorithm in the following way: |
| 685 | * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX |
| 686 | * 2. if imm > 0 and magic < 0, add numerator to EDX |
| 687 | * if imm < 0 and magic > 0, sub numerator from EDX |
| 688 | * 3. if S !=0, SAR S bits for EDX |
| 689 | * 4. add 1 to EDX if EDX < 0 |
| 690 | * 5. Thus, EDX is the quotient |
| 691 | */ |
| 692 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 693 | FlushReg(rs_r0); |
| 694 | Clobber(rs_r0); |
| 695 | LockTemp(rs_r0); |
| 696 | FlushReg(rs_r2); |
| 697 | Clobber(rs_r2); |
| 698 | LockTemp(rs_r2); |
| 699 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 700 | // Assume that the result will be in EDX for divide, and EAX for remainder. |
| 701 | rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, is_div ? rs_r2 : rs_r0, |
| 702 | INVALID_SREG, INVALID_SREG}; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 703 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 704 | // We need the value at least twice. Load into a temp. |
| 705 | rl_src = LoadValue(rl_src, kCoreReg); |
| 706 | RegStorage numerator_reg = rl_src.reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 707 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 708 | // Check if numerator is 0. |
| 709 | OpRegImm(kOpCmp, numerator_reg, 0); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 710 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 711 | // Return result 0 if numerator was 0. |
| 712 | LoadConstantNoClobber(rl_result.reg, 0); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 713 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 714 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 715 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 716 | // EAX = magic. |
| 717 | LoadConstant(rs_r0, magic); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 718 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 719 | // EDX:EAX = magic * numerator. |
| 720 | NewLIR1(kX86Imul32DaR, numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 721 | |
| 722 | if (imm > 0 && magic < 0) { |
| 723 | // Add numerator to EDX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 724 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 725 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 726 | } else if (imm < 0 && magic > 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 727 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 728 | NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | // Do we need the shift? |
| 732 | if (shift != 0) { |
| 733 | // Shift EDX by 'shift' bits. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 734 | NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | // Add 1 to EDX if EDX < 0. |
| 738 | |
| 739 | // Move EDX to EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 740 | OpRegCopy(rs_r0, rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 741 | |
| 742 | // Move sign bit to bit 0, zeroing the rest. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 743 | NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 744 | |
| 745 | // EDX = EDX + EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 746 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 747 | |
| 748 | // Quotient is in EDX. |
| 749 | if (!is_div) { |
| 750 | // We need to compute the remainder. |
| 751 | // Remainder is divisor - (quotient * imm). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 752 | DCHECK(numerator_reg.Valid()); |
| 753 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 754 | |
| 755 | // EAX = numerator * imm. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 756 | OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 757 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 758 | // EAX -= EDX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 759 | NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 760 | |
| 761 | // For this case, return the result in EAX. |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 762 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 763 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 764 | } |
| 765 | |
| 766 | return rl_result; |
| 767 | } |
| 768 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 769 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, |
| 770 | bool is_div) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 771 | UNUSED(rl_dest, reg_lo, reg_hi, is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 772 | LOG(FATAL) << "Unexpected use of GenDivRem for x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 773 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 774 | } |
| 775 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 776 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 777 | RegLocation rl_src2, bool is_div, int flags) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 778 | UNUSED(rl_dest); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 779 | // We have to use fixed registers, so flush all the temps. |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 780 | |
| 781 | // Prepare for explicit register usage. |
| 782 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 783 | |
| 784 | // Load LHS into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 785 | LoadValueDirectFixed(rl_src1, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 786 | |
| 787 | // Load RHS into EBX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 788 | LoadValueDirectFixed(rl_src2, rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 789 | |
| 790 | // Copy LHS sign bit into EDX. |
| 791 | NewLIR0(kx86Cdq32Da); |
| 792 | |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 793 | if ((flags & MIR_IGNORE_DIV_ZERO_CHECK) == 0) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 794 | // Handle division by zero case. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 795 | GenDivZeroCheck(rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 796 | } |
| 797 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 798 | // Check if numerator is 0 |
| 799 | OpRegImm(kOpCmp, rs_r0, 0); |
| 800 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 801 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 802 | // Have to catch 0x80000000/-1 case, or we will get an exception! |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 803 | OpRegImm(kOpCmp, rs_r1, -1); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 804 | LIR* minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 805 | |
| 806 | // RHS is -1. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 807 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 808 | LIR* minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 809 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame] | 810 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 811 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 812 | // In 0x80000000/-1 case. |
| 813 | if (!is_div) { |
| 814 | // For DIV, EAX is already right. For REM, we need EDX 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 815 | LoadConstantNoClobber(rs_r2, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 816 | } |
| 817 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 818 | |
| 819 | // Expected case. |
| 820 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 821 | minint_branch->target = minus_one_branch->target; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 822 | NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 823 | done->target = NewLIR0(kPseudoTargetLabel); |
| 824 | |
| 825 | // Result is in EAX for div and EDX for rem. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 826 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 827 | if (!is_div) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 828 | rl_result.reg.SetReg(r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 829 | } |
| 830 | return rl_result; |
| 831 | } |
| 832 | |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 833 | bool X86Mir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 834 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 835 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 836 | if (is_long && !cu_->target64) { |
| 837 | /* |
| 838 | * We want to implement the following algorithm |
| 839 | * mov eax, low part of arg1 |
| 840 | * mov edx, high part of arg1 |
| 841 | * mov ebx, low part of arg2 |
| 842 | * mov ecx, high part of arg2 |
| 843 | * mov edi, eax |
| 844 | * sub edi, ebx |
| 845 | * mov edi, edx |
| 846 | * sbb edi, ecx |
| 847 | * is_min ? "cmovgel eax, ebx" : "cmovll eax, ebx" |
| 848 | * is_min ? "cmovgel edx, ecx" : "cmovll edx, ecx" |
| 849 | * |
| 850 | * The algorithm above needs 5 registers: a pair for the first operand |
| 851 | * (which later will be used as result), a pair for the second operand |
| 852 | * and a temp register (e.g. 'edi') for intermediate calculations. |
| 853 | * Ideally we have 6 GP caller-save registers in 32-bit mode. They are: |
| 854 | * 'eax', 'ebx', 'ecx', 'edx', 'esi' and 'edi'. So there should be |
| 855 | * always enough registers to operate on. Practically, there is a pair |
| 856 | * of registers 'edi' and 'esi' which holds promoted values and |
| 857 | * sometimes should be treated as 'callee save'. If one of the operands |
| 858 | * is in the promoted registers then we have enough register to |
| 859 | * operate on. Otherwise there is lack of resources and we have to |
| 860 | * save 'edi' before calculations and restore after. |
| 861 | */ |
| 862 | |
| 863 | RegLocation rl_src1 = info->args[0]; |
| 864 | RegLocation rl_src2 = info->args[2]; |
| 865 | RegLocation rl_dest = InlineTargetWide(info); |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 866 | |
Mark Mendell | a65c1db | 2014-10-21 17:44:32 -0400 | [diff] [blame] | 867 | if (rl_dest.s_reg_low == INVALID_SREG) { |
| 868 | // Result is unused, the code is dead. Inlining successful, no code generated. |
| 869 | return true; |
| 870 | } |
| 871 | |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 872 | if (PartiallyIntersects(rl_src1, rl_dest) && |
| 873 | PartiallyIntersects(rl_src2, rl_dest)) { |
| 874 | // A special case which we don't want to handle. |
| 875 | // This is when src1 is mapped on v0 and v1, |
| 876 | // src2 is mapped on v2, v3, |
| 877 | // result is mapped on v1, v2 |
| 878 | return false; |
| 879 | } |
| 880 | |
| 881 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 882 | /* |
| 883 | * If the result register is the same as the second element, then we |
| 884 | * need to be careful. The reason is that the first copy will |
| 885 | * inadvertently clobber the second element with the first one thus |
| 886 | * yielding the wrong result. Thus we do a swap in that case. |
| 887 | */ |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 888 | if (Intersects(rl_src2, rl_dest)) { |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 889 | std::swap(rl_src1, rl_src2); |
| 890 | } |
| 891 | |
| 892 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 893 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 894 | |
| 895 | // Pick the first integer as min/max. |
| 896 | OpRegCopyWide(rl_result.reg, rl_src1.reg); |
| 897 | |
| 898 | /* |
| 899 | * If the integers are both in the same register, then there is |
| 900 | * nothing else to do because they are equal and we have already |
| 901 | * moved one into the result. |
| 902 | */ |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 903 | if (mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 904 | mir_graph_->SRegToVReg(rl_src2.s_reg_low)) { |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 905 | StoreValueWide(rl_dest, rl_result); |
| 906 | return true; |
| 907 | } |
| 908 | |
| 909 | // Free registers to make some room for the second operand. |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 910 | // But don't try to free part of a source which intersects |
| 911 | // part of result or promoted registers. |
| 912 | |
| 913 | if (IsTemp(rl_src1.reg.GetLow()) && |
| 914 | (rl_src1.reg.GetLowReg() != rl_result.reg.GetHighReg()) && |
| 915 | (rl_src1.reg.GetLowReg() != rl_result.reg.GetLowReg())) { |
| 916 | // Is low part temporary and doesn't intersect any parts of result? |
| 917 | FreeTemp(rl_src1.reg.GetLow()); |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 918 | } |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 919 | |
| 920 | if (IsTemp(rl_src1.reg.GetHigh()) && |
| 921 | (rl_src1.reg.GetHighReg() != rl_result.reg.GetLowReg()) && |
| 922 | (rl_src1.reg.GetHighReg() != rl_result.reg.GetHighReg())) { |
| 923 | // Is high part temporary and doesn't intersect any parts of result? |
| 924 | FreeTemp(rl_src1.reg.GetHigh()); |
| 925 | } |
| 926 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 927 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 928 | |
| 929 | // Do we have a free register for intermediate calculations? |
| 930 | RegStorage tmp = AllocTemp(false); |
| 931 | if (tmp == RegStorage::InvalidReg()) { |
| 932 | /* |
| 933 | * No, will use 'edi'. |
| 934 | * |
| 935 | * As mentioned above we have 4 temporary and 2 promotable |
| 936 | * caller-save registers. Therefore, we assume that a free |
| 937 | * register can be allocated only if 'esi' and 'edi' are |
| 938 | * already used as operands. If number of promotable registers |
| 939 | * increases from 2 to 4 then our assumption fails and operand |
| 940 | * data is corrupted. |
| 941 | * Let's DCHECK it. |
| 942 | */ |
| 943 | DCHECK(IsTemp(rl_src2.reg.GetLow()) && |
| 944 | IsTemp(rl_src2.reg.GetHigh()) && |
| 945 | IsTemp(rl_result.reg.GetLow()) && |
| 946 | IsTemp(rl_result.reg.GetHigh())); |
| 947 | tmp = rs_rDI; |
| 948 | NewLIR1(kX86Push32R, tmp.GetReg()); |
| 949 | } |
| 950 | |
| 951 | // Now we are ready to do calculations. |
| 952 | OpRegReg(kOpMov, tmp, rl_result.reg.GetLow()); |
| 953 | OpRegReg(kOpSub, tmp, rl_src2.reg.GetLow()); |
| 954 | OpRegReg(kOpMov, tmp, rl_result.reg.GetHigh()); |
| 955 | OpRegReg(kOpSbc, tmp, rl_src2.reg.GetHigh()); |
| 956 | |
| 957 | // Let's put pop 'edi' here to break a bit the dependency chain. |
| 958 | if (tmp == rs_rDI) { |
| 959 | NewLIR1(kX86Pop32R, tmp.GetReg()); |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 960 | } else { |
| 961 | FreeTemp(tmp); |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | // Conditionally move the other integer into the destination register. |
| 965 | ConditionCode cc = is_min ? kCondGe : kCondLt; |
| 966 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); |
| 967 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); |
nikolay serdjuk | 5569328 | 2015-01-20 17:03:02 +0600 | [diff] [blame] | 968 | FreeTemp(rl_src2.reg); |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 969 | StoreValueWide(rl_dest, rl_result); |
| 970 | return true; |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 971 | } |
| 972 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 973 | // Get the two arguments to the invoke and place them in GP registers. |
Chao-ying Fu | ff87d7b | 2015-01-19 15:51:57 -0800 | [diff] [blame] | 974 | RegLocation rl_dest = (is_long) ? InlineTargetWide(info) : InlineTarget(info); |
| 975 | if (rl_dest.s_reg_low == INVALID_SREG) { |
| 976 | // Result is unused, the code is dead. Inlining successful, no code generated. |
| 977 | return true; |
| 978 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 979 | RegLocation rl_src1 = info->args[0]; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 980 | RegLocation rl_src2 = (is_long) ? info->args[2] : info->args[1]; |
| 981 | rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg); |
| 982 | rl_src2 = (is_long) ? LoadValueWide(rl_src2, kCoreReg) : LoadValue(rl_src2, kCoreReg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 983 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 984 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 985 | |
| 986 | /* |
| 987 | * If the result register is the same as the second element, then we need to be careful. |
| 988 | * The reason is that the first copy will inadvertently clobber the second element with |
| 989 | * the first one thus yielding the wrong result. Thus we do a swap in that case. |
| 990 | */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 991 | if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 992 | std::swap(rl_src1, rl_src2); |
| 993 | } |
| 994 | |
| 995 | // Pick the first integer as min/max. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 996 | OpRegCopy(rl_result.reg, rl_src1.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 997 | |
| 998 | // If the integers are both in the same register, then there is nothing else to do |
| 999 | // because they are equal and we have already moved one into the result. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1000 | if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1001 | // It is possible we didn't pick correctly so do the actual comparison now. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1002 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1003 | |
| 1004 | // Conditionally move the other integer into the destination register. |
| 1005 | ConditionCode condition_code = is_min ? kCondGt : kCondLt; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1006 | OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 1007 | } |
| 1008 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1009 | if (is_long) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1010 | StoreValueWide(rl_dest, rl_result); |
| 1011 | } else { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1012 | StoreValue(rl_dest, rl_result); |
| 1013 | } |
| 1014 | return true; |
| 1015 | } |
| 1016 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1017 | bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
Chao-ying Fu | ff87d7b | 2015-01-19 15:51:57 -0800 | [diff] [blame] | 1018 | RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); |
| 1019 | if (rl_dest.s_reg_low == INVALID_SREG) { |
| 1020 | // Result is unused, the code is dead. Inlining successful, no code generated. |
| 1021 | return true; |
| 1022 | } |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1023 | RegLocation rl_src_address = info->args[0]; // long address |
| 1024 | RegLocation rl_address; |
| 1025 | if (!cu_->target64) { |
| 1026 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 1027 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 1028 | } else { |
| 1029 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 1030 | } |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1031 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1032 | // Unaligned access is allowed on x86. |
| 1033 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
| 1034 | if (size == k64) { |
| 1035 | StoreValueWide(rl_dest, rl_result); |
| 1036 | } else { |
| 1037 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 1038 | StoreValue(rl_dest, rl_result); |
| 1039 | } |
| 1040 | return true; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1041 | } |
| 1042 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1043 | bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1044 | RegLocation rl_src_address = info->args[0]; // long address |
| 1045 | RegLocation rl_address; |
| 1046 | if (!cu_->target64) { |
| 1047 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 1048 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 1049 | } else { |
| 1050 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 1051 | } |
| 1052 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 1053 | RegLocation rl_value; |
| 1054 | if (size == k64) { |
| 1055 | // Unaligned access is allowed on x86. |
| 1056 | rl_value = LoadValueWide(rl_src_value, kCoreReg); |
| 1057 | } else { |
| 1058 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 1059 | // In 32-bit mode the only EAX..EDX registers can be used with Mov8MR. |
| 1060 | if (!cu_->target64 && size == kSignedByte) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1061 | rl_src_value = UpdateLocTyped(rl_src_value); |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1062 | if (rl_src_value.location == kLocPhysReg && !IsByteRegister(rl_src_value.reg)) { |
| 1063 | RegStorage temp = AllocateByteRegister(); |
| 1064 | OpRegCopy(temp, rl_src_value.reg); |
| 1065 | rl_value.reg = temp; |
| 1066 | } else { |
| 1067 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1068 | } |
| 1069 | } else { |
| 1070 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1071 | } |
| 1072 | } |
| 1073 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
| 1074 | return true; |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1075 | } |
| 1076 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1077 | void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { |
| 1078 | NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1079 | } |
| 1080 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1081 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1082 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 1083 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
| 1084 | } |
| 1085 | |
| 1086 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { |
| 1087 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 1088 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1089 | } |
| 1090 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1091 | static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { |
| 1092 | return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1093 | } |
| 1094 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 1095 | bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 1096 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1097 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 1098 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 1099 | RegLocation rl_src_offset = info->args[2]; // long low |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1100 | if (!cu_->target64) { |
| 1101 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
| 1102 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1103 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
| 1104 | // If is_long, high half is in info->args[5] |
| 1105 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 1106 | // If is_long, high half is in info->args[7] |
| 1107 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1108 | if (is_long && cu_->target64) { |
| 1109 | // RAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in RAX. |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1110 | FlushReg(rs_r0q); |
| 1111 | Clobber(rs_r0q); |
| 1112 | LockTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1113 | |
| 1114 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1115 | RegLocation rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1116 | RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1117 | LoadValueDirectWide(rl_src_expected, rs_r0q); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1118 | NewLIR5(kX86LockCmpxchg64AR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1119 | rl_new_value.reg.GetReg()); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1120 | |
| 1121 | // After a store we need to insert barrier in case of potential load. Since the |
| 1122 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1123 | GenMemBarrier(kAnyAny); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1124 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1125 | FreeTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1126 | } else if (is_long) { |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1127 | // TODO: avoid unnecessary loads of SI and DI when the values are in registers. |
| 1128 | // TODO: CFI support. |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1129 | FlushAllRegs(); |
| 1130 | LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1131 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 1132 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1133 | LoadValueDirectWideFixed(rl_src_expected, r_tmp1); |
| 1134 | LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1135 | // FIXME: needs 64-bit update. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1136 | const bool obj_in_di = IsInReg(this, rl_src_obj, rs_rDI); |
| 1137 | const bool obj_in_si = IsInReg(this, rl_src_obj, rs_rSI); |
| 1138 | DCHECK(!obj_in_si || !obj_in_di); |
| 1139 | const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); |
| 1140 | const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); |
| 1141 | DCHECK(!off_in_si || !off_in_di); |
| 1142 | // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg. |
| 1143 | RegStorage rs_obj = obj_in_di ? rs_rDI : obj_in_si ? rs_rSI : !off_in_di ? rs_rDI : rs_rSI; |
| 1144 | RegStorage rs_off = off_in_si ? rs_rSI : off_in_di ? rs_rDI : !obj_in_si ? rs_rSI : rs_rDI; |
| 1145 | bool push_di = (!obj_in_di && !off_in_di) && (rs_obj == rs_rDI || rs_off == rs_rDI); |
| 1146 | bool push_si = (!obj_in_si && !off_in_si) && (rs_obj == rs_rSI || rs_off == rs_rSI); |
| 1147 | if (push_di) { |
| 1148 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1149 | MarkTemp(rs_rDI); |
| 1150 | LockTemp(rs_rDI); |
| 1151 | } |
| 1152 | if (push_si) { |
| 1153 | NewLIR1(kX86Push32R, rs_rSI.GetReg()); |
| 1154 | MarkTemp(rs_rSI); |
| 1155 | LockTemp(rs_rSI); |
| 1156 | } |
| 1157 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1158 | const size_t push_offset = (push_si ? 4u : 0u) + (push_di ? 4u : 0u); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1159 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1160 | if (!obj_in_si && !obj_in_di) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1161 | LoadWordDisp(rs_rSP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1162 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1163 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1164 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1165 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1166 | } |
| 1167 | if (!off_in_si && !off_in_di) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1168 | LoadWordDisp(rs_rSP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1169 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1170 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1171 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1172 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1173 | } |
| 1174 | NewLIR4(kX86LockCmpxchg64A, rs_obj.GetReg(), rs_off.GetReg(), 0, 0); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1175 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1176 | // After a store we need to insert barrier to prevent reordering with either |
| 1177 | // earlier or later memory accesses. Since |
| 1178 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1179 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1180 | GenMemBarrier(kAnyAny); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1181 | |
| 1182 | if (push_si) { |
| 1183 | FreeTemp(rs_rSI); |
| 1184 | UnmarkTemp(rs_rSI); |
| 1185 | NewLIR1(kX86Pop32R, rs_rSI.GetReg()); |
| 1186 | } |
| 1187 | if (push_di) { |
| 1188 | FreeTemp(rs_rDI); |
| 1189 | UnmarkTemp(rs_rDI); |
| 1190 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
| 1191 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1192 | FreeCallTemps(); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1193 | } else { |
| 1194 | // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1195 | FlushReg(rs_r0); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1196 | Clobber(rs_r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1197 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1198 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1199 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
buzbee | 7c02e91 | 2014-10-03 13:14:17 -0700 | [diff] [blame] | 1200 | RegLocation rl_new_value = LoadValue(rl_src_new_value, LocToRegClass(rl_src_new_value)); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1201 | |
| 1202 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 1203 | // Mark card for object assuming new value is stored. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1204 | FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). |
Vladimir Marko | 743b98c | 2014-11-24 19:45:41 +0000 | [diff] [blame] | 1205 | MarkGCCard(0, rl_new_value.reg, rl_object.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1206 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1207 | } |
| 1208 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1209 | RegLocation rl_offset; |
| 1210 | if (cu_->target64) { |
| 1211 | rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1212 | } else { |
| 1213 | rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 1214 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1215 | LoadValueDirect(rl_src_expected, rs_r0); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1216 | NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1217 | rl_new_value.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1218 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1219 | // After a store we need to insert barrier to prevent reordering with either |
| 1220 | // earlier or later memory accesses. Since |
| 1221 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1222 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1223 | GenMemBarrier(kAnyAny); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1224 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1225 | FreeTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1226 | } |
| 1227 | |
| 1228 | // Convert ZF to boolean |
| 1229 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 1230 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1231 | RegStorage result_reg = rl_result.reg; |
| 1232 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1233 | // For 32-bit, SETcc only works with EAX..EDX. |
| 1234 | if (!IsByteRegister(result_reg)) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1235 | result_reg = AllocateByteRegister(); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1236 | } |
| 1237 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); |
| 1238 | NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); |
| 1239 | if (IsTemp(result_reg)) { |
| 1240 | FreeTemp(result_reg); |
| 1241 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1242 | StoreValue(rl_dest, rl_result); |
| 1243 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1244 | } |
| 1245 | |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1246 | void X86Mir2Lir::SwapBits(RegStorage result_reg, int shift, int32_t value) { |
| 1247 | RegStorage r_temp = AllocTemp(); |
| 1248 | OpRegCopy(r_temp, result_reg); |
| 1249 | OpRegImm(kOpLsr, result_reg, shift); |
| 1250 | OpRegImm(kOpAnd, r_temp, value); |
| 1251 | OpRegImm(kOpAnd, result_reg, value); |
| 1252 | OpRegImm(kOpLsl, r_temp, shift); |
| 1253 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1254 | FreeTemp(r_temp); |
| 1255 | } |
| 1256 | |
| 1257 | void X86Mir2Lir::SwapBits64(RegStorage result_reg, int shift, int64_t value) { |
| 1258 | RegStorage r_temp = AllocTempWide(); |
| 1259 | OpRegCopy(r_temp, result_reg); |
| 1260 | OpRegImm(kOpLsr, result_reg, shift); |
| 1261 | RegStorage r_value = AllocTempWide(); |
| 1262 | LoadConstantWide(r_value, value); |
| 1263 | OpRegReg(kOpAnd, r_temp, r_value); |
| 1264 | OpRegReg(kOpAnd, result_reg, r_value); |
| 1265 | OpRegImm(kOpLsl, r_temp, shift); |
| 1266 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1267 | FreeTemp(r_temp); |
| 1268 | FreeTemp(r_value); |
| 1269 | } |
| 1270 | |
| 1271 | bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { |
Chao-ying Fu | ff87d7b | 2015-01-19 15:51:57 -0800 | [diff] [blame] | 1272 | RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); |
| 1273 | if (rl_dest.s_reg_low == INVALID_SREG) { |
| 1274 | // Result is unused, the code is dead. Inlining successful, no code generated. |
| 1275 | return true; |
| 1276 | } |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1277 | RegLocation rl_src_i = info->args[0]; |
| 1278 | RegLocation rl_i = (size == k64) ? LoadValueWide(rl_src_i, kCoreReg) |
| 1279 | : LoadValue(rl_src_i, kCoreReg); |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1280 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1281 | if (size == k64) { |
| 1282 | if (cu_->instruction_set == kX86_64) { |
| 1283 | /* Use one bswap instruction to reverse byte order first and then use 3 rounds of |
| 1284 | swapping bits to reverse bits in a long number x. Using bswap to save instructions |
| 1285 | compared to generic luni implementation which has 5 rounds of swapping bits. |
| 1286 | x = bswap x |
| 1287 | x = (x & 0x5555555555555555) << 1 | (x >> 1) & 0x5555555555555555; |
| 1288 | x = (x & 0x3333333333333333) << 2 | (x >> 2) & 0x3333333333333333; |
| 1289 | x = (x & 0x0F0F0F0F0F0F0F0F) << 4 | (x >> 4) & 0x0F0F0F0F0F0F0F0F; |
| 1290 | */ |
| 1291 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1292 | SwapBits64(rl_result.reg, 1, 0x5555555555555555); |
| 1293 | SwapBits64(rl_result.reg, 2, 0x3333333333333333); |
| 1294 | SwapBits64(rl_result.reg, 4, 0x0f0f0f0f0f0f0f0f); |
| 1295 | StoreValueWide(rl_dest, rl_result); |
| 1296 | return true; |
| 1297 | } |
| 1298 | RegStorage r_i_low = rl_i.reg.GetLow(); |
| 1299 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1300 | // First REV shall clobber rl_result.reg.GetLowReg(), save the value in a temp for the second |
| 1301 | // REV. |
| 1302 | r_i_low = AllocTemp(); |
| 1303 | OpRegCopy(r_i_low, rl_i.reg); |
| 1304 | } |
| 1305 | OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); |
| 1306 | OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); |
| 1307 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1308 | FreeTemp(r_i_low); |
| 1309 | } |
| 1310 | SwapBits(rl_result.reg.GetLow(), 1, 0x55555555); |
| 1311 | SwapBits(rl_result.reg.GetLow(), 2, 0x33333333); |
| 1312 | SwapBits(rl_result.reg.GetLow(), 4, 0x0f0f0f0f); |
| 1313 | SwapBits(rl_result.reg.GetHigh(), 1, 0x55555555); |
| 1314 | SwapBits(rl_result.reg.GetHigh(), 2, 0x33333333); |
| 1315 | SwapBits(rl_result.reg.GetHigh(), 4, 0x0f0f0f0f); |
| 1316 | StoreValueWide(rl_dest, rl_result); |
| 1317 | } else { |
| 1318 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1319 | SwapBits(rl_result.reg, 1, 0x55555555); |
| 1320 | SwapBits(rl_result.reg, 2, 0x33333333); |
| 1321 | SwapBits(rl_result.reg, 4, 0x0f0f0f0f); |
| 1322 | StoreValue(rl_dest, rl_result); |
| 1323 | } |
| 1324 | return true; |
| 1325 | } |
| 1326 | |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame^] | 1327 | // When we don't know the proper offset for the value, pick one that will force |
| 1328 | // 4 byte offset. We will fix this up in the assembler or linker later to have |
| 1329 | // the right value. |
| 1330 | static constexpr int kDummy32BitOffset = 256; |
| 1331 | |
Vladimir Marko | f6737f7 | 2015-03-23 17:05:14 +0000 | [diff] [blame] | 1332 | void X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Mark Mendell | 27dee8b | 2014-12-01 19:06:12 -0500 | [diff] [blame] | 1333 | if (cu_->target64) { |
| 1334 | // We can do this directly using RIP addressing. |
Mark Mendell | 27dee8b | 2014-12-01 19:06:12 -0500 | [diff] [blame] | 1335 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame^] | 1336 | LIR* res = NewLIR3(kX86Mov32RM, reg.GetReg(), kRIPReg, kDummy32BitOffset); |
Mark Mendell | 27dee8b | 2014-12-01 19:06:12 -0500 | [diff] [blame] | 1337 | res->target = target; |
| 1338 | res->flags.fixup = kFixupLoad; |
Vladimir Marko | f6737f7 | 2015-03-23 17:05:14 +0000 | [diff] [blame] | 1339 | return; |
Mark Mendell | 27dee8b | 2014-12-01 19:06:12 -0500 | [diff] [blame] | 1340 | } |
| 1341 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1342 | CHECK(base_of_code_ != nullptr); |
| 1343 | |
| 1344 | // Address the start of the method |
| 1345 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1346 | if (rl_method.wide) { |
| 1347 | LoadValueDirectWideFixed(rl_method, reg); |
| 1348 | } else { |
| 1349 | LoadValueDirectFixed(rl_method, reg); |
| 1350 | } |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1351 | store_method_addr_used_ = true; |
| 1352 | |
| 1353 | // Load the proper value from the literal area. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1354 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame^] | 1355 | LIR* res = NewLIR3(kX86Mov32RM, reg.GetReg(), reg.GetReg(), kDummy32BitOffset); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1356 | res->target = target; |
| 1357 | res->flags.fixup = kFixupLoad; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1358 | } |
| 1359 | |
Vladimir Marko | dc56cc5 | 2015-03-27 18:18:36 +0000 | [diff] [blame^] | 1360 | bool X86Mir2Lir::CanUseOpPcRelDexCacheArrayLoad() const { |
| 1361 | // TODO: Implement for 32-bit. |
| 1362 | return cu_->target64 && dex_cache_arrays_layout_.Valid(); |
| 1363 | } |
| 1364 | |
| 1365 | void X86Mir2Lir::OpPcRelDexCacheArrayLoad(const DexFile* dex_file, int offset, |
| 1366 | RegStorage r_dest) { |
| 1367 | if (cu_->target64) { |
| 1368 | LIR* mov = NewLIR3(kX86Mov32RM, r_dest.GetReg(), kRIPReg, kDummy32BitOffset); |
| 1369 | mov->flags.fixup = kFixupLabel; |
| 1370 | mov->operands[3] = WrapPointer(dex_file); |
| 1371 | mov->operands[4] = offset; |
| 1372 | dex_cache_access_insns_.push_back(mov); |
| 1373 | } else { |
| 1374 | // TODO: Implement for 32-bit. |
| 1375 | LOG(FATAL) << "Unimplemented."; |
| 1376 | UNREACHABLE(); |
| 1377 | } |
| 1378 | } |
| 1379 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1380 | LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1381 | UNUSED(r_base, count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1382 | LOG(FATAL) << "Unexpected use of OpVldm for x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1383 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1384 | } |
| 1385 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1386 | LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1387 | UNUSED(r_base, count); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1388 | LOG(FATAL) << "Unexpected use of OpVstm for x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1389 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1390 | } |
| 1391 | |
| 1392 | void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 1393 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1394 | int first_bit, int second_bit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1395 | UNUSED(lit); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1396 | RegStorage t_reg = AllocTemp(); |
| 1397 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 1398 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1399 | FreeTemp(t_reg); |
| 1400 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1401 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1402 | } |
| 1403 | } |
| 1404 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1405 | void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1406 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1407 | DCHECK(reg.Is64Bit()); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1408 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1409 | NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); |
| 1410 | } else { |
| 1411 | DCHECK(reg.IsPair()); |
| 1412 | |
| 1413 | // We are not supposed to clobber the incoming storage, so allocate a temporary. |
| 1414 | RegStorage t_reg = AllocTemp(); |
| 1415 | // Doing an OR is a quick way to check if both registers are zero. This will set the flags. |
| 1416 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
| 1417 | // The temp is no longer needed so free it at this time. |
| 1418 | FreeTemp(t_reg); |
| 1419 | } |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1420 | |
| 1421 | // In case of zero, throw ArithmeticException. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1422 | GenDivZeroCheck(kCondEq); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1423 | } |
| 1424 | |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1425 | void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, |
| 1426 | RegStorage array_base, |
| 1427 | int len_offset) { |
| 1428 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1429 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 1430 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch_in, |
| 1431 | RegStorage index_in, RegStorage array_base_in, int32_t len_offset_in) |
Vladimir Marko | 0b40ecf | 2015-03-20 12:08:03 +0000 | [diff] [blame] | 1432 | : LIRSlowPath(m2l, branch_in), |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 1433 | index_(index_in), array_base_(array_base_in), len_offset_(len_offset_in) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1434 | } |
| 1435 | |
| 1436 | void Compile() OVERRIDE { |
| 1437 | m2l_->ResetRegPool(); |
| 1438 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1439 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1440 | |
| 1441 | RegStorage new_index = index_; |
| 1442 | // Move index out of kArg1, either directly to kArg0, or to kArg2. |
Serguei Katkov | 4c7cc15 | 2014-06-24 00:50:02 +0700 | [diff] [blame] | 1443 | // TODO: clean-up to check not a number but with type |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1444 | if (index_ == m2l_->TargetReg(kArg1, kNotWide)) { |
| 1445 | if (array_base_ == m2l_->TargetReg(kArg0, kRef)) { |
| 1446 | m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kNotWide), index_); |
| 1447 | new_index = m2l_->TargetReg(kArg2, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1448 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1449 | m2l_->OpRegCopy(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1450 | new_index = m2l_->TargetReg(kArg0, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1451 | } |
| 1452 | } |
| 1453 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1454 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1455 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1456 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, new_index, |
| 1457 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1458 | } |
| 1459 | |
| 1460 | private: |
| 1461 | const RegStorage index_; |
| 1462 | const RegStorage array_base_; |
| 1463 | const int32_t len_offset_; |
| 1464 | }; |
| 1465 | |
| 1466 | OpRegMem(kOpCmp, index, array_base, len_offset); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1467 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1468 | LIR* branch = OpCondBranch(kCondUge, nullptr); |
| 1469 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1470 | index, array_base, len_offset)); |
| 1471 | } |
| 1472 | |
| 1473 | void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, |
| 1474 | RegStorage array_base, |
| 1475 | int32_t len_offset) { |
| 1476 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1477 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 1478 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch_in, |
| 1479 | int32_t index_in, RegStorage array_base_in, int32_t len_offset_in) |
Vladimir Marko | 0b40ecf | 2015-03-20 12:08:03 +0000 | [diff] [blame] | 1480 | : LIRSlowPath(m2l, branch_in), |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 1481 | index_(index_in), array_base_(array_base_in), len_offset_(len_offset_in) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | void Compile() OVERRIDE { |
| 1485 | m2l_->ResetRegPool(); |
| 1486 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1487 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1488 | |
| 1489 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1490 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1491 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1492 | x86_m2l->LoadConstant(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1493 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, m2l_->TargetReg(kArg0, kNotWide), |
| 1494 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1495 | } |
| 1496 | |
| 1497 | private: |
| 1498 | const int32_t index_; |
| 1499 | const RegStorage array_base_; |
| 1500 | const int32_t len_offset_; |
| 1501 | }; |
| 1502 | |
| 1503 | NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1504 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1505 | LIR* branch = OpCondBranch(kCondLs, nullptr); |
| 1506 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1507 | index, array_base, len_offset)); |
| 1508 | } |
| 1509 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1510 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1511 | LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1512 | if (cu_->target64) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1513 | OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); |
| 1514 | } else { |
| 1515 | OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); |
| 1516 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1517 | return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); |
| 1518 | } |
| 1519 | |
| 1520 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1521 | LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1522 | OpRegImm(kOpSub, reg, 1); |
Yixin Shou | a0dac3e | 2014-01-23 05:01:22 -0800 | [diff] [blame] | 1523 | return OpCondBranch(c_code, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1524 | } |
| 1525 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 1526 | bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1527 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1528 | UNUSED(dalvik_opcode, is_div, rl_src, rl_dest, lit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1529 | LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1530 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1531 | } |
| 1532 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1533 | bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1534 | UNUSED(rl_src, rl_dest, lit); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1535 | LOG(FATAL) << "Unexpected use of easyMultiply in x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1536 | UNREACHABLE(); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1537 | } |
| 1538 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1539 | LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1540 | UNUSED(cond, guide); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1541 | LOG(FATAL) << "Unexpected use of OpIT in x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1542 | UNREACHABLE(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1543 | } |
| 1544 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1545 | void X86Mir2Lir::OpEndIT(LIR* it) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1546 | UNUSED(it); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1547 | LOG(FATAL) << "Unexpected use of OpEndIT in x86"; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1548 | UNREACHABLE(); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1549 | } |
| 1550 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1551 | void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1552 | switch (val) { |
| 1553 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1554 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1555 | break; |
| 1556 | case 1: |
| 1557 | OpRegCopy(dest, src); |
| 1558 | break; |
| 1559 | default: |
| 1560 | OpRegRegImm(kOpMul, dest, src, val); |
| 1561 | break; |
| 1562 | } |
| 1563 | } |
| 1564 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1565 | void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1566 | UNUSED(sreg); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1567 | // All memory accesses below reference dalvik regs. |
| 1568 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1569 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1570 | LIR *m; |
| 1571 | switch (val) { |
| 1572 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1573 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1574 | break; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1575 | case 1: { |
| 1576 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
| 1577 | LoadBaseDisp(rs_rSP, displacement, dest, k32, kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1578 | break; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1579 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1580 | default: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1581 | m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1582 | rs_rX86_SP_32.GetReg(), displacement, val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1583 | AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); |
| 1584 | break; |
| 1585 | } |
| 1586 | } |
| 1587 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1588 | void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1589 | RegLocation rl_src2, int flags) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1590 | if (!cu_->target64) { |
| 1591 | // Some x86 32b ops are fallback. |
| 1592 | switch (opcode) { |
| 1593 | case Instruction::NOT_LONG: |
| 1594 | case Instruction::DIV_LONG: |
| 1595 | case Instruction::DIV_LONG_2ADDR: |
| 1596 | case Instruction::REM_LONG: |
| 1597 | case Instruction::REM_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1598 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1599 | return; |
| 1600 | |
| 1601 | default: |
| 1602 | // Everything else we can handle. |
| 1603 | break; |
| 1604 | } |
| 1605 | } |
| 1606 | |
| 1607 | switch (opcode) { |
| 1608 | case Instruction::NOT_LONG: |
| 1609 | GenNotLong(rl_dest, rl_src2); |
| 1610 | return; |
| 1611 | |
| 1612 | case Instruction::ADD_LONG: |
| 1613 | case Instruction::ADD_LONG_2ADDR: |
| 1614 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1615 | return; |
| 1616 | |
| 1617 | case Instruction::SUB_LONG: |
| 1618 | case Instruction::SUB_LONG_2ADDR: |
| 1619 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); |
| 1620 | return; |
| 1621 | |
| 1622 | case Instruction::MUL_LONG: |
| 1623 | case Instruction::MUL_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1624 | GenMulLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1625 | return; |
| 1626 | |
| 1627 | case Instruction::DIV_LONG: |
| 1628 | case Instruction::DIV_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1629 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1630 | return; |
| 1631 | |
| 1632 | case Instruction::REM_LONG: |
| 1633 | case Instruction::REM_LONG_2ADDR: |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1634 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1635 | return; |
| 1636 | |
| 1637 | case Instruction::AND_LONG_2ADDR: |
| 1638 | case Instruction::AND_LONG: |
| 1639 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1640 | return; |
| 1641 | |
| 1642 | case Instruction::OR_LONG: |
| 1643 | case Instruction::OR_LONG_2ADDR: |
| 1644 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1645 | return; |
| 1646 | |
| 1647 | case Instruction::XOR_LONG: |
| 1648 | case Instruction::XOR_LONG_2ADDR: |
| 1649 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1650 | return; |
| 1651 | |
| 1652 | case Instruction::NEG_LONG: |
| 1653 | GenNegLong(rl_dest, rl_src2); |
| 1654 | return; |
| 1655 | |
| 1656 | default: |
| 1657 | LOG(FATAL) << "Invalid long arith op"; |
| 1658 | return; |
| 1659 | } |
| 1660 | } |
| 1661 | |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1662 | bool X86Mir2Lir::GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val, int flags) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1663 | // All memory accesses below reference dalvik regs. |
| 1664 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1665 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1666 | if (val == 0) { |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1667 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1668 | if (cu_->target64) { |
| 1669 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1670 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1671 | OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); |
| 1672 | OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1673 | } |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1674 | StoreValueWide(rl_dest, rl_result); |
| 1675 | return true; |
| 1676 | } else if (val == 1) { |
| 1677 | StoreValueWide(rl_dest, rl_src1); |
| 1678 | return true; |
| 1679 | } else if (val == 2) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1680 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1681 | return true; |
| 1682 | } else if (IsPowerOfTwo(val)) { |
Andreas Gampe | 7e49992 | 2015-01-06 08:28:12 -0800 | [diff] [blame] | 1683 | int shift_amount = CTZ(val); |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1684 | if (!PartiallyIntersects(rl_src1, rl_dest)) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1685 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1686 | RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1687 | shift_amount, flags); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1688 | StoreValueWide(rl_dest, rl_result); |
| 1689 | return true; |
| 1690 | } |
| 1691 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1692 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1693 | // Okay, on 32b just bite the bullet and do it, still better than the general case. |
| 1694 | if (!cu_->target64) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1695 | int32_t val_lo = Low32Bits(val); |
| 1696 | int32_t val_hi = High32Bits(val); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 1697 | // Prepare for explicit register usage. |
| 1698 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1699 | rl_src1 = UpdateLocWideTyped(rl_src1); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1700 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1701 | int displacement = SRegOffset(rl_src1.s_reg_low); |
| 1702 | |
| 1703 | // ECX <- 1H * 2L |
| 1704 | // EAX <- 1L * 2H |
| 1705 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1706 | GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); |
| 1707 | GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1708 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1709 | GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); |
| 1710 | GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1711 | } |
| 1712 | |
| 1713 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1714 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1715 | |
| 1716 | // EAX <- 2L |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1717 | LoadConstantNoClobber(rs_r0, val_lo); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1718 | |
| 1719 | // EDX:EAX <- 2L * 1L (double precision) |
| 1720 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1721 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1722 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1723 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP_32.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1724 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1725 | true /* is_load */, true /* is_64bit */); |
| 1726 | } |
| 1727 | |
| 1728 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1729 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1730 | |
| 1731 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1732 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 1733 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1734 | StoreValueWide(rl_dest, rl_result); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1735 | return true; |
| 1736 | } |
| 1737 | return false; |
| 1738 | } |
| 1739 | |
| 1740 | void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1741 | RegLocation rl_src2, int flags) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1742 | if (rl_src1.is_const) { |
| 1743 | std::swap(rl_src1, rl_src2); |
| 1744 | } |
| 1745 | |
| 1746 | if (rl_src2.is_const) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 1747 | if (GenMulLongConst(rl_dest, rl_src1, mir_graph_->ConstantValueWide(rl_src2), flags)) { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1748 | return; |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | // All memory accesses below reference dalvik regs. |
| 1753 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1754 | |
| 1755 | if (cu_->target64) { |
| 1756 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1757 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1758 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1759 | if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1760 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1761 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 1762 | } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && |
| 1763 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1764 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); |
| 1765 | } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1766 | rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { |
| 1767 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1768 | } else { |
| 1769 | OpRegCopy(rl_result.reg, rl_src1.reg); |
| 1770 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1771 | } |
| 1772 | StoreValueWide(rl_dest, rl_result); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1773 | return; |
| 1774 | } |
| 1775 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1776 | // Not multiplying by a constant. Do it the hard way |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1777 | // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. |
| 1778 | bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 1779 | mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 1780 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 1781 | // Prepare for explicit register usage. |
| 1782 | ExplicitTempRegisterLock(this, 3, &rs_r0, &rs_r1, &rs_r2); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1783 | rl_src1 = UpdateLocWideTyped(rl_src1); |
| 1784 | rl_src2 = UpdateLocWideTyped(rl_src2); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1785 | |
| 1786 | // At this point, the VRs are in their home locations. |
| 1787 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1788 | bool src2_in_reg = rl_src2.location == kLocPhysReg; |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1789 | const RegStorage rs_rSP = cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1790 | |
| 1791 | // ECX <- 1H |
| 1792 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1793 | NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1794 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1795 | LoadBaseDisp(rs_rSP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1796 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1797 | } |
| 1798 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1799 | if (is_square) { |
| 1800 | // Take advantage of the fact that the values are the same. |
| 1801 | // ECX <- ECX * 2L (1H * 2L) |
| 1802 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1803 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1804 | } else { |
| 1805 | int displacement = SRegOffset(rl_src2.s_reg_low); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1806 | LIR* m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP_32.GetReg(), |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1807 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1808 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1809 | true /* is_load */, true /* is_64bit */); |
| 1810 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1811 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1812 | // ECX <- 2*ECX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1813 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1814 | } else { |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1815 | // EAX <- 2H |
| 1816 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1817 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1818 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1819 | LoadBaseDisp(rs_rSP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1820 | kNotVolatile); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1821 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1822 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1823 | // EAX <- EAX * 1L (2H * 1L) |
| 1824 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1825 | NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1826 | } else { |
| 1827 | int displacement = SRegOffset(rl_src1.s_reg_low); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1828 | LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP_32.GetReg(), |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1829 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1830 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1831 | true /* is_load */, true /* is_64bit */); |
| 1832 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1833 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1834 | // ECX <- ECX * 2L (1H * 2L) |
| 1835 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1836 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1837 | } else { |
| 1838 | int displacement = SRegOffset(rl_src2.s_reg_low); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1839 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP_32.GetReg(), |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1840 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1841 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1842 | true /* is_load */, true /* is_64bit */); |
| 1843 | } |
| 1844 | |
| 1845 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1846 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1847 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1848 | |
| 1849 | // EAX <- 2L |
| 1850 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1851 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1852 | } else { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1853 | LoadBaseDisp(rs_rSP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1854 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1855 | } |
| 1856 | |
| 1857 | // EDX:EAX <- 2L * 1L (double precision) |
| 1858 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1859 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1860 | } else { |
| 1861 | int displacement = SRegOffset(rl_src1.s_reg_low); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1862 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP_32.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1863 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1864 | true /* is_load */, true /* is_64bit */); |
| 1865 | } |
| 1866 | |
| 1867 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1868 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1869 | |
| 1870 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1871 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1872 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1873 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1874 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1875 | |
| 1876 | void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, |
| 1877 | Instruction::Code op) { |
| 1878 | DCHECK_EQ(rl_dest.location, kLocPhysReg); |
| 1879 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
| 1880 | if (rl_src.location == kLocPhysReg) { |
| 1881 | // Both operands are in registers. |
Serguei Katkov | ab5545f | 2014-03-25 10:51:15 +0700 | [diff] [blame] | 1882 | // But we must ensure that rl_src is in pair |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1883 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1884 | NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); |
| 1885 | } else { |
| 1886 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1887 | if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
| 1888 | // The registers are the same, so we would clobber it before the use. |
| 1889 | RegStorage temp_reg = AllocTemp(); |
| 1890 | OpRegCopy(temp_reg, rl_dest.reg); |
| 1891 | rl_src.reg.SetHighReg(temp_reg.GetReg()); |
| 1892 | } |
| 1893 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1894 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1895 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1896 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1897 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1898 | return; |
| 1899 | } |
| 1900 | |
| 1901 | // RHS is in memory. |
| 1902 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 1903 | (rl_src.location == kLocCompilerTemp)); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1904 | int r_base = rs_rX86_SP_32.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1905 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 1906 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1907 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1908 | LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), |
| 1909 | r_base, displacement + LOWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1910 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 1911 | true /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1912 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1913 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1914 | lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1915 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1916 | true /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1917 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1918 | } |
| 1919 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1920 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1921 | rl_dest = UpdateLocWideTyped(rl_dest); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1922 | if (rl_dest.location == kLocPhysReg) { |
| 1923 | // Ensure we are in a register pair |
| 1924 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1925 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1926 | rl_src = UpdateLocWideTyped(rl_src); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1927 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1928 | StoreFinalValueWide(rl_dest, rl_result); |
| 1929 | return; |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1930 | } else if (!cu_->target64 && Intersects(rl_src, rl_dest)) { |
| 1931 | // Handle the case when src and dest are intersect. |
| 1932 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1933 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 1934 | rl_src = UpdateLocWideTyped(rl_src); |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 1935 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1936 | StoreFinalValueWide(rl_dest, rl_result); |
| 1937 | return; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1938 | } |
| 1939 | |
| 1940 | // It wasn't in registers, so it better be in memory. |
| 1941 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1942 | (rl_dest.location == kLocCompilerTemp)); |
| 1943 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1944 | |
| 1945 | // Operate directly into memory. |
| 1946 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 1947 | int r_base = rs_rX86_SP_32.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1948 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1949 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1950 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1951 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1952 | cu_->target64 ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1953 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1954 | true /* is_load */, true /* is64bit */); |
| 1955 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1956 | false /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1957 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1958 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1959 | lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1960 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1961 | true /* is_load */, true /* is64bit */); |
| 1962 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1963 | false /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1964 | } |
nikolay serdjuk | 6b9356c | 2014-11-13 18:15:23 +0600 | [diff] [blame] | 1965 | |
| 1966 | int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low); |
| 1967 | int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); |
| 1968 | |
| 1969 | // If the left operand is in memory and the right operand is in a register |
| 1970 | // and both belong to the same dalvik register then we should clobber the |
| 1971 | // right one because it doesn't hold valid data anymore. |
| 1972 | if (v_src_reg == v_dst_reg) { |
| 1973 | Clobber(rl_src.reg); |
| 1974 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1975 | } |
| 1976 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1977 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, |
| 1978 | RegLocation rl_src2, Instruction::Code op, |
| 1979 | bool is_commutative) { |
| 1980 | // Is this really a 2 operand operation? |
| 1981 | switch (op) { |
| 1982 | case Instruction::ADD_LONG_2ADDR: |
| 1983 | case Instruction::SUB_LONG_2ADDR: |
| 1984 | case Instruction::AND_LONG_2ADDR: |
| 1985 | case Instruction::OR_LONG_2ADDR: |
| 1986 | case Instruction::XOR_LONG_2ADDR: |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 1987 | if (GenerateTwoOperandInstructions()) { |
| 1988 | GenLongArith(rl_dest, rl_src2, op); |
| 1989 | return; |
| 1990 | } |
| 1991 | break; |
| 1992 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1993 | default: |
| 1994 | break; |
| 1995 | } |
| 1996 | |
| 1997 | if (rl_dest.location == kLocPhysReg) { |
| 1998 | RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); |
| 1999 | |
| 2000 | // We are about to clobber the LHS, so it needs to be a temp. |
| 2001 | rl_result = ForceTempWide(rl_result); |
| 2002 | |
| 2003 | // Perform the operation using the RHS. |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2004 | rl_src2 = UpdateLocWideTyped(rl_src2); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2005 | GenLongRegOrMemOp(rl_result, rl_src2, op); |
| 2006 | |
| 2007 | // And now record that the result is in the temp. |
| 2008 | StoreFinalValueWide(rl_dest, rl_result); |
| 2009 | return; |
| 2010 | } |
| 2011 | |
| 2012 | // It wasn't in registers, so it better be in memory. |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2013 | DCHECK((rl_dest.location == kLocDalvikFrame) || (rl_dest.location == kLocCompilerTemp)); |
| 2014 | rl_src1 = UpdateLocWideTyped(rl_src1); |
| 2015 | rl_src2 = UpdateLocWideTyped(rl_src2); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2016 | |
| 2017 | // Get one of the source operands into temporary register. |
| 2018 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2019 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2020 | if (IsTemp(rl_src1.reg)) { |
| 2021 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 2022 | } else if (is_commutative) { |
| 2023 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 2024 | // We need at least one of them to be a temporary. |
| 2025 | if (!IsTemp(rl_src2.reg)) { |
| 2026 | rl_src1 = ForceTempWide(rl_src1); |
| 2027 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 2028 | } else { |
| 2029 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 2030 | StoreFinalValueWide(rl_dest, rl_src2); |
| 2031 | return; |
| 2032 | } |
| 2033 | } else { |
| 2034 | // Need LHS to be the temp. |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2035 | rl_src1 = ForceTempWide(rl_src1); |
Yevgeny Rouban | 91b6ffa | 2014-03-07 14:35:44 +0700 | [diff] [blame] | 2036 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2037 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2038 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2039 | if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 2040 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 2041 | } else if (is_commutative) { |
| 2042 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 2043 | // We need at least one of them to be a temporary. |
| 2044 | if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { |
| 2045 | rl_src1 = ForceTempWide(rl_src1); |
| 2046 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 2047 | } else { |
| 2048 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 2049 | StoreFinalValueWide(rl_dest, rl_src2); |
| 2050 | return; |
| 2051 | } |
| 2052 | } else { |
| 2053 | // Need LHS to be the temp. |
| 2054 | rl_src1 = ForceTempWide(rl_src1); |
| 2055 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 2056 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2057 | } |
| 2058 | |
| 2059 | StoreFinalValueWide(rl_dest, rl_src1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2060 | } |
| 2061 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2062 | void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2063 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2064 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2065 | RegLocation rl_result; |
| 2066 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2067 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 2068 | OpReg(kOpNot, rl_result.reg); |
| 2069 | StoreValueWide(rl_dest, rl_result); |
| 2070 | } else { |
| 2071 | LOG(FATAL) << "Unexpected use GenNotLong()"; |
| 2072 | } |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2073 | } |
| 2074 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2075 | void X86Mir2Lir::GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, |
| 2076 | int64_t imm, bool is_div) { |
| 2077 | if (imm == 0) { |
| 2078 | GenDivZeroException(); |
| 2079 | } else if (imm == 1) { |
| 2080 | if (is_div) { |
| 2081 | // x / 1 == x. |
| 2082 | StoreValueWide(rl_dest, rl_src); |
| 2083 | } else { |
| 2084 | // x % 1 == 0. |
| 2085 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2086 | LoadConstantWide(rl_result.reg, 0); |
| 2087 | StoreValueWide(rl_dest, rl_result); |
| 2088 | } |
| 2089 | } else if (imm == -1) { // handle 0x8000000000000000 / -1 special case. |
| 2090 | if (is_div) { |
| 2091 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2092 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2093 | RegStorage rs_temp = AllocTempWide(); |
| 2094 | |
| 2095 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 2096 | LoadConstantWide(rs_temp, 0x8000000000000000); |
| 2097 | |
| 2098 | // If x == MIN_LONG, return MIN_LONG. |
| 2099 | OpRegReg(kOpCmp, rl_src.reg, rs_temp); |
| 2100 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 2101 | |
| 2102 | // For x != MIN_LONG, x / -1 == -x. |
| 2103 | OpReg(kOpNeg, rl_result.reg); |
| 2104 | |
| 2105 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2106 | FreeTemp(rs_temp); |
| 2107 | StoreValueWide(rl_dest, rl_result); |
| 2108 | } else { |
| 2109 | // x % -1 == 0. |
| 2110 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2111 | LoadConstantWide(rl_result.reg, 0); |
| 2112 | StoreValueWide(rl_dest, rl_result); |
| 2113 | } |
| 2114 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 2115 | // Division using shifting. |
| 2116 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2117 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2118 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 2119 | RegStorage rs_temp = AllocTypedTempWide(false, kCoreReg); |
| 2120 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 2121 | } |
| 2122 | LoadConstantWide(rl_result.reg, std::abs(imm) - 1); |
| 2123 | OpRegReg(kOpAdd, rl_result.reg, rl_src.reg); |
| 2124 | NewLIR2(kX86Test64RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 2125 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
Andreas Gampe | 7e49992 | 2015-01-06 08:28:12 -0800 | [diff] [blame] | 2126 | int shift_amount = CTZ(imm); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2127 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 2128 | if (imm < 0) { |
| 2129 | OpReg(kOpNeg, rl_result.reg); |
| 2130 | } |
| 2131 | StoreValueWide(rl_dest, rl_result); |
| 2132 | } else { |
| 2133 | CHECK(imm <= -2 || imm >= 2); |
| 2134 | |
| 2135 | FlushReg(rs_r0q); |
| 2136 | Clobber(rs_r0q); |
| 2137 | LockTemp(rs_r0q); |
| 2138 | FlushReg(rs_r2q); |
| 2139 | Clobber(rs_r2q); |
| 2140 | LockTemp(rs_r2q); |
| 2141 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2142 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 2143 | is_div ? rs_r2q : rs_r0q, INVALID_SREG, INVALID_SREG}; |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2144 | |
| 2145 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 2146 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 2147 | int64_t magic; |
| 2148 | int shift; |
| 2149 | CalculateMagicAndShift(imm, magic, shift, true /* is_long */); |
| 2150 | |
| 2151 | /* |
| 2152 | * For imm >= 2, |
| 2153 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 2154 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 2155 | * For imm <= -2, |
| 2156 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 2157 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 2158 | * We implement this algorithm in the following way: |
| 2159 | * 1. multiply magic number m and numerator n, get the higher 64bit result in RDX |
| 2160 | * 2. if imm > 0 and magic < 0, add numerator to RDX |
| 2161 | * if imm < 0 and magic > 0, sub numerator from RDX |
| 2162 | * 3. if S !=0, SAR S bits for RDX |
| 2163 | * 4. add 1 to RDX if RDX < 0 |
| 2164 | * 5. Thus, RDX is the quotient |
| 2165 | */ |
| 2166 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2167 | // RAX = magic. |
| 2168 | LoadConstantWide(rs_r0q, magic); |
| 2169 | |
| 2170 | // Multiply by numerator. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2171 | RegStorage numerator_reg; |
| 2172 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 2173 | // We will need the value later. |
| 2174 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2175 | numerator_reg = rl_src.reg; |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2176 | |
| 2177 | // RDX:RAX = magic * numerator. |
| 2178 | NewLIR1(kX86Imul64DaR, numerator_reg.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2179 | } else { |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2180 | // Only need this once. Multiply directly from the value. |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2181 | rl_src = UpdateLocWideTyped(rl_src); |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2182 | if (rl_src.location != kLocPhysReg) { |
| 2183 | // Okay, we can do this from memory. |
| 2184 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2185 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 2186 | // RDX:RAX = magic * numerator. |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2187 | LIR *m = NewLIR2(kX86Imul64DaM, rs_rX86_SP_32.GetReg(), displacement); |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2188 | AnnotateDalvikRegAccess(m, displacement >> 2, |
| 2189 | true /* is_load */, true /* is_64bit */); |
| 2190 | } else { |
| 2191 | // RDX:RAX = magic * numerator. |
| 2192 | NewLIR1(kX86Imul64DaR, rl_src.reg.GetReg()); |
| 2193 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2194 | } |
| 2195 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2196 | if (imm > 0 && magic < 0) { |
| 2197 | // Add numerator to RDX. |
| 2198 | DCHECK(numerator_reg.Valid()); |
| 2199 | OpRegReg(kOpAdd, rs_r2q, numerator_reg); |
| 2200 | } else if (imm < 0 && magic > 0) { |
| 2201 | DCHECK(numerator_reg.Valid()); |
| 2202 | OpRegReg(kOpSub, rs_r2q, numerator_reg); |
| 2203 | } |
| 2204 | |
| 2205 | // Do we need the shift? |
| 2206 | if (shift != 0) { |
| 2207 | // Shift RDX by 'shift' bits. |
| 2208 | OpRegImm(kOpAsr, rs_r2q, shift); |
| 2209 | } |
| 2210 | |
| 2211 | // Move RDX to RAX. |
| 2212 | OpRegCopyWide(rs_r0q, rs_r2q); |
| 2213 | |
| 2214 | // Move sign bit to bit 0, zeroing the rest. |
| 2215 | OpRegImm(kOpLsr, rs_r2q, 63); |
| 2216 | |
| 2217 | // RDX = RDX + RAX. |
| 2218 | OpRegReg(kOpAdd, rs_r2q, rs_r0q); |
| 2219 | |
| 2220 | // Quotient is in RDX. |
| 2221 | if (!is_div) { |
| 2222 | // We need to compute the remainder. |
| 2223 | // Remainder is divisor - (quotient * imm). |
| 2224 | DCHECK(numerator_reg.Valid()); |
| 2225 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2226 | |
| 2227 | // Imul doesn't support 64-bit imms. |
| 2228 | if (imm > std::numeric_limits<int32_t>::max() || |
| 2229 | imm < std::numeric_limits<int32_t>::min()) { |
| 2230 | RegStorage rs_temp = AllocTempWide(); |
| 2231 | LoadConstantWide(rs_temp, imm); |
| 2232 | |
| 2233 | // RAX = numerator * imm. |
| 2234 | NewLIR2(kX86Imul64RR, rs_r2q.GetReg(), rs_temp.GetReg()); |
| 2235 | |
| 2236 | FreeTemp(rs_temp); |
| 2237 | } else { |
| 2238 | // RAX = numerator * imm. |
| 2239 | int short_imm = static_cast<int>(imm); |
| 2240 | NewLIR3(kX86Imul64RRI, rs_r2q.GetReg(), rs_r2q.GetReg(), short_imm); |
| 2241 | } |
| 2242 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2243 | // RAX -= RDX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2244 | OpRegReg(kOpSub, rs_r0q, rs_r2q); |
| 2245 | |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2246 | // Result in RAX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2247 | } else { |
Mark Mendell | 3a91f44 | 2014-09-02 12:44:24 -0400 | [diff] [blame] | 2248 | // Result in RDX. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2249 | } |
| 2250 | StoreValueWide(rl_dest, rl_result); |
| 2251 | FreeTemp(rs_r0q); |
| 2252 | FreeTemp(rs_r2q); |
| 2253 | } |
| 2254 | } |
| 2255 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2256 | void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2257 | RegLocation rl_src2, bool is_div, int flags) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2258 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2259 | LOG(FATAL) << "Unexpected use GenDivRemLong()"; |
| 2260 | return; |
| 2261 | } |
| 2262 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2263 | if (rl_src2.is_const) { |
| 2264 | DCHECK(rl_src2.wide); |
| 2265 | int64_t imm = mir_graph_->ConstantValueWide(rl_src2); |
| 2266 | GenDivRemLongLit(rl_dest, rl_src1, imm, is_div); |
| 2267 | return; |
| 2268 | } |
| 2269 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2270 | // We have to use fixed registers, so flush all the temps. |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2271 | // Prepare for explicit register usage. |
| 2272 | ExplicitTempRegisterLock(this, 4, &rs_r0q, &rs_r1q, &rs_r2q, &rs_r6q); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2273 | |
| 2274 | // Load LHS into RAX. |
| 2275 | LoadValueDirectWideFixed(rl_src1, rs_r0q); |
| 2276 | |
| 2277 | // Load RHS into RCX. |
| 2278 | LoadValueDirectWideFixed(rl_src2, rs_r1q); |
| 2279 | |
| 2280 | // Copy LHS sign bit into RDX. |
| 2281 | NewLIR0(kx86Cqo64Da); |
| 2282 | |
| 2283 | // Handle division by zero case. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2284 | if ((flags & MIR_IGNORE_DIV_ZERO_CHECK) == 0) { |
| 2285 | GenDivZeroCheckWide(rs_r1q); |
| 2286 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2287 | |
| 2288 | // Have to catch 0x8000000000000000/-1 case, or we will get an exception! |
| 2289 | NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2290 | LIR* minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2291 | |
| 2292 | // RHS is -1. |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2293 | LoadConstantWide(rs_r6q, 0x8000000000000000); |
| 2294 | NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r6q.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2295 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2296 | |
| 2297 | // In 0x8000000000000000/-1 case. |
| 2298 | if (!is_div) { |
| 2299 | // For DIV, RAX is already right. For REM, we need RDX 0. |
| 2300 | NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); |
| 2301 | } |
| 2302 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 2303 | |
| 2304 | // Expected case. |
| 2305 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2306 | minint_branch->target = minus_one_branch->target; |
| 2307 | NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); |
| 2308 | done->target = NewLIR0(kPseudoTargetLabel); |
| 2309 | |
| 2310 | // Result is in RAX for div and RDX for rem. |
| 2311 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; |
| 2312 | if (!is_div) { |
| 2313 | rl_result.reg.SetReg(r2q); |
| 2314 | } |
| 2315 | |
| 2316 | StoreValueWide(rl_dest, rl_result); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2317 | } |
| 2318 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2319 | void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2320 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2321 | RegLocation rl_result; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2322 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2323 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2324 | OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); |
| 2325 | } else { |
| 2326 | rl_result = ForceTempWide(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2327 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow |
| 2328 | OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF |
| 2329 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2330 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2331 | StoreValueWide(rl_dest, rl_result); |
| 2332 | } |
| 2333 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2334 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 2335 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 2336 | X86OpCode opcode = kX86Bkpt; |
| 2337 | switch (op) { |
| 2338 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2339 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2340 | default: |
| 2341 | LOG(FATAL) << "Bad opcode: " << op; |
| 2342 | break; |
| 2343 | } |
| 2344 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
| 2345 | } |
| 2346 | |
| 2347 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { |
| 2348 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2349 | X86OpCode opcode = kX86Bkpt; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2350 | if (cu_->target64 && r_dest.Is64BitSolo()) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 2351 | switch (op) { |
| 2352 | case kOpCmp: opcode = kX86Cmp64RT; break; |
| 2353 | case kOpMov: opcode = kX86Mov64RT; break; |
| 2354 | default: |
| 2355 | LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; |
| 2356 | break; |
| 2357 | } |
| 2358 | } else { |
| 2359 | switch (op) { |
| 2360 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2361 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2362 | default: |
| 2363 | LOG(FATAL) << "Bad opcode: " << op; |
| 2364 | break; |
| 2365 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2366 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2367 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2368 | } |
| 2369 | |
| 2370 | /* |
| 2371 | * Generate array load |
| 2372 | */ |
| 2373 | void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2374 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
Mark Mendell | ca54134 | 2014-10-15 16:59:49 -0400 | [diff] [blame] | 2375 | RegisterClass reg_class = RegClassForFieldLoadStore(size, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2376 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2377 | RegLocation rl_result; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2378 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2379 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2380 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2381 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2382 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2383 | } else { |
| 2384 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2385 | } |
| 2386 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2387 | bool constant_index = rl_index.is_const; |
| 2388 | int32_t constant_index_value = 0; |
| 2389 | if (!constant_index) { |
| 2390 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2391 | } else { |
| 2392 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2393 | // If index is constant, just fold it into the data offset |
| 2394 | data_offset += constant_index_value << scale; |
| 2395 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2396 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2397 | } |
| 2398 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2399 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2400 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2401 | |
| 2402 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2403 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2404 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2405 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2406 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2407 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2408 | } |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2409 | rl_result = EvalLoc(rl_dest, reg_class, true); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2410 | LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2411 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2412 | StoreValueWide(rl_dest, rl_result); |
| 2413 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2414 | StoreValue(rl_dest, rl_result); |
| 2415 | } |
| 2416 | } |
| 2417 | |
| 2418 | /* |
| 2419 | * Generate array store |
| 2420 | * |
| 2421 | */ |
| 2422 | void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2423 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
Mark Mendell | ca54134 | 2014-10-15 16:59:49 -0400 | [diff] [blame] | 2424 | RegisterClass reg_class = RegClassForFieldLoadStore(size, false); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2425 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 2426 | int data_offset; |
| 2427 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2428 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2429 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2430 | } else { |
| 2431 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2432 | } |
| 2433 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2434 | rl_array = LoadValue(rl_array, kRefReg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2435 | bool constant_index = rl_index.is_const; |
| 2436 | int32_t constant_index_value = 0; |
| 2437 | if (!constant_index) { |
| 2438 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2439 | } else { |
| 2440 | // If index is constant, just fold it into the data offset |
| 2441 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2442 | data_offset += constant_index_value << scale; |
| 2443 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2444 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2445 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2446 | |
| 2447 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2448 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2449 | |
| 2450 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2451 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2452 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2453 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2454 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2455 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2456 | } |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2457 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2458 | rl_src = LoadValueWide(rl_src, reg_class); |
| 2459 | } else { |
| 2460 | rl_src = LoadValue(rl_src, reg_class); |
| 2461 | } |
| 2462 | // If the src reg can't be byte accessed, move it to a temp first. |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2463 | if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2464 | RegStorage temp = AllocTemp(); |
| 2465 | OpRegCopy(temp, rl_src.reg); |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 2466 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2467 | } else { |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 2468 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2469 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2470 | if (card_mark) { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 2471 | // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2472 | if (!constant_index) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2473 | FreeTemp(rl_index.reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2474 | } |
Vladimir Marko | 743b98c | 2014-11-24 19:45:41 +0000 | [diff] [blame] | 2475 | MarkGCCard(opt_flags, rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2476 | } |
| 2477 | } |
| 2478 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2479 | RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2480 | RegLocation rl_src, int shift_amount, int flags) { |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2481 | UNUSED(flags); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2482 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2483 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2484 | OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ |
| 2485 | switch (opcode) { |
| 2486 | case Instruction::SHL_LONG: |
| 2487 | case Instruction::SHL_LONG_2ADDR: |
| 2488 | op = kOpLsl; |
| 2489 | break; |
| 2490 | case Instruction::SHR_LONG: |
| 2491 | case Instruction::SHR_LONG_2ADDR: |
| 2492 | op = kOpAsr; |
| 2493 | break; |
| 2494 | case Instruction::USHR_LONG: |
| 2495 | case Instruction::USHR_LONG_2ADDR: |
| 2496 | op = kOpLsr; |
| 2497 | break; |
| 2498 | default: |
| 2499 | LOG(FATAL) << "Unexpected case"; |
| 2500 | } |
| 2501 | OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); |
| 2502 | } else { |
| 2503 | switch (opcode) { |
| 2504 | case Instruction::SHL_LONG: |
| 2505 | case Instruction::SHL_LONG_2ADDR: |
| 2506 | DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. |
| 2507 | if (shift_amount == 32) { |
| 2508 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2509 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2510 | } else if (shift_amount > 31) { |
| 2511 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2512 | NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); |
| 2513 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2514 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2515 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2516 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2517 | NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), |
| 2518 | shift_amount); |
| 2519 | NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); |
| 2520 | } |
| 2521 | break; |
| 2522 | case Instruction::SHR_LONG: |
| 2523 | case Instruction::SHR_LONG_2ADDR: |
| 2524 | if (shift_amount == 32) { |
| 2525 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2526 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2527 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2528 | } else if (shift_amount > 31) { |
| 2529 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2530 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2531 | NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2532 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2533 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2534 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2535 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2536 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2537 | shift_amount); |
| 2538 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2539 | } |
| 2540 | break; |
| 2541 | case Instruction::USHR_LONG: |
| 2542 | case Instruction::USHR_LONG_2ADDR: |
| 2543 | if (shift_amount == 32) { |
| 2544 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2545 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2546 | } else if (shift_amount > 31) { |
| 2547 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2548 | NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2549 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2550 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2551 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2552 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2553 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2554 | shift_amount); |
| 2555 | NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2556 | } |
| 2557 | break; |
| 2558 | default: |
| 2559 | LOG(FATAL) << "Unexpected case"; |
| 2560 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2561 | } |
| 2562 | return rl_result; |
| 2563 | } |
| 2564 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2565 | void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2566 | RegLocation rl_src, RegLocation rl_shift, int flags) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2567 | // Per spec, we only care about low 6 bits of shift amount. |
| 2568 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 2569 | if (shift_amount == 0) { |
| 2570 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2571 | StoreValueWide(rl_dest, rl_src); |
| 2572 | return; |
| 2573 | } else if (shift_amount == 1 && |
| 2574 | (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { |
| 2575 | // Need to handle this here to avoid calling StoreValueWide twice. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2576 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src, flags); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2577 | return; |
| 2578 | } |
Alexei Zavjalov | d8c3e36 | 2014-10-08 15:51:59 +0700 | [diff] [blame] | 2579 | if (PartiallyIntersects(rl_src, rl_dest)) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2580 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 2581 | return; |
| 2582 | } |
| 2583 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2584 | RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount, flags); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2585 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2586 | } |
| 2587 | |
| 2588 | void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2589 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 2590 | int flags) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2591 | bool isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2592 | switch (opcode) { |
| 2593 | case Instruction::ADD_LONG: |
| 2594 | case Instruction::AND_LONG: |
| 2595 | case Instruction::OR_LONG: |
| 2596 | case Instruction::XOR_LONG: |
| 2597 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2598 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2599 | } else { |
| 2600 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2601 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2602 | } |
| 2603 | break; |
| 2604 | case Instruction::SUB_LONG: |
| 2605 | case Instruction::SUB_LONG_2ADDR: |
| 2606 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2607 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2608 | } else { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2609 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2610 | isConstSuccess = true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2611 | } |
| 2612 | break; |
| 2613 | case Instruction::ADD_LONG_2ADDR: |
| 2614 | case Instruction::OR_LONG_2ADDR: |
| 2615 | case Instruction::XOR_LONG_2ADDR: |
| 2616 | case Instruction::AND_LONG_2ADDR: |
| 2617 | if (rl_src2.is_const) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2618 | if (GenerateTwoOperandInstructions()) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2619 | isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2620 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2621 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2622 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2623 | } else { |
| 2624 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2625 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2626 | } |
| 2627 | break; |
| 2628 | default: |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2629 | isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2630 | break; |
| 2631 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2632 | |
| 2633 | if (!isConstSuccess) { |
| 2634 | // Default - bail to non-const handler. |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 2635 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2636 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2637 | } |
| 2638 | |
| 2639 | bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { |
| 2640 | switch (op) { |
| 2641 | case Instruction::AND_LONG_2ADDR: |
| 2642 | case Instruction::AND_LONG: |
| 2643 | return value == -1; |
| 2644 | case Instruction::OR_LONG: |
| 2645 | case Instruction::OR_LONG_2ADDR: |
| 2646 | case Instruction::XOR_LONG: |
| 2647 | case Instruction::XOR_LONG_2ADDR: |
| 2648 | return value == 0; |
| 2649 | default: |
| 2650 | return false; |
| 2651 | } |
| 2652 | } |
| 2653 | |
| 2654 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 2655 | bool is_high_op) { |
| 2656 | bool rhs_in_mem = rhs.location != kLocPhysReg; |
| 2657 | bool dest_in_mem = dest.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2658 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2659 | DCHECK(!rhs_in_mem || !dest_in_mem); |
| 2660 | switch (op) { |
| 2661 | case Instruction::ADD_LONG: |
| 2662 | case Instruction::ADD_LONG_2ADDR: |
| 2663 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2664 | return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2665 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2666 | return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2667 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2668 | return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2669 | case Instruction::SUB_LONG: |
| 2670 | case Instruction::SUB_LONG_2ADDR: |
| 2671 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2672 | return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2673 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2674 | return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2675 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2676 | return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2677 | case Instruction::AND_LONG_2ADDR: |
| 2678 | case Instruction::AND_LONG: |
| 2679 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2680 | return is64Bit ? kX86And64MR : kX86And32MR; |
| 2681 | } |
| 2682 | if (is64Bit) { |
| 2683 | return rhs_in_mem ? kX86And64RM : kX86And64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2684 | } |
| 2685 | return rhs_in_mem ? kX86And32RM : kX86And32RR; |
| 2686 | case Instruction::OR_LONG: |
| 2687 | case Instruction::OR_LONG_2ADDR: |
| 2688 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2689 | return is64Bit ? kX86Or64MR : kX86Or32MR; |
| 2690 | } |
| 2691 | if (is64Bit) { |
| 2692 | return rhs_in_mem ? kX86Or64RM : kX86Or64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2693 | } |
| 2694 | return rhs_in_mem ? kX86Or32RM : kX86Or32RR; |
| 2695 | case Instruction::XOR_LONG: |
| 2696 | case Instruction::XOR_LONG_2ADDR: |
| 2697 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2698 | return is64Bit ? kX86Xor64MR : kX86Xor32MR; |
| 2699 | } |
| 2700 | if (is64Bit) { |
| 2701 | return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2702 | } |
| 2703 | return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; |
| 2704 | default: |
| 2705 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2706 | return kX86Add32RR; |
| 2707 | } |
| 2708 | } |
| 2709 | |
| 2710 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, |
| 2711 | int32_t value) { |
| 2712 | bool in_mem = loc.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2713 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2714 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2715 | DCHECK(in_mem || !loc.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2716 | switch (op) { |
| 2717 | case Instruction::ADD_LONG: |
| 2718 | case Instruction::ADD_LONG_2ADDR: |
| 2719 | if (byte_imm) { |
| 2720 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2721 | return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2722 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2723 | return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2724 | } |
| 2725 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2726 | return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2727 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2728 | return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2729 | case Instruction::SUB_LONG: |
| 2730 | case Instruction::SUB_LONG_2ADDR: |
| 2731 | if (byte_imm) { |
| 2732 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2733 | return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2734 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2735 | return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2736 | } |
| 2737 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2738 | return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2739 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2740 | return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2741 | case Instruction::AND_LONG_2ADDR: |
| 2742 | case Instruction::AND_LONG: |
| 2743 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2744 | if (is64Bit) { |
| 2745 | return in_mem ? kX86And64MI8 : kX86And64RI8; |
| 2746 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2747 | return in_mem ? kX86And32MI8 : kX86And32RI8; |
| 2748 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2749 | if (is64Bit) { |
| 2750 | return in_mem ? kX86And64MI : kX86And64RI; |
| 2751 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2752 | return in_mem ? kX86And32MI : kX86And32RI; |
| 2753 | case Instruction::OR_LONG: |
| 2754 | case Instruction::OR_LONG_2ADDR: |
| 2755 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2756 | if (is64Bit) { |
| 2757 | return in_mem ? kX86Or64MI8 : kX86Or64RI8; |
| 2758 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2759 | return in_mem ? kX86Or32MI8 : kX86Or32RI8; |
| 2760 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2761 | if (is64Bit) { |
| 2762 | return in_mem ? kX86Or64MI : kX86Or64RI; |
| 2763 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2764 | return in_mem ? kX86Or32MI : kX86Or32RI; |
| 2765 | case Instruction::XOR_LONG: |
| 2766 | case Instruction::XOR_LONG_2ADDR: |
| 2767 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2768 | if (is64Bit) { |
| 2769 | return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; |
| 2770 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2771 | return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; |
| 2772 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2773 | if (is64Bit) { |
| 2774 | return in_mem ? kX86Xor64MI : kX86Xor64RI; |
| 2775 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2776 | return in_mem ? kX86Xor32MI : kX86Xor32RI; |
| 2777 | default: |
| 2778 | LOG(FATAL) << "Unexpected opcode: " << op; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2779 | UNREACHABLE(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2780 | } |
| 2781 | } |
| 2782 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2783 | bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2784 | DCHECK(rl_src.is_const); |
| 2785 | int64_t val = mir_graph_->ConstantValueWide(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2786 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2787 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2788 | // We can do with imm only if it fits 32 bit |
| 2789 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2790 | return false; |
| 2791 | } |
| 2792 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2793 | rl_dest = UpdateLocWideTyped(rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2794 | |
| 2795 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2796 | (rl_dest.location == kLocCompilerTemp)) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2797 | int r_base = rs_rX86_SP_32.GetReg(); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2798 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2799 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2800 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2801 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
| 2802 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); |
| 2803 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2804 | true /* is_load */, true /* is64bit */); |
| 2805 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2806 | false /* is_load */, true /* is64bit */); |
| 2807 | return true; |
| 2808 | } |
| 2809 | |
| 2810 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2811 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
| 2812 | DCHECK(!rl_result.reg.IsFloat()); |
| 2813 | |
| 2814 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2815 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2816 | |
| 2817 | StoreValueWide(rl_dest, rl_result); |
| 2818 | return true; |
| 2819 | } |
| 2820 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2821 | int32_t val_lo = Low32Bits(val); |
| 2822 | int32_t val_hi = High32Bits(val); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2823 | rl_dest = UpdateLocWideTyped(rl_dest); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2824 | |
| 2825 | // Can we just do this into memory? |
| 2826 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2827 | (rl_dest.location == kLocCompilerTemp)) { |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 2828 | int r_base = rs_rX86_SP_32.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2829 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2830 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2831 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2832 | if (!IsNoOp(op, val_lo)) { |
| 2833 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2834 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2835 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2836 | true /* is_load */, true /* is64bit */); |
| 2837 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2838 | false /* is_load */, true /* is64bit */); |
| 2839 | } |
| 2840 | if (!IsNoOp(op, val_hi)) { |
| 2841 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2842 | LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2843 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2844 | true /* is_load */, true /* is64bit */); |
| 2845 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2846 | false /* is_load */, true /* is64bit */); |
| 2847 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2848 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2849 | } |
| 2850 | |
| 2851 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2852 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2853 | DCHECK(!rl_result.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2854 | |
| 2855 | if (!IsNoOp(op, val_lo)) { |
| 2856 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2857 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2858 | } |
| 2859 | if (!IsNoOp(op, val_hi)) { |
| 2860 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2861 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2862 | } |
| 2863 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2864 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2865 | } |
| 2866 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2867 | bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2868 | RegLocation rl_src2, Instruction::Code op) { |
| 2869 | DCHECK(rl_src2.is_const); |
| 2870 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2871 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2872 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2873 | // We can do with imm only if it fits 32 bit |
| 2874 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2875 | return false; |
| 2876 | } |
| 2877 | if (rl_dest.location == kLocPhysReg && |
| 2878 | rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { |
| 2879 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2880 | OpRegCopy(rl_dest.reg, rl_src1.reg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2881 | NewLIR2(x86op, rl_dest.reg.GetReg(), val); |
| 2882 | StoreFinalValueWide(rl_dest, rl_dest); |
| 2883 | return true; |
| 2884 | } |
| 2885 | |
| 2886 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2887 | // We need the values to be in a temporary |
| 2888 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2889 | |
| 2890 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2891 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2892 | |
| 2893 | StoreFinalValueWide(rl_dest, rl_result); |
| 2894 | return true; |
| 2895 | } |
| 2896 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2897 | int32_t val_lo = Low32Bits(val); |
| 2898 | int32_t val_hi = High32Bits(val); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 2899 | rl_dest = UpdateLocWideTyped(rl_dest); |
| 2900 | rl_src1 = UpdateLocWideTyped(rl_src1); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2901 | |
| 2902 | // Can we do this directly into the destination registers? |
| 2903 | if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2904 | rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2905 | rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2906 | if (!IsNoOp(op, val_lo)) { |
| 2907 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2908 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2909 | } |
| 2910 | if (!IsNoOp(op, val_hi)) { |
| 2911 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2912 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2913 | } |
Maxim Kazantsev | 653f2bf | 2014-02-13 15:11:17 +0700 | [diff] [blame] | 2914 | |
| 2915 | StoreFinalValueWide(rl_dest, rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2916 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2917 | } |
| 2918 | |
| 2919 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2920 | DCHECK_EQ(rl_src1.location, kLocPhysReg); |
| 2921 | |
| 2922 | // We need the values to be in a temporary |
| 2923 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2924 | if (!IsNoOp(op, val_lo)) { |
| 2925 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2926 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2927 | } |
| 2928 | if (!IsNoOp(op, val_hi)) { |
| 2929 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2930 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2931 | } |
| 2932 | |
| 2933 | StoreFinalValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2934 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2935 | } |
| 2936 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2937 | // For final classes there are no sub-classes to check and so we can answer the instance-of |
| 2938 | // question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. |
| 2939 | void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, |
| 2940 | RegLocation rl_dest, RegLocation rl_src) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2941 | RegLocation object = LoadValue(rl_src, kRefReg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2942 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2943 | RegStorage result_reg = rl_result.reg; |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2944 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2945 | // For 32-bit, SETcc only works with EAX..EDX. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2946 | RegStorage object_32reg = object.reg.Is64Bit() ? As32BitReg(object.reg) : object.reg; |
Dmitry Petrochenko | 407f5c1 | 2014-07-01 01:21:38 +0700 | [diff] [blame] | 2947 | if (result_reg.GetRegNum() == object_32reg.GetRegNum() || !IsByteRegister(result_reg)) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2948 | result_reg = AllocateByteRegister(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2949 | } |
| 2950 | |
| 2951 | // Assume that there is no match. |
| 2952 | LoadConstant(result_reg, 0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2953 | LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2954 | |
Mark Mendell | ade54a2 | 2014-06-09 12:49:55 -0400 | [diff] [blame] | 2955 | // We will use this register to compare to memory below. |
| 2956 | // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). |
| 2957 | // For this reason, force allocation of a 32 bit register to use, so that the |
| 2958 | // compare to memory will be done using a 32 bit comparision. |
| 2959 | // The LoadRefDisp(s) below will work normally, even in 64 bit mode. |
| 2960 | RegStorage check_class = AllocTemp(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2961 | |
| 2962 | // If Method* is already in a register, we can save a copy. |
| 2963 | RegLocation rl_method = mir_graph_->GetMethodLoc(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2964 | int32_t offset_of_type = mirror::Array::DataOffset( |
| 2965 | sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + |
| 2966 | (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2967 | |
| 2968 | if (rl_method.location == kLocPhysReg) { |
| 2969 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2970 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2971 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2972 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2973 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2974 | check_class, kNotVolatile); |
| 2975 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2976 | } |
| 2977 | } else { |
| 2978 | LoadCurrMethodDirect(check_class); |
| 2979 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2980 | LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2981 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2982 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2983 | LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2984 | check_class, kNotVolatile); |
| 2985 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2986 | } |
| 2987 | } |
| 2988 | |
| 2989 | // Compare the computed class to the class in the object. |
| 2990 | DCHECK_EQ(object.location, kLocPhysReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2991 | OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2992 | |
| 2993 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2994 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2995 | |
| 2996 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 2997 | null_branchover->target = target; |
| 2998 | FreeTemp(check_class); |
| 2999 | if (IsTemp(result_reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3000 | OpRegCopy(rl_result.reg, result_reg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 3001 | FreeTemp(result_reg); |
| 3002 | } |
| 3003 | StoreValue(rl_dest, rl_result); |
| 3004 | } |
| 3005 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3006 | void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 3007 | RegLocation rl_lhs, RegLocation rl_rhs, int flags) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3008 | OpKind op = kOpBkpt; |
| 3009 | bool is_div_rem = false; |
| 3010 | bool unary = false; |
| 3011 | bool shift_op = false; |
| 3012 | bool is_two_addr = false; |
| 3013 | RegLocation rl_result; |
| 3014 | switch (opcode) { |
| 3015 | case Instruction::NEG_INT: |
| 3016 | op = kOpNeg; |
| 3017 | unary = true; |
| 3018 | break; |
| 3019 | case Instruction::NOT_INT: |
| 3020 | op = kOpMvn; |
| 3021 | unary = true; |
| 3022 | break; |
| 3023 | case Instruction::ADD_INT_2ADDR: |
| 3024 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3025 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3026 | case Instruction::ADD_INT: |
| 3027 | op = kOpAdd; |
| 3028 | break; |
| 3029 | case Instruction::SUB_INT_2ADDR: |
| 3030 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3031 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3032 | case Instruction::SUB_INT: |
| 3033 | op = kOpSub; |
| 3034 | break; |
| 3035 | case Instruction::MUL_INT_2ADDR: |
| 3036 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3037 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3038 | case Instruction::MUL_INT: |
| 3039 | op = kOpMul; |
| 3040 | break; |
| 3041 | case Instruction::DIV_INT_2ADDR: |
| 3042 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3043 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3044 | case Instruction::DIV_INT: |
| 3045 | op = kOpDiv; |
| 3046 | is_div_rem = true; |
| 3047 | break; |
| 3048 | /* NOTE: returns in kArg1 */ |
| 3049 | case Instruction::REM_INT_2ADDR: |
| 3050 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3051 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3052 | case Instruction::REM_INT: |
| 3053 | op = kOpRem; |
| 3054 | is_div_rem = true; |
| 3055 | break; |
| 3056 | case Instruction::AND_INT_2ADDR: |
| 3057 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3058 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3059 | case Instruction::AND_INT: |
| 3060 | op = kOpAnd; |
| 3061 | break; |
| 3062 | case Instruction::OR_INT_2ADDR: |
| 3063 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3064 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3065 | case Instruction::OR_INT: |
| 3066 | op = kOpOr; |
| 3067 | break; |
| 3068 | case Instruction::XOR_INT_2ADDR: |
| 3069 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3070 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3071 | case Instruction::XOR_INT: |
| 3072 | op = kOpXor; |
| 3073 | break; |
| 3074 | case Instruction::SHL_INT_2ADDR: |
| 3075 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3076 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3077 | case Instruction::SHL_INT: |
| 3078 | shift_op = true; |
| 3079 | op = kOpLsl; |
| 3080 | break; |
| 3081 | case Instruction::SHR_INT_2ADDR: |
| 3082 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3083 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3084 | case Instruction::SHR_INT: |
| 3085 | shift_op = true; |
| 3086 | op = kOpAsr; |
| 3087 | break; |
| 3088 | case Instruction::USHR_INT_2ADDR: |
| 3089 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3090 | FALLTHROUGH_INTENDED; |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3091 | case Instruction::USHR_INT: |
| 3092 | shift_op = true; |
| 3093 | op = kOpLsr; |
| 3094 | break; |
| 3095 | default: |
| 3096 | LOG(FATAL) << "Invalid word arith op: " << opcode; |
| 3097 | } |
| 3098 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3099 | // Can we convert to a two address instruction? |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3100 | if (!is_two_addr && |
| 3101 | (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3102 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3103 | is_two_addr = true; |
| 3104 | } |
| 3105 | |
| 3106 | if (!GenerateTwoOperandInstructions()) { |
| 3107 | is_two_addr = false; |
| 3108 | } |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3109 | |
| 3110 | // Get the div/rem stuff out of the way. |
| 3111 | if (is_div_rem) { |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame] | 3112 | rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, flags); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3113 | StoreValue(rl_dest, rl_result); |
| 3114 | return; |
| 3115 | } |
| 3116 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3117 | // If we generate any memory access below, it will reference a dalvik reg. |
| 3118 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 3119 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3120 | if (unary) { |
| 3121 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3122 | rl_result = UpdateLocTyped(rl_dest); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3123 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3124 | OpRegReg(op, rl_result.reg, rl_lhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3125 | } else { |
| 3126 | if (shift_op) { |
| 3127 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3128 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3129 | LoadValueDirectFixed(rl_rhs, t_reg); |
| 3130 | if (is_two_addr) { |
| 3131 | // Can we do this directly into memory? |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3132 | rl_result = UpdateLocTyped(rl_dest); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3133 | if (rl_result.location != kLocPhysReg) { |
| 3134 | // Okay, we can do this into memory |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3135 | OpMemReg(op, rl_result, t_reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3136 | FreeTemp(t_reg); |
| 3137 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3138 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3139 | // Can do this directly into the result register |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3140 | OpRegReg(op, rl_result.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3141 | FreeTemp(t_reg); |
| 3142 | StoreFinalValue(rl_dest, rl_result); |
| 3143 | return; |
| 3144 | } |
| 3145 | } |
| 3146 | // Three address form, or we can't do directly. |
| 3147 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3148 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3149 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3150 | FreeTemp(t_reg); |
| 3151 | } else { |
| 3152 | // Multiply is 3 operand only (sort of). |
| 3153 | if (is_two_addr && op != kOpMul) { |
| 3154 | // Can we do this directly into memory? |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3155 | rl_result = UpdateLocTyped(rl_dest); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3156 | if (rl_result.location == kLocPhysReg) { |
Serguei Katkov | 366f8ae | 2014-04-15 16:55:26 +0700 | [diff] [blame] | 3157 | // Ensure res is in a core reg |
| 3158 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3159 | // Can we do this from memory directly? |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3160 | rl_rhs = UpdateLocTyped(rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3161 | if (rl_rhs.location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3162 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3163 | StoreFinalValue(rl_dest, rl_result); |
| 3164 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3165 | } else if (!rl_rhs.reg.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3166 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3167 | StoreFinalValue(rl_dest, rl_result); |
| 3168 | return; |
| 3169 | } |
| 3170 | } |
| 3171 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
Serguei Katkov | d293fb4 | 2014-05-19 15:45:42 +0700 | [diff] [blame] | 3172 | // It might happen rl_rhs and rl_dest are the same VR |
| 3173 | // in this case rl_dest is in reg after LoadValue while |
| 3174 | // rl_result is not updated yet, so do this |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3175 | rl_result = UpdateLocTyped(rl_dest); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3176 | if (rl_result.location != kLocPhysReg) { |
| 3177 | // Okay, we can do this into memory. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 3178 | OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3179 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3180 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3181 | // Can do this directly into the result register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3182 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3183 | StoreFinalValue(rl_dest, rl_result); |
| 3184 | return; |
| 3185 | } else { |
| 3186 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3187 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3188 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3189 | } |
| 3190 | } else { |
| 3191 | // Try to use reg/memory instructions. |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3192 | rl_lhs = UpdateLocTyped(rl_lhs); |
| 3193 | rl_rhs = UpdateLocTyped(rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3194 | // We can't optimize with FP registers. |
| 3195 | if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { |
| 3196 | // Something is difficult, so fall back to the standard case. |
| 3197 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3198 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3199 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3200 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3201 | } else { |
| 3202 | // We can optimize by moving to result and using memory operands. |
| 3203 | if (rl_rhs.location != kLocPhysReg) { |
| 3204 | // Force LHS into result. |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3205 | // We should be careful with order here |
| 3206 | // If rl_dest and rl_lhs points to the same VR we should load first |
| 3207 | // If the are different we should find a register first for dest |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3208 | if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3209 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3210 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3211 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3212 | // No-op if these are the same. |
| 3213 | OpRegCopy(rl_result.reg, rl_lhs.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3214 | } else { |
| 3215 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3216 | LoadValueDirect(rl_lhs, rl_result.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3217 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3218 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3219 | } else if (rl_lhs.location != kLocPhysReg) { |
| 3220 | // RHS is in a register; LHS is in memory. |
| 3221 | if (op != kOpSub) { |
| 3222 | // Force RHS into result and operate on memory. |
| 3223 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3224 | OpRegCopy(rl_result.reg, rl_rhs.reg); |
| 3225 | OpRegMem(op, rl_result.reg, rl_lhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3226 | } else { |
| 3227 | // Subtraction isn't commutative. |
| 3228 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3229 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3230 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3231 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3232 | } |
| 3233 | } else { |
| 3234 | // Both are in registers. |
| 3235 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3236 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3237 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3238 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3239 | } |
| 3240 | } |
| 3241 | } |
| 3242 | } |
| 3243 | } |
| 3244 | StoreValue(rl_dest, rl_result); |
| 3245 | } |
| 3246 | |
| 3247 | bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { |
| 3248 | // If we have non-core registers, then we can't do good things. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3249 | if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3250 | return false; |
| 3251 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3252 | if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3253 | return false; |
| 3254 | } |
| 3255 | |
| 3256 | // Everything will be fine :-). |
| 3257 | return true; |
| 3258 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3259 | |
| 3260 | void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3261 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3262 | Mir2Lir::GenIntToLong(rl_dest, rl_src); |
| 3263 | return; |
| 3264 | } |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3265 | rl_src = UpdateLocTyped(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3266 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 3267 | if (rl_src.location == kLocPhysReg) { |
| 3268 | NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 3269 | } else { |
| 3270 | int displacement = SRegOffset(rl_src.s_reg_low); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3271 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Ian Rogers | b28c1c0 | 2014-11-08 11:21:21 -0800 | [diff] [blame] | 3272 | LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP_32.GetReg(), |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3273 | displacement + LOWORD_OFFSET); |
| 3274 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 3275 | true /* is_load */, true /* is_64bit */); |
| 3276 | } |
| 3277 | StoreValueWide(rl_dest, rl_result); |
| 3278 | } |
| 3279 | |
Yevgeny Rouban | 6af8206 | 2014-11-26 18:11:54 +0600 | [diff] [blame] | 3280 | void X86Mir2Lir::GenLongToInt(RegLocation rl_dest, RegLocation rl_src) { |
| 3281 | rl_src = UpdateLocWide(rl_src); |
| 3282 | rl_src = NarrowRegLoc(rl_src); |
| 3283 | StoreValue(rl_dest, rl_src); |
| 3284 | |
| 3285 | if (cu_->target64) { |
| 3286 | // if src and dest are in the same phys reg then StoreValue generates |
| 3287 | // no operation but we need explicit 32-bit mov R, R to clear |
| 3288 | // the higher 32-bits |
| 3289 | rl_dest = UpdateLoc(rl_dest); |
| 3290 | if (rl_src.location == kLocPhysReg && rl_dest.location == kLocPhysReg |
| 3291 | && IsSameReg(rl_src.reg, rl_dest.reg)) { |
| 3292 | LIR* copy_lir = OpRegCopyNoInsert(rl_dest.reg, rl_dest.reg); |
| 3293 | // remove nop flag set by OpRegCopyNoInsert if src == dest |
| 3294 | copy_lir->flags.is_nop = false; |
| 3295 | AppendLIR(copy_lir); |
| 3296 | } |
| 3297 | } |
| 3298 | } |
| 3299 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3300 | void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 3301 | RegLocation rl_src1, RegLocation rl_shift) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3302 | if (!cu_->target64) { |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 3303 | // Long shift operations in 32-bit. Use shld or shrd to create a 32-bit register filled from |
| 3304 | // the other half, shift the other half, if the shift amount is less than 32 we're done, |
| 3305 | // otherwise move one register to the other and place zero or sign bits in the other. |
| 3306 | LIR* branch; |
| 3307 | FlushAllRegs(); |
| 3308 | LockCallTemps(); |
| 3309 | LoadValueDirectFixed(rl_shift, rs_rCX); |
| 3310 | RegStorage r_tmp = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 3311 | LoadValueDirectWideFixed(rl_src1, r_tmp); |
| 3312 | switch (opcode) { |
| 3313 | case Instruction::SHL_LONG: |
| 3314 | case Instruction::SHL_LONG_2ADDR: |
| 3315 | NewLIR3(kX86Shld32RRC, r_tmp.GetHighReg(), r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3316 | NewLIR2(kX86Sal32RC, r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3317 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3318 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3319 | OpRegCopy(r_tmp.GetHigh(), r_tmp.GetLow()); |
| 3320 | LoadConstant(r_tmp.GetLow(), 0); |
| 3321 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3322 | break; |
| 3323 | case Instruction::SHR_LONG: |
| 3324 | case Instruction::SHR_LONG_2ADDR: |
| 3325 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3326 | NewLIR2(kX86Sar32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3327 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3328 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3329 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3330 | NewLIR2(kX86Sar32RI, r_tmp.GetHighReg(), 31); |
| 3331 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3332 | break; |
| 3333 | case Instruction::USHR_LONG: |
| 3334 | case Instruction::USHR_LONG_2ADDR: |
| 3335 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), |
| 3336 | rs_rCX.GetReg()); |
| 3337 | NewLIR2(kX86Shr32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3338 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3339 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3340 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3341 | LoadConstant(r_tmp.GetHigh(), 0); |
| 3342 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3343 | break; |
| 3344 | default: |
| 3345 | LOG(FATAL) << "Unexpected case: " << opcode; |
| 3346 | return; |
| 3347 | } |
| 3348 | RegLocation rl_result = LocCReturnWide(); |
| 3349 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3350 | return; |
| 3351 | } |
| 3352 | |
| 3353 | bool is_two_addr = false; |
| 3354 | OpKind op = kOpBkpt; |
| 3355 | RegLocation rl_result; |
| 3356 | |
| 3357 | switch (opcode) { |
| 3358 | case Instruction::SHL_LONG_2ADDR: |
| 3359 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3360 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3361 | case Instruction::SHL_LONG: |
| 3362 | op = kOpLsl; |
| 3363 | break; |
| 3364 | case Instruction::SHR_LONG_2ADDR: |
| 3365 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3366 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3367 | case Instruction::SHR_LONG: |
| 3368 | op = kOpAsr; |
| 3369 | break; |
| 3370 | case Instruction::USHR_LONG_2ADDR: |
| 3371 | is_two_addr = true; |
Ian Rogers | fc787ec | 2014-10-09 21:56:44 -0700 | [diff] [blame] | 3372 | FALLTHROUGH_INTENDED; |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3373 | case Instruction::USHR_LONG: |
| 3374 | op = kOpLsr; |
| 3375 | break; |
| 3376 | default: |
| 3377 | op = kOpBkpt; |
| 3378 | } |
| 3379 | |
| 3380 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3381 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3382 | LoadValueDirectFixed(rl_shift, t_reg); |
| 3383 | if (is_two_addr) { |
| 3384 | // Can we do this directly into memory? |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 3385 | rl_result = UpdateLocWideTyped(rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3386 | if (rl_result.location != kLocPhysReg) { |
| 3387 | // Okay, we can do this into memory |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3388 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3389 | OpMemReg(op, rl_result, t_reg.GetReg()); |
| 3390 | } else if (!rl_result.reg.IsFloat()) { |
| 3391 | // Can do this directly into the result register |
| 3392 | OpRegReg(op, rl_result.reg, t_reg); |
| 3393 | StoreFinalValueWide(rl_dest, rl_result); |
| 3394 | } |
| 3395 | } else { |
| 3396 | // Three address form, or we can't do directly. |
| 3397 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 3398 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 3399 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); |
| 3400 | StoreFinalValueWide(rl_dest, rl_result); |
| 3401 | } |
| 3402 | |
| 3403 | FreeTemp(t_reg); |
| 3404 | } |
| 3405 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 3406 | } // namespace art |